1.1 --- a/pkg/devices/lib/dma/include/dma-jz4730.h Tue Oct 24 17:22:51 2023 +0200
1.2 +++ b/pkg/devices/lib/dma/include/dma-jz4730.h Tue Oct 24 17:32:54 2023 +0200
1.3 @@ -1,7 +1,7 @@
1.4 /*
1.5 * DMA support for the JZ4730.
1.6 *
1.7 - * Copyright (C) 2021 Paul Boddie <paul@boddie.org.uk>
1.8 + * Copyright (C) 2021, 2023 Paul Boddie <paul@boddie.org.uk>
1.9 *
1.10 * This program is free software; you can redistribute it and/or
1.11 * modify it under the terms of the GNU General Public License as
1.12 @@ -28,7 +28,7 @@
1.13
1.14 /* Enumerated types for various transfer parameters. */
1.15
1.16 -enum Dma_jz4730_request_type : unsigned
1.17 +enum Dma_jz4730_request_type
1.18 {
1.19 Dma_request_external = 0,
1.20 Dma_request_pcmcia_out = 4,
1.21 @@ -53,19 +53,19 @@
1.22 Dma_request_ost2_underflow = 28,
1.23 };
1.24
1.25 -enum Dma_jz4730_ext_level : unsigned
1.26 +enum Dma_jz4730_ext_level
1.27 {
1.28 Dma_ext_active_high = 0,
1.29 Dma_ext_active_low = 1,
1.30 };
1.31
1.32 -enum Dma_jz4730_ext_output_mode_cycle : unsigned
1.33 +enum Dma_jz4730_ext_output_mode_cycle
1.34 {
1.35 Dma_ext_output_mode_read_cycle = 0,
1.36 Dma_ext_output_mode_write_cycle = 1,
1.37 };
1.38
1.39 -enum Dma_jz4730_ext_req_detect_mode : unsigned
1.40 +enum Dma_jz4730_ext_req_detect_mode
1.41 {
1.42 Dma_ext_req_detect_mode_low_level = 0,
1.43 Dma_ext_req_detect_mode_falling_edge = 1,
1.44 @@ -73,15 +73,6 @@
1.45 Dma_ext_req_detect_mode_rising_edge = 3,
1.46 };
1.47
1.48 -enum Dma_jz4730_trans_unit_size : unsigned
1.49 -{
1.50 - Dma_trans_unit_size_32_bit = 0,
1.51 - Dma_trans_unit_size_8_bit = 1,
1.52 - Dma_trans_unit_size_16_bit = 2,
1.53 - Dma_trans_unit_size_16_byte = 3,
1.54 - Dma_trans_unit_size_32_byte = 4,
1.55 -};
1.56 -
1.57
1.58
1.59 #ifdef __cplusplus
1.60 @@ -103,7 +94,7 @@
1.61 Hw::Register_block<32> _regs;
1.62 Dma_jz4730_chip *_chip;
1.63 uint8_t _channel;
1.64 - l4_cap_idx_t _irq=L4_INVALID_CAP;
1.65 + l4_cap_idx_t _irq = L4_INVALID_CAP;
1.66
1.67 // External transfer properties with defaults.
1.68
1.69 @@ -117,9 +108,13 @@
1.70
1.71 unsigned int transfer(uint32_t source, uint32_t destination,
1.72 unsigned int count,
1.73 - enum Dma_jz4730_trans_unit_size size,
1.74 + bool source_increment, bool destination_increment,
1.75 + uint8_t source_width, uint8_t destination_width,
1.76 + uint8_t transfer_unit_size,
1.77 enum Dma_jz4730_request_type type=Dma_request_auto);
1.78
1.79 + unsigned int wait();
1.80 +
1.81 // External transfer property configuration.
1.82
1.83 void set_output_polarity(enum Dma_jz4730_ext_level polarity)
1.84 @@ -139,15 +134,13 @@
1.85
1.86 uint32_t encode_external_transfer(enum Dma_jz4730_request_type type);
1.87
1.88 - uint32_t encode_source_address_increment(enum Dma_jz4730_request_type type);
1.89 -
1.90 - uint32_t encode_destination_address_increment(enum Dma_jz4730_request_type type);
1.91 -
1.92 uint32_t encode_req_detect_int_length(uint8_t units);
1.93
1.94 - uint32_t encode_source_port_width(enum Dma_jz4730_request_type type);
1.95 + uint32_t encode_source_port_width(uint8_t width);
1.96
1.97 - uint32_t encode_destination_port_width(enum Dma_jz4730_request_type type);
1.98 + uint32_t encode_destination_port_width(uint8_t width);
1.99 +
1.100 + uint32_t encode_transfer_unit_size(uint8_t size);
1.101
1.102 // Transaction control.
1.103
1.104 @@ -209,9 +202,14 @@
1.105
1.106 void jz4730_dma_set_req_detect_mode(void *dma_channel, enum Dma_jz4730_ext_req_detect_mode mode);
1.107
1.108 -unsigned int jz4730_dma_transfer(void *dma_channel, uint32_t source,
1.109 - uint32_t destination, unsigned int count,
1.110 - enum Dma_jz4730_trans_unit_size size,
1.111 - enum Dma_jz4730_request_type type);
1.112 +unsigned int jz4730_dma_transfer(void *dma_channel,
1.113 + uint32_t source, uint32_t destination,
1.114 + unsigned int count,
1.115 + int source_increment, int destination_increment,
1.116 + uint8_t source_width, uint8_t destination_width,
1.117 + uint8_t transfer_unit_size,
1.118 + enum Dma_jz4730_request_type type);
1.119 +
1.120 +unsigned int jz4730_dma_wait(void *dma_channel);
1.121
1.122 EXTERN_C_END