1.1 --- a/pkg/landfall-examples/qi_lb60_lcd/jzlcd.h Tue May 29 22:26:18 2018 +0200
1.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000
1.3 @@ -1,236 +0,0 @@
1.4 -/*
1.5 - * U-Boot and jz4740 LCD controller definitions.
1.6 - *
1.7 - * Copyright (C) 2001 Wolfgang Denk, DENX Software Engineering, wd@denx.de.
1.8 - * Copyright (C) 2005-2007, Ingenic Semiconductor Inc.
1.9 - * Copyright (C) 2009 Qi Hardware Inc.
1.10 - * Author: Xiangfu Liu <xiangfu@sharism.cc>
1.11 - * Copyright (C) Xiangfu Liu <xiangfu@sharism.cc>
1.12 - * Copyright (C) 2015, 2016, 2017, 2018 Paul Boddie <paul@boddie.org.uk>
1.13 - *
1.14 - * This program is free software; you can redistribute it and/or
1.15 - * modify it under the terms of the GNU General Public License as
1.16 - * published by the Free Software Foundation; either version 2 of
1.17 - * the License, or (at your option) any later version.
1.18 - *
1.19 - * This program is distributed in the hope that it will be useful,
1.20 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
1.21 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1.22 - * GNU General Public License for more details.
1.23 - *
1.24 - * You should have received a copy of the GNU General Public License
1.25 - * along with this program; if not, write to the Free Software
1.26 - * Foundation, Inc., 51 Franklin Street, Fifth Floor,
1.27 - * Boston, MA 02110-1301, USA
1.28 - */
1.29 -
1.30 -#ifndef __JZLCD_H__
1.31 -#define __JZLCD_H__
1.32 -
1.33 -#include <stdint.h>
1.34 -
1.35 -/* Framebuffer characteristics. */
1.36 -
1.37 -struct jzfb_info {
1.38 - uint32_t cfg; /* panel mode and pin usage etc. */
1.39 - uint32_t w; /* display width in pixels */
1.40 - uint32_t h; /* display height in pixels */
1.41 - uint32_t bpp; /* bits per pixel */
1.42 - uint32_t fclk; /* frame clock */
1.43 - uint32_t hsw; /* hsync width, in pixel clock */
1.44 - uint32_t vsw; /* vsync width, in line count */
1.45 - uint32_t elw; /* end of line, in pixel clock */
1.46 - uint32_t blw; /* begin of line, in pixel clock */
1.47 - uint32_t efw; /* end of frame, in line count */
1.48 - uint32_t bfw; /* begin of frame, in line count */
1.49 -};
1.50 -
1.51 -/* LCD controller stucture for jz4740. */
1.52 -
1.53 -struct jz_fb_dma_descriptor {
1.54 - struct jz_fb_dma_descriptor *fdadr; /* frame descriptor address register */
1.55 - uint32_t fsadr; /* frame source address register */
1.56 - uint32_t fidr; /* frame identifier register */
1.57 - uint32_t ldcmd; /* command register */
1.58 -};
1.59 -
1.60 -/* Display characteristics and memory resources. */
1.61 -
1.62 -typedef struct vidinfo {
1.63 - struct jzfb_info *jz_fb; /* framebuffer and panel properties */
1.64 - void *lcd; /* address of LCD controller registers */
1.65 -} vidinfo_t;
1.66 -
1.67 -
1.68 -
1.69 -/* Public functions. */
1.70 -
1.71 -uint32_t jz4740_lcd_get_aligned_size(vidinfo_t *vid);
1.72 -uint32_t jz4740_lcd_get_descriptors_size(vidinfo_t *vid);
1.73 -uint32_t jz4740_lcd_get_line_size(vidinfo_t *vid);
1.74 -uint32_t jz4740_lcd_get_screen_size(vidinfo_t *vid);
1.75 -uint32_t jz4740_lcd_get_pixel_clock(vidinfo_t *vid);
1.76 -
1.77 -void jz4740_lcd_set_base(vidinfo_t *vid, void *lcd_base);
1.78 -
1.79 -void jz4740_lcd_ctrl_init(
1.80 - struct jz_fb_dma_descriptor *desc_vaddr,
1.81 - struct jz_fb_dma_descriptor *desc_paddr,
1.82 - void *fb_vaddr, void *fb_paddr,
1.83 - vidinfo_t *vid);
1.84 -
1.85 -void jz4740_lcd_hw_init(vidinfo_t *vid);
1.86 -void jz4740_lcd_set_bpp(uint8_t bpp, vidinfo_t *vid);
1.87 -void jz4740_lcd_enable(vidinfo_t *vid);
1.88 -void jz4740_lcd_disable(vidinfo_t *vid);
1.89 -void jz4740_lcd_quick_disable(vidinfo_t *vid);
1.90 -
1.91 -
1.92 -
1.93 -/* Alignment/rounding macros. */
1.94 -
1.95 -#define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1)
1.96 -#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask))
1.97 -
1.98 -/* Display device mode select (LCD_CFG.MODE). */
1.99 -
1.100 -#define MODE_MASK 0x0f
1.101 -#define MODE_TFT_GEN 0x00
1.102 -#define MODE_TFT_SHARP 0x01
1.103 -#define MODE_TFT_CASIO 0x02
1.104 -#define MODE_TFT_SAMSUNG 0x03
1.105 -#define MODE_CCIR656_NONINT 0x04
1.106 -#define MODE_CCIR656_INT 0x05
1.107 -#define MODE_STN_COLOR_SINGLE 0x08
1.108 -#define MODE_STN_MONO_SINGLE 0x09
1.109 -#define MODE_STN_COLOR_DUAL 0x0a
1.110 -#define MODE_STN_MONO_DUAL 0x0b
1.111 -#define MODE_8BIT_SERIAL_TFT 0x0c
1.112 -
1.113 -/* 16-bit or 18-bit TFT panel selection (LCD_CFG.18/16). */
1.114 -
1.115 -#define MODE_TFT_18BIT (1<<7)
1.116 -
1.117 -/* STN pin utilisation (LCD_CFG.PDW). */
1.118 -
1.119 -#define STN_DAT_PIN1 (0x00 << 4)
1.120 -#define STN_DAT_PIN2 (0x01 << 4)
1.121 -#define STN_DAT_PIN4 (0x02 << 4)
1.122 -#define STN_DAT_PIN8 (0x03 << 4)
1.123 -#define STN_DAT_PINMASK STN_DAT_PIN8
1.124 -
1.125 -/* Pin reset states (LCD_CFG). */
1.126 -
1.127 -#define STFT_PSHI (1 << 15)
1.128 -#define STFT_CLSHI (1 << 14)
1.129 -#define STFT_SPLHI (1 << 13)
1.130 -#define STFT_REVHI (1 << 12)
1.131 -
1.132 -/* Sync direction (LCD_CFG.SYNDIR). */
1.133 -
1.134 -#define SYNC_MASTER (0 << 16)
1.135 -#define SYNC_SLAVE (1 << 16)
1.136 -
1.137 -/* Data enable polarity (LCD_CFG.DEP). */
1.138 -
1.139 -#define DE_P (0 << 9)
1.140 -#define DE_N (1 << 9)
1.141 -
1.142 -/* Pixel clock polarity (LCD_CFG.PCP). */
1.143 -
1.144 -#define PCLK_P (0 << 10)
1.145 -#define PCLK_N (1 << 10)
1.146 -
1.147 -/* Horizontal sync polarity (LCD_CFG.HSP). */
1.148 -
1.149 -#define HSYNC_P (0 << 11)
1.150 -#define HSYNC_N (1 << 11)
1.151 -
1.152 -/* Vertical sync polarity (LCD_CFG.VSP). */
1.153 -
1.154 -#define VSYNC_P (0 << 8)
1.155 -#define VSYNC_N (1 << 8)
1.156 -
1.157 -/* Inverse output data (LCD_CFG.INVDAT). */
1.158 -
1.159 -#define DATA_NORMAL (0 << 17)
1.160 -#define DATA_INVERSE (1 << 17)
1.161 -
1.162 -/* Register offsets. */
1.163 -
1.164 -#define LCD_CFG 0x00 /* LCD Configure Register */
1.165 -#define LCD_VSYNC 0x04 /* Vertical Synchronize Register */
1.166 -#define LCD_HSYNC 0x08 /* Horizontal Synchronize Register */
1.167 -#define LCD_VAT 0x0c /* Virtual Area Setting Register */
1.168 -#define LCD_DAH 0x10 /* Display Area Horizontal Start/End Point */
1.169 -#define LCD_DAV 0x14 /* Display Area Vertical Start/End Point */
1.170 -#define LCD_PS 0x18 /* PS Signal Setting */
1.171 -#define LCD_CLS 0x1c /* CLS Signal Setting */
1.172 -#define LCD_SPL 0x20 /* SPL Signal Setting */
1.173 -#define LCD_REV 0x24 /* REV Signal Setting */
1.174 -#define LCD_CTRL 0x30 /* LCD Control Register */
1.175 -#define LCD_STATE 0x34 /* LCD Status Register */
1.176 -#define LCD_IID 0x38 /* Interrupt ID Register */
1.177 -#define LCD_DA0 0x40 /* Descriptor Address Register 0 */
1.178 -#define LCD_SA0 0x44 /* Source Address Register 0 */
1.179 -#define LCD_FID0 0x48 /* Frame ID Register 0 */
1.180 -#define LCD_CMD0 0x4c /* DMA Command Register 0 */
1.181 -#define LCD_DA1 0x50 /* Descriptor Address Register 1 */
1.182 -#define LCD_SA1 0x54 /* Source Address Register 1 */
1.183 -#define LCD_FID1 0x58 /* Frame ID Register 1 */
1.184 -#define LCD_CMD1 0x5c /* DMA Command Register 1 */
1.185 -
1.186 -/* Burst length selection (LCD_CTRL.BST). */
1.187 -
1.188 -#define LCD_CTRL_BST_MASK (0x03 << 28)
1.189 -#define LCD_CTRL_BST_4 (0 << 28) /* 4-word */
1.190 -#define LCD_CTRL_BST_8 (1 << 28) /* 8-word */
1.191 -#define LCD_CTRL_BST_16 (2 << 28) /* 16-word */
1.192 -
1.193 -/* RGB mode (LCD_CTRL.RGB). */
1.194 -
1.195 -#define LCD_CTRL_RGB565 (0 << 27) /* RGB565 mode */
1.196 -#define LCD_CTRL_RGB555 (1 << 27) /* RGB555 mode */
1.197 -
1.198 -/* Output FIFO underrun protection (LCD_CTRL.OFUP). */
1.199 -
1.200 -#define LCD_CTRL_OFUP (1 << 26) /* Output FIFO underrun protection enable */
1.201 -
1.202 -/* STN FRC algorithm selection (LCD_CTRL.FRC). */
1.203 -
1.204 -#define LCD_CTRL_FRC_16 (0 << 24) /* 16 grayscale */
1.205 -#define LCD_CTRL_FRC_4 (1 << 24) /* 4 grayscale */
1.206 -#define LCD_CTRL_FRC_2 (2 << 24) /* 2 grayscale */
1.207 -#define LCD_CTRL_FRC_MASK (0x03 << 24)
1.208 -
1.209 -/* Load palette delay counter (LCD_CTRL.PDD) */
1.210 -
1.211 -#define LCD_CTRL_PDD_MASK (0xff << 16)
1.212 -
1.213 -#define LCD_CTRL_EOFM (1 << 13) /* EOF interrupt mask */
1.214 -#define LCD_CTRL_SOFM (1 << 12) /* SOF interrupt mask */
1.215 -#define LCD_CTRL_OFUM (1 << 11) /* Output FIFO underrun interrupt mask */
1.216 -#define LCD_CTRL_IFUM0 (1 << 10) /* Input FIFO 0 underrun interrupt mask */
1.217 -#define LCD_CTRL_IFUM1 (1 << 9) /* Input FIFO 1 underrun interrupt mask */
1.218 -#define LCD_CTRL_LDDM (1 << 8) /* LCD disable done interrupt mask */
1.219 -#define LCD_CTRL_QDM (1 << 7) /* LCD quick disable done interrupt mask */
1.220 -#define LCD_CTRL_BEDN (1 << 6) /* Endian selection */
1.221 -#define LCD_CTRL_PEDN (1 << 5) /* Endian in byte:0-msb first, 1-lsb first */
1.222 -#define LCD_CTRL_DIS (1 << 4) /* Disable indicate bit */
1.223 -#define LCD_CTRL_ENA (1 << 3) /* LCD enable bit */
1.224 -
1.225 -/* Bits per pixel (LCD_CTRL.BPP). */
1.226 -
1.227 -#define LCD_CTRL_BPP_1 0 /* 1 bpp */
1.228 -#define LCD_CTRL_BPP_2 1 /* 2 bpp */
1.229 -#define LCD_CTRL_BPP_4 2 /* 4 bpp */
1.230 -#define LCD_CTRL_BPP_8 3 /* 8 bpp */
1.231 -#define LCD_CTRL_BPP_16 4 /* 15/16 bpp */
1.232 -#define LCD_CTRL_BPP_18_24 5 /* 18/24/32 bpp */
1.233 -#define LCD_CTRL_BPP_MASK 0x07
1.234 -
1.235 -/* Palette buffer (LCD_CMDx.PAL). */
1.236 -
1.237 -#define LCD_CMD_PAL (1 << 28)
1.238 -
1.239 -#endif /* __JZLCD_H__ */