1.1 --- a/pkg/devices/lib/cpm/src/x1600.cc Thu Sep 14 01:38:13 2023 +0200
1.2 +++ b/pkg/devices/lib/cpm/src/x1600.cc Thu Sep 14 18:51:41 2023 +0200
1.3 @@ -263,42 +263,6 @@
1.4
1.5
1.6
1.7 -// Clock input descriptions.
1.8 -
1.9 -struct Clock_input_desc
1.10 -{
1.11 - uint32_t source_reg;
1.12 - enum Clock_source_bits source_bit;
1.13 - int num_inputs;
1.14 - enum Clock_input_identifiers inputs[3];
1.15 -};
1.16 -
1.17 -struct Clock_input_desc clock_input_desc[Clock_input_identifier_count] = {
1.18 -
1.19 - /* Clock_input_ahb2_apb */ {Clock_control, Clock_source_hclock2,
1.20 - 3, {Clock_input_none, Clock_input_main, Clock_input_pll_M}},
1.21 -
1.22 - /* Clock_input_external */ {Reg_undefined, Clock_source_undefined,
1.23 - 0, {}},
1.24 -
1.25 - /* Clock_input_main */ {Clock_control, Clock_source_main,
1.26 - 3, {Clock_input_none, Clock_input_external, Clock_input_pll_A}},
1.27 -
1.28 - /* Clock_input_none */ {Reg_undefined, Clock_source_undefined,
1.29 - 0, {}},
1.30 -
1.31 - /* Clock_input_pll_A */ {Reg_undefined, Clock_source_undefined,
1.32 - 1, {Clock_input_external}},
1.33 -
1.34 - /* Clock_input_pll_E */ {Reg_undefined, Clock_source_undefined,
1.35 - 1, {Clock_input_external}},
1.36 -
1.37 - /* Clock_input_pll_M */ {Reg_undefined, Clock_source_undefined,
1.38 - 1, {Clock_input_external}},
1.39 -};
1.40 -
1.41 -
1.42 -
1.43 // Clock descriptions.
1.44
1.45 struct Clock_desc
1.46 @@ -315,8 +279,7 @@
1.47 enum Clock_divider_bits divider_bit;
1.48 uint32_t divider_mask;
1.49 int num_inputs;
1.50 - enum Clock_input_identifiers inputs[4];
1.51 - enum Clock_identifiers clock_input;
1.52 + enum Clock_identifiers inputs[4];
1.53 };
1.54
1.55 #define Clock_desc_undefined {Reg_undefined, Clock_source_undefined, \
1.56 @@ -324,11 +287,17 @@
1.57 Reg_undefined, Clock_change_enable_undefined, \
1.58 Reg_undefined, Clock_busy_undefined, \
1.59 Reg_undefined, Clock_divider_undefined, 0, \
1.60 - 0, {}, \
1.61 - Clock_undefined}
1.62 + 0, {}}
1.63
1.64 static struct Clock_desc clock_desc[Clock_identifier_count] = {
1.65
1.66 + /* Clock_ahb2_apb */ {Clock_control, Clock_source_hclock2,
1.67 + Reg_undefined, Clock_gate_undefined,
1.68 + Reg_undefined, Clock_change_enable_undefined,
1.69 + Reg_undefined, Clock_busy_undefined,
1.70 + Reg_undefined, Clock_divider_undefined, 0,
1.71 + 3, {Clock_none, Clock_main, Clock_pll_M}},
1.72 +
1.73 /* Clock_aic_bitclk */ Clock_desc_undefined,
1.74
1.75 /* Clock_aic_pclk */ Clock_desc_undefined,
1.76 @@ -338,74 +307,72 @@
1.77 Can_divider0, Clock_change_enable_can0,
1.78 Can_divider0, Clock_busy_can0,
1.79 Can_divider0, Clock_divider_can0, 0xff,
1.80 - 4, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E, Clock_input_external},
1.81 - Clock_undefined},
1.82 + 4, {Clock_main, Clock_pll_M, Clock_pll_E, Clock_external}},
1.83
1.84 /* Clock_can1 */ {Can_divider1, Clock_source_can1,
1.85 Clock_gate1, Clock_gate_can1,
1.86 Can_divider1, Clock_change_enable_can1,
1.87 Can_divider1, Clock_busy_can1,
1.88 Can_divider1, Clock_divider_can1, 0xff,
1.89 - 4, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E, Clock_input_external},
1.90 - Clock_undefined},
1.91 + 4, {Clock_main, Clock_pll_M, Clock_pll_E, Clock_external}},
1.92
1.93 /* Clock_cdbus */ {Cdbus_divider, Clock_source_cdbus,
1.94 Clock_gate1, Clock_gate_cdbus,
1.95 Cdbus_divider, Clock_change_enable_cdbus,
1.96 Cdbus_divider, Clock_busy_cdbus,
1.97 Cdbus_divider, Clock_divider_cdbus, 0xff,
1.98 - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E},
1.99 - Clock_undefined},
1.100 + 3, {Clock_main, Clock_pll_M, Clock_pll_E}},
1.101
1.102 /* Clock_cim */ {Cim_divider, Clock_source_cim,
1.103 Clock_gate0, Clock_gate_cim,
1.104 Cim_divider, Clock_change_enable_cim,
1.105 Cim_divider, Clock_busy_cim,
1.106 Cim_divider, Clock_divider_cim, 0xff,
1.107 - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E},
1.108 - Clock_undefined},
1.109 + 3, {Clock_main, Clock_pll_M, Clock_pll_E}},
1.110
1.111 /* Clock_cpu */ {Clock_control, Clock_source_cpu,
1.112 Reg_undefined, Clock_gate_undefined,
1.113 Clock_control, Clock_change_enable_cpu,
1.114 Clock_status, Clock_busy_cpu,
1.115 Clock_control, Clock_divider_cpu, 0x0f,
1.116 - 3, {Clock_input_none, Clock_input_main, Clock_input_pll_M},
1.117 - Clock_undefined},
1.118 + 3, {Clock_none, Clock_main, Clock_pll_M}},
1.119
1.120 /* Clock_ddr */ {Ddr_divider, Clock_source_ddr,
1.121 Clock_gate0, Clock_gate_ddr,
1.122 Ddr_divider, Clock_change_enable_ddr,
1.123 Ddr_divider, Clock_busy_ddr,
1.124 Ddr_divider, Clock_divider_ddr, 0x0f,
1.125 - 3, {Clock_input_none, Clock_input_main, Clock_input_pll_M},
1.126 - Clock_undefined},
1.127 + 3, {Clock_none, Clock_main, Clock_pll_M}},
1.128
1.129 /* Clock_dma */ {Reg_undefined, Clock_source_undefined,
1.130 Clock_gate0, Clock_gate_dma,
1.131 Reg_undefined, Clock_change_enable_undefined,
1.132 Reg_undefined, Clock_busy_undefined,
1.133 Reg_undefined, Clock_divider_undefined, 0,
1.134 - 0, {},
1.135 - Clock_pclock},
1.136 + 1, {Clock_pclock}},
1.137
1.138 /* Clock_emac */ Clock_desc_undefined,
1.139
1.140 + /* Clock_external */ {Reg_undefined, Clock_source_undefined,
1.141 + Reg_undefined, Clock_gate_undefined,
1.142 + Reg_undefined, Clock_change_enable_undefined,
1.143 + Reg_undefined, Clock_busy_undefined,
1.144 + Reg_undefined, Clock_divider_undefined, 0,
1.145 + 0, {}},
1.146 +
1.147 /* Clock_hclock0 */ {Clock_control, Clock_source_hclock0,
1.148 Clock_gate0, Clock_gate_ahb0,
1.149 Clock_control, Clock_change_enable_ahb0,
1.150 Reg_undefined, Clock_busy_undefined,
1.151 Clock_control, Clock_divider_hclock0, 0x0f,
1.152 - 3, {Clock_input_none, Clock_input_main, Clock_input_pll_M},
1.153 - Clock_undefined},
1.154 + 3, {Clock_none, Clock_main, Clock_pll_M}},
1.155
1.156 /* Clock_hclock2 */ {Reg_undefined, Clock_source_undefined,
1.157 Clock_gate0, Clock_gate_apb0,
1.158 Clock_control, Clock_change_enable_ahb2,
1.159 Reg_undefined, Clock_busy_undefined,
1.160 Clock_control, Clock_divider_hclock2, 0x0f,
1.161 - 1, {Clock_input_ahb2_apb},
1.162 - Clock_undefined},
1.163 + 1, {Clock_ahb2_apb}},
1.164
1.165 /* Clock_hdmi */ Clock_desc_undefined,
1.166
1.167 @@ -414,24 +381,21 @@
1.168 Reg_undefined, Clock_change_enable_undefined,
1.169 Reg_undefined, Clock_busy_undefined,
1.170 Reg_undefined, Clock_divider_undefined, 0,
1.171 - 0, {},
1.172 - Clock_pclock},
1.173 + 1, {Clock_pclock}},
1.174
1.175 /* Clock_i2c0 */ {Reg_undefined, Clock_source_undefined,
1.176 Clock_gate0, Clock_gate_i2c0,
1.177 Reg_undefined, Clock_change_enable_undefined,
1.178 Reg_undefined, Clock_busy_undefined,
1.179 Reg_undefined, Clock_divider_undefined, 0,
1.180 - 0, {},
1.181 - Clock_pclock},
1.182 + 1, {Clock_pclock}},
1.183
1.184 /* Clock_i2c1 */ {Reg_undefined, Clock_source_undefined,
1.185 Clock_gate0, Clock_gate_i2c1,
1.186 Reg_undefined, Clock_change_enable_undefined,
1.187 Reg_undefined, Clock_busy_undefined,
1.188 Reg_undefined, Clock_divider_undefined, 0,
1.189 - 0, {},
1.190 - Clock_pclock},
1.191 + 1, {Clock_pclock}},
1.192
1.193 /* Clock_i2s */ Clock_desc_undefined,
1.194
1.195 @@ -440,16 +404,14 @@
1.196 I2s_divider0, Clock_change_enable_i2s,
1.197 Reg_undefined, Clock_busy_undefined,
1.198 Reg_undefined, Clock_divider_undefined, 0, // NOTE: To define.
1.199 - 2, {Clock_input_main, Clock_input_pll_E},
1.200 - Clock_undefined},
1.201 + 2, {Clock_main, Clock_pll_E}},
1.202
1.203 /* Clock_i2s0_tx */ {I2s_divider0, Clock_source_i2s,
1.204 Clock_gate1, Clock_gate_i2s0_tx,
1.205 I2s_divider0, Clock_change_enable_i2s,
1.206 Reg_undefined, Clock_busy_undefined,
1.207 Reg_undefined, Clock_divider_undefined, 0, // NOTE: To define.
1.208 - 2, {Clock_input_main, Clock_input_pll_E},
1.209 - Clock_undefined},
1.210 + 2, {Clock_main, Clock_pll_E}},
1.211
1.212 /* Clock_kbc */ Clock_desc_undefined,
1.213
1.214 @@ -460,72 +422,91 @@
1.215 Lcd_divider, Clock_change_enable_lcd,
1.216 Lcd_divider, Clock_busy_lcd,
1.217 Lcd_divider, Clock_divider_lcd, 0xff,
1.218 - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E},
1.219 - Clock_undefined},
1.220 + 3, {Clock_main, Clock_pll_M, Clock_pll_E}},
1.221
1.222 /* Clock_mac */ {Mac_divider, Clock_source_mac,
1.223 Clock_gate1, Clock_gate_gmac0,
1.224 Mac_divider, Clock_change_enable_mac,
1.225 Mac_divider, Clock_busy_mac,
1.226 Mac_divider, Clock_divider_mac, 0xff,
1.227 - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E},
1.228 - Clock_undefined},
1.229 + 3, {Clock_main, Clock_pll_M, Clock_pll_E}},
1.230
1.231 - /* Clock_main */ {Reg_undefined, Clock_source_undefined,
1.232 + /* Clock_main */ {Clock_control, Clock_source_main,
1.233 Clock_control, Clock_gate_main,
1.234 Reg_undefined, Clock_change_enable_undefined,
1.235 Reg_undefined, Clock_busy_undefined,
1.236 Reg_undefined, Clock_divider_undefined, 0,
1.237 - 1, {Clock_input_main},
1.238 - Clock_undefined},
1.239 + 3, {Clock_none, Clock_external, Clock_pll_A}},
1.240
1.241 /* Clock_msc */ {Msc_divider0, Clock_source_msc0,
1.242 Clock_gate0, Clock_gate_msc0,
1.243 Msc_divider0, Clock_change_enable_msc0,
1.244 Msc_divider0, Clock_busy_msc0,
1.245 Msc_divider0, Clock_divider_msc0, 0xff,
1.246 - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E},
1.247 - Clock_undefined},
1.248 + 3, {Clock_main, Clock_pll_M, Clock_pll_E}},
1.249
1.250 /* Clock_msc0 */ {Msc_divider0, Clock_source_msc0,
1.251 Clock_gate0, Clock_gate_msc0,
1.252 Msc_divider0, Clock_change_enable_msc0,
1.253 Msc_divider0, Clock_busy_msc0,
1.254 Msc_divider0, Clock_divider_msc0, 0xff,
1.255 - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E},
1.256 - Clock_undefined},
1.257 + 3, {Clock_main, Clock_pll_M, Clock_pll_E}},
1.258
1.259 /* Clock_msc1 */ {Msc_divider1, Clock_source_msc1,
1.260 Clock_gate0, Clock_gate_msc1,
1.261 Msc_divider1, Clock_change_enable_msc1,
1.262 Msc_divider1, Clock_busy_msc1,
1.263 Msc_divider1, Clock_divider_msc1, 0xff,
1.264 - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E},
1.265 - Clock_undefined},
1.266 + 3, {Clock_main, Clock_pll_M, Clock_pll_E}},
1.267 +
1.268 + /* Clock_none */ {Reg_undefined, Clock_source_undefined,
1.269 + Reg_undefined, Clock_gate_undefined,
1.270 + Reg_undefined, Clock_change_enable_undefined,
1.271 + Reg_undefined, Clock_busy_undefined,
1.272 + Reg_undefined, Clock_divider_undefined, 0,
1.273 + 0, {}},
1.274
1.275 /* Clock_pclock */ {Reg_undefined, Clock_source_undefined,
1.276 Clock_gate0, Clock_gate_apb0,
1.277 Reg_undefined, Clock_change_enable_undefined,
1.278 Reg_undefined, Clock_busy_undefined,
1.279 Clock_control, Clock_divider_pclock, 0x0f,
1.280 - 1, {Clock_input_ahb2_apb},
1.281 - Clock_undefined},
1.282 + 1, {Clock_ahb2_apb}},
1.283 +
1.284 + /* Clock_pll_A */ {Reg_undefined, Clock_source_undefined,
1.285 + Reg_undefined, Clock_gate_undefined,
1.286 + Reg_undefined, Clock_change_enable_undefined,
1.287 + Reg_undefined, Clock_busy_undefined,
1.288 + Reg_undefined, Clock_divider_undefined, 0,
1.289 + 1, {Clock_external}},
1.290 +
1.291 + /* Clock_pll_E */ {Reg_undefined, Clock_source_undefined,
1.292 + Reg_undefined, Clock_gate_undefined,
1.293 + Reg_undefined, Clock_change_enable_undefined,
1.294 + Reg_undefined, Clock_busy_undefined,
1.295 + Reg_undefined, Clock_divider_undefined, 0,
1.296 + 1, {Clock_external}},
1.297 +
1.298 + /* Clock_pll_M */ {Reg_undefined, Clock_source_undefined,
1.299 + Reg_undefined, Clock_gate_undefined,
1.300 + Reg_undefined, Clock_change_enable_undefined,
1.301 + Reg_undefined, Clock_busy_undefined,
1.302 + Reg_undefined, Clock_divider_undefined, 0,
1.303 + 1, {Clock_external}},
1.304
1.305 /* Clock_pwm */ {Pwm_divider, Clock_source_pwm,
1.306 Clock_gate1, Clock_gate_pwm,
1.307 Pwm_divider, Clock_change_enable_pwm,
1.308 Pwm_divider, Clock_busy_pwm,
1.309 Pwm_divider, Clock_divider_pwm, 0x0f,
1.310 - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E},
1.311 - Clock_undefined},
1.312 + 3, {Clock_main, Clock_pll_M, Clock_pll_E}},
1.313
1.314 /* Clock_pwm0 */ {Pwm_divider, Clock_source_pwm,
1.315 Clock_gate1, Clock_gate_pwm,
1.316 Pwm_divider, Clock_change_enable_pwm,
1.317 Pwm_divider, Clock_busy_pwm,
1.318 Pwm_divider, Clock_divider_pwm, 0x0f,
1.319 - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E},
1.320 - Clock_undefined},
1.321 + 3, {Clock_main, Clock_pll_M, Clock_pll_E}},
1.322
1.323 /* Clock_pwm1 */ Clock_desc_undefined,
1.324
1.325 @@ -536,8 +517,7 @@
1.326 Sfc_divider, Clock_change_enable_sfc,
1.327 Sfc_divider, Clock_busy_sfc,
1.328 Sfc_divider, Clock_divider_sfc, 0xff,
1.329 - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E},
1.330 - Clock_undefined},
1.331 + 3, {Clock_main, Clock_pll_M, Clock_pll_E}},
1.332
1.333 /* Clock_smb0 */ Clock_desc_undefined,
1.334
1.335 @@ -554,48 +534,42 @@
1.336 Ssi_divider, Clock_change_enable_ssi,
1.337 Ssi_divider, Clock_busy_ssi,
1.338 Ssi_divider, Clock_divider_ssi, 0xff,
1.339 - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E},
1.340 - Clock_undefined},
1.341 + 3, {Clock_main, Clock_pll_M, Clock_pll_E}},
1.342
1.343 /* Clock_timer */ {Reg_undefined, Clock_source_undefined,
1.344 Clock_gate0, Clock_gate_timer,
1.345 Reg_undefined, Clock_change_enable_undefined,
1.346 Reg_undefined, Clock_busy_undefined,
1.347 Reg_undefined, Clock_divider_undefined, 0,
1.348 - 0, {},
1.349 - Clock_pclock},
1.350 + 1, {Clock_pclock}},
1.351
1.352 /* Clock_uart0 */ {Reg_undefined, Clock_source_undefined,
1.353 Clock_gate0, Clock_gate_uart0,
1.354 Reg_undefined, Clock_change_enable_undefined,
1.355 Reg_undefined, Clock_busy_undefined,
1.356 Reg_undefined, Clock_divider_undefined, 0,
1.357 - 1, {Clock_input_external},
1.358 - Clock_undefined},
1.359 + 1, {Clock_external}},
1.360
1.361 /* Clock_uart1 */ {Reg_undefined, Clock_source_undefined,
1.362 Clock_gate0, Clock_gate_uart1,
1.363 Reg_undefined, Clock_change_enable_undefined,
1.364 Reg_undefined, Clock_busy_undefined,
1.365 Reg_undefined, Clock_divider_undefined, 0,
1.366 - 1, {Clock_input_external},
1.367 - Clock_undefined},
1.368 + 1, {Clock_external}},
1.369
1.370 /* Clock_uart2 */ {Reg_undefined, Clock_source_undefined,
1.371 Clock_gate0, Clock_gate_uart2,
1.372 Reg_undefined, Clock_change_enable_undefined,
1.373 Reg_undefined, Clock_busy_undefined,
1.374 Reg_undefined, Clock_divider_undefined, 0,
1.375 - 1, {Clock_input_external},
1.376 - Clock_undefined},
1.377 + 1, {Clock_external}},
1.378
1.379 /* Clock_uart3 */ {Reg_undefined, Clock_source_undefined,
1.380 Clock_gate1, Clock_gate_uart3,
1.381 Reg_undefined, Clock_change_enable_undefined,
1.382 Reg_undefined, Clock_busy_undefined,
1.383 Reg_undefined, Clock_divider_undefined, 0,
1.384 - 1, {Clock_input_external},
1.385 - Clock_undefined},
1.386 + 1, {Clock_external}},
1.387
1.388 /* Clock_udc */ Clock_desc_undefined,
1.389
1.390 @@ -892,68 +866,32 @@
1.391 // Clock source frequencies.
1.392
1.393 uint32_t
1.394 -Cpm_x1600_chip::get_input_frequency(enum Clock_input_identifiers clock)
1.395 -{
1.396 - struct Clock_input_desc desc = clock_input_desc[clock];
1.397 -
1.398 - // Clocks with no inputs provide a frequency.
1.399 -
1.400 - if (desc.num_inputs == 0)
1.401 - {
1.402 - switch (clock)
1.403 - {
1.404 - case Clock_input_external: return _exclk_freq;
1.405 - default: return 0;
1.406 - }
1.407 - }
1.408 -
1.409 - // Of the input clocks, only PLLs have a single input.
1.410 -
1.411 - else if (desc.num_inputs == 1)
1.412 - {
1.413 - switch (clock)
1.414 - {
1.415 - case Clock_input_pll_A: return get_pll_frequency(Pll_control_A);
1.416 - case Clock_input_pll_E: return get_pll_frequency(Pll_control_E);
1.417 - case Clock_input_pll_M: return get_pll_frequency(Pll_control_M);
1.418 - default: return 0;
1.419 - }
1.420 - }
1.421 -
1.422 - // With multiple sources, obtain the selected source for the clock.
1.423 -
1.424 - uint8_t source = get_field(desc.source_reg, Source_mask, desc.source_bit);
1.425 -
1.426 - // Return the frequency of the source.
1.427 -
1.428 - if (source < desc.num_inputs)
1.429 - return get_input_frequency(desc.inputs[source]);
1.430 - else
1.431 - return 0;
1.432 -}
1.433 -
1.434 -uint32_t
1.435 Cpm_x1600_chip::get_source_frequency(enum Clock_identifiers clock)
1.436 {
1.437 struct Clock_desc desc = clock_desc[clock];
1.438
1.439 if (desc.num_inputs == 0)
1.440 {
1.441 - // Clocks may reference other clocks.
1.442 -
1.443 - if (desc.clock_input != Clock_undefined)
1.444 - return get_frequency(desc.clock_input);
1.445 -
1.446 - // Undefined clocks return zero.
1.447 -
1.448 - else
1.449 - return 0;
1.450 + switch (clock)
1.451 + {
1.452 + case Clock_external: return _exclk_freq;
1.453 + default: return 0;
1.454 + }
1.455 }
1.456
1.457 - // Clocks with one source yield that input frequency.
1.458 + // Clocks with one source yield that input frequency, although PLLs are
1.459 + // handled specially.
1.460
1.461 else if (desc.num_inputs == 1)
1.462 - return get_input_frequency(desc.inputs[0]);
1.463 + {
1.464 + switch (clock)
1.465 + {
1.466 + case Clock_pll_A: return get_pll_frequency(Pll_control_A);
1.467 + case Clock_pll_E: return get_pll_frequency(Pll_control_E);
1.468 + case Clock_pll_M: return get_pll_frequency(Pll_control_M);
1.469 + default: return get_frequency(desc.inputs[0]);
1.470 + }
1.471 + }
1.472
1.473 // With multiple sources, obtain the selected source for the clock.
1.474
1.475 @@ -962,7 +900,7 @@
1.476 // Return the frequency of the source.
1.477
1.478 if (source < desc.num_inputs)
1.479 - return get_input_frequency(desc.inputs[source]);
1.480 + return get_frequency(desc.inputs[source]);
1.481 else
1.482 return 0;
1.483 }