1.1 --- a/pkg/devices/lib/lcd/src/jz4740/lcd-jz4740.cc Fri May 22 00:25:28 2020 +0200
1.2 +++ b/pkg/devices/lib/lcd/src/jz4740/lcd-jz4740.cc Sat May 23 16:05:22 2020 +0200
1.3 @@ -2,7 +2,8 @@
1.4 * LCD peripheral support for the JZ4740 and related SoCs.
1.5 *
1.6 * Copyright (C) Xiangfu Liu <xiangfu@sharism.cc>
1.7 - * Copyright (C) 2015, 2016, 2017, 2018 Paul Boddie <paul@boddie.org.uk>
1.8 + * Copyright (C) 2015, 2016, 2017, 2018,
1.9 + * 2020 Paul Boddie <paul@boddie.org.uk>
1.10 *
1.11 * This program is free software; you can redistribute it and/or
1.12 * modify it under the terms of the GNU General Public License as
1.13 @@ -83,23 +84,25 @@
1.14
1.15 enum Control_bits : unsigned
1.16 {
1.17 - Control_burst_length = 28, // BST (burst length selection)
1.18 - Control_rgb_mode = 27, // RGB (RGB mode)
1.19 - Control_out_underrun = 26, // OFUP (output FIFO underrun protection)
1.20 - Control_frc_algorithm = 24, // FRC (STN FRC algorithm selection)
1.21 - Control_palette_delay = 16, // PDD (load palette delay counter)
1.22 - Control_frame_end_irq_mask = 13, // EOFM (end of frame interrupt mask)
1.23 - Control_frame_start_irq_mask = 12, // SOFM (start of frame interrupt mask)
1.24 - Control_out_underrun_irq_mask = 11, // OFUM (output FIFO underrun interrupt mask)
1.25 - Control_in0_underrun_irq_mask = 10, // IFUM0 (input FIFO 0 underrun interrupt mask)
1.26 - Control_in1_underrun_irq_mask = 9, // IFUM1 (input FIFO 1 underrun interrupt mask)
1.27 - Control_disabled_irq_mask = 8, // LDDM (LCD disable done interrupt mask)
1.28 - Control_quick_disabled_irq_mask = 7, // QDM (LCD quick disable done interrupt mask)
1.29 - Control_endian_select = 6, // BEDN (endian selection)
1.30 - Control_bit_order = 5, // PEDN (bit order in bytes)
1.31 - Control_disable = 4, // DIS (disable controller)
1.32 - Control_enable = 3, // ENA (enable controller)
1.33 - Control_bpp = 0, // BPP (bits per pixel)
1.34 + Control_pin_modify = 31, // PINMD (change pin usage from 15..0 to 17..10, 8..1)
1.35 + Control_burst_length = 28, // BST (burst length selection)
1.36 + Control_rgb_mode = 27, // RGB (RGB mode)
1.37 + Control_out_underrun = 26, // OFUP (output FIFO underrun protection)
1.38 + Control_frc_algorithm = 24, // FRC (STN FRC algorithm selection)
1.39 + Control_palette_delay = 16, // PDD (load palette delay counter)
1.40 + Control_dac_loopback_test = 14, // DACTE (DAC loopback test)
1.41 + Control_frame_end_irq_enable = 13, // EOFM (end of frame interrupt enable)
1.42 + Control_frame_start_irq_enable = 12, // SOFM (start of frame interrupt enable)
1.43 + Control_out_underrun_irq_enable = 11, // OFUM (output FIFO underrun interrupt enable)
1.44 + Control_in0_underrun_irq_enable = 10, // IFUM0 (input FIFO 0 underrun interrupt enable)
1.45 + Control_in1_underrun_irq_enable = 9, // IFUM1 (input FIFO 1 underrun interrupt enable)
1.46 + Control_disabled_irq_enable = 8, // LDDM (LCD disable done interrupt enable)
1.47 + Control_quick_disabled_irq_enable = 7, // QDM (LCD quick disable done interrupt enable)
1.48 + Control_endian_select = 6, // BEDN (endian selection)
1.49 + Control_bit_order = 5, // PEDN (bit order in bytes)
1.50 + Control_disable = 4, // DIS (disable controller)
1.51 + Control_enable = 3, // ENA (enable controller)
1.52 + Control_bpp = 0, // BPP (bits per pixel)
1.53 };
1.54
1.55 enum Burst_length_values : unsigned