1.1 --- a/pkg/devices/lib/cpm/src/common.cc Mon Sep 18 00:41:04 2023 +0200
1.2 +++ b/pkg/devices/lib/cpm/src/common.cc Mon Sep 18 02:21:50 2023 +0200
1.3 @@ -135,10 +135,6 @@
1.4 return 0;
1.5 }
1.6
1.7 -// Undefined source.
1.8 -
1.9 -Source Source::undefined;
1.10 -
1.11
1.12
1.13 // Clock control.
1.14 @@ -203,10 +199,6 @@
1.15 _change_enable.set_field(regs, 1);
1.16 }
1.17
1.18 -// Undefined control.
1.19 -
1.20 -Control Control::undefined;
1.21 -
1.22
1.23
1.24 // PLL-specific control.
1.25 @@ -305,10 +297,6 @@
1.26 set_divider(regs, parameters[0]);
1.27 }
1.28
1.29 -// Undefined divider.
1.30 -
1.31 -Divider Divider::undefined;
1.32 -
1.33
1.34
1.35 // Feedback (13-bit) multiplier.
1.36 @@ -578,26 +566,26 @@
1.37
1.38 // Divided clock interface.
1.39
1.40 -Clock_divided::~Clock_divided()
1.41 +Clock_divided_base::~Clock_divided_base()
1.42 {
1.43 }
1.44
1.45 // Output clock frequencies.
1.46
1.47 uint32_t
1.48 -Clock_divided::get_frequency(Cpm_regs ®s)
1.49 +Clock_divided_base::get_frequency(Cpm_regs ®s)
1.50 {
1.51 return _get_divider().get_frequency(regs, get_source_frequency(regs));
1.52 }
1.53
1.54 int
1.55 -Clock_divided::get_parameters(Cpm_regs ®s, uint32_t parameters[])
1.56 +Clock_divided_base::get_parameters(Cpm_regs ®s, uint32_t parameters[])
1.57 {
1.58 return _get_divider().get_parameters(regs, parameters);
1.59 }
1.60
1.61 void
1.62 -Clock_divided::set_parameters(Cpm_regs ®s, uint32_t parameters[])
1.63 +Clock_divided_base::set_parameters(Cpm_regs ®s, uint32_t parameters[])
1.64 {
1.65 _get_control().change_enable(regs);
1.66 _get_divider().set_parameters(regs, parameters);