1.1 --- a/pkg/devices/lib/cpm/src/x1600.cc Mon Sep 18 00:41:04 2023 +0200
1.2 +++ b/pkg/devices/lib/cpm/src/x1600.cc Mon Sep 18 02:21:50 2023 +0200
1.3 @@ -248,105 +248,108 @@
1.4
1.5 // Clock instances.
1.6
1.7 -static Clock_passive clock_external;
1.8 +static Clock_null clock_none;
1.9 +
1.10 +static Clock_passive clock_external;
1.11
1.12 -static Clock_null clock_none;
1.13 +// Note the use of extra parentheses due to the annoying C++ "most vexing parse"
1.14 +// problem. See: https://en.wikipedia.org/wiki/Most_vexing_parse
1.15
1.16 -static Clock clock_ahb2_apb(Source(mux_core, Clock_source_hclock2)),
1.17 +static Clock clock_ahb2_apb(Source(mux_core, Clock_source_hclock2)),
1.18
1.19 - clock_can0(Source(mux_bus, Clock_source_can0),
1.20 - Control(Clock_gate_can0, Clock_change_enable_can0, Clock_busy_can0),
1.21 - Divider(Clock_divider_can0)),
1.22 -
1.23 - clock_can1(Source(mux_bus, Clock_source_can1),
1.24 - Control(Clock_gate_can1, Clock_change_enable_can1, Clock_busy_can1),
1.25 - Divider(Clock_divider_can1)),
1.26 -
1.27 - clock_cdbus(Source(mux_dev, Clock_source_cdbus),
1.28 - Control(Clock_gate_cdbus, Clock_change_enable_cdbus, Clock_busy_cdbus),
1.29 - Divider(Clock_divider_cdbus)),
1.30 -
1.31 - clock_cim(Source(mux_dev, Clock_source_cim),
1.32 - Control(Clock_gate_cim, Clock_change_enable_cim, Clock_busy_cim),
1.33 - Divider(Clock_divider_cim)),
1.34 -
1.35 - clock_cpu(Source(mux_core, Clock_source_cpu),
1.36 - Control(Field::undefined, Clock_change_enable_cpu, Clock_busy_cpu),
1.37 - Divider(Clock_divider_cpu)),
1.38 -
1.39 - clock_ddr(Source(mux_core, Clock_source_ddr),
1.40 - Control(Clock_gate_ddr, Clock_change_enable_ddr, Clock_busy_ddr),
1.41 - Divider(Clock_divider_ddr)),
1.42 -
1.43 - clock_dma(Source(mux_pclock), Control(Clock_gate_dma), Divider::undefined),
1.44 -
1.45 - clock_hclock0(Source(mux_core, Clock_source_hclock0),
1.46 - Control(Clock_gate_ahb0, Clock_change_enable_ahb0),
1.47 - Divider(Clock_divider_hclock0)),
1.48 -
1.49 - clock_hclock2(Source(mux_ahb2_apb),
1.50 - Control(Clock_gate_apb0, Clock_change_enable_ahb2),
1.51 - Divider(Clock_divider_hclock2)),
1.52 -
1.53 - clock_i2c(Source(mux_pclock), Control(Clock_gate_i2c0), Divider::undefined),
1.54 -
1.55 - clock_i2c0(Source(mux_pclock), Control(Clock_gate_i2c0), Divider::undefined),
1.56 -
1.57 - clock_i2c1(Source(mux_pclock), Control(Clock_gate_i2c1), Divider::undefined),
1.58 -
1.59 - clock_lcd_pixel(Source(mux_dev, Clock_source_lcd),
1.60 - Control(Clock_gate_lcd_pixel, Clock_change_enable_lcd, Clock_busy_lcd),
1.61 - Divider(Clock_divider_lcd)),
1.62 + clock_dma((Source(mux_pclock)), (Control(Clock_gate_dma))),
1.63 +
1.64 + clock_i2c((Source(mux_pclock)), (Control(Clock_gate_i2c0))),
1.65 +
1.66 + clock_i2c0((Source(mux_pclock)), (Control(Clock_gate_i2c0))),
1.67 +
1.68 + clock_i2c1((Source(mux_pclock)), (Control(Clock_gate_i2c1))),
1.69 +
1.70 + clock_main(Source(mux_core, Clock_source_main),
1.71 + Control(Clock_gate_main)),
1.72 +
1.73 + clock_timer((Source(mux_pclock)), (Control(Clock_gate_timer))),
1.74 +
1.75 + clock_uart0((Source(mux_external)), (Control(Clock_gate_uart0))),
1.76 +
1.77 + clock_uart1((Source(mux_external)), (Control(Clock_gate_uart1))),
1.78 +
1.79 + clock_uart2((Source(mux_external)), (Control(Clock_gate_uart2))),
1.80 +
1.81 + clock_uart3((Source(mux_external)), (Control(Clock_gate_uart3)));
1.82
1.83 - clock_mac(Source(mux_dev, Clock_source_mac),
1.84 - Control(Clock_gate_gmac0, Clock_change_enable_mac, Clock_busy_mac),
1.85 - Divider(Clock_divider_mac)),
1.86 -
1.87 - clock_main(Source(mux_core, Clock_source_main),
1.88 - Control(Clock_gate_main)),
1.89 -
1.90 - clock_msc(Source(mux_dev, Clock_source_msc0),
1.91 - Control(Clock_gate_msc0, Clock_change_enable_msc0, Clock_busy_msc0),
1.92 - Divider(Clock_divider_msc0)),
1.93 -
1.94 - clock_msc0(Source(mux_dev, Clock_source_msc0),
1.95 - Control(Clock_gate_msc0, Clock_change_enable_msc0, Clock_busy_msc0),
1.96 - Divider(Clock_divider_msc0)),
1.97 -
1.98 - clock_msc1(Source(mux_dev, Clock_source_msc1),
1.99 - Control(Clock_gate_msc1, Clock_change_enable_msc1, Clock_busy_msc1),
1.100 - Divider(Clock_divider_msc1)),
1.101 -
1.102 - clock_pclock(Source(mux_ahb2_apb),
1.103 - Control(Clock_gate_apb0, Field::undefined, Field::undefined),
1.104 - Divider(Clock_divider_pclock)),
1.105 -
1.106 - clock_pwm(Source(mux_dev, Clock_source_pwm),
1.107 - Control(Clock_gate_pwm, Clock_change_enable_pwm, Clock_busy_pwm),
1.108 - Divider(Clock_divider_pwm)),
1.109 -
1.110 - clock_pwm0(Source(mux_dev, Clock_source_pwm),
1.111 - Control(Clock_gate_pwm, Clock_change_enable_pwm, Clock_busy_pwm),
1.112 - Divider(Clock_divider_pwm)),
1.113 -
1.114 - clock_sfc(Source(mux_dev, Clock_source_sfc),
1.115 - Control(Clock_gate_sfc, Clock_change_enable_sfc, Clock_busy_sfc),
1.116 - Divider(Clock_divider_sfc)),
1.117 -
1.118 - clock_ssi(Source(mux_dev, Clock_source_ssi),
1.119 - Control(Clock_gate_ssi0, Clock_change_enable_ssi, Clock_busy_ssi),
1.120 - Divider(Clock_divider_ssi)),
1.121 -
1.122 - clock_timer(Source(mux_pclock), Control(Clock_gate_timer), Divider::undefined),
1.123 -
1.124 - clock_uart0(Source(mux_external), Control(Clock_gate_uart0), Divider::undefined),
1.125 -
1.126 - clock_uart1(Source(mux_external), Control(Clock_gate_uart1), Divider::undefined),
1.127 -
1.128 - clock_uart2(Source(mux_external), Control(Clock_gate_uart2), Divider::undefined),
1.129 -
1.130 - clock_uart3(Source(mux_external), Control(Clock_gate_uart3), Divider::undefined);
1.131 -
1.132 +static Clock_divided clock_can0(Source(mux_bus, Clock_source_can0),
1.133 + Control(Clock_gate_can0, Clock_change_enable_can0, Clock_busy_can0),
1.134 + Divider(Clock_divider_can0)),
1.135 +
1.136 + clock_can1(Source(mux_bus, Clock_source_can1),
1.137 + Control(Clock_gate_can1, Clock_change_enable_can1, Clock_busy_can1),
1.138 + Divider(Clock_divider_can1)),
1.139 +
1.140 + clock_cdbus(Source(mux_dev, Clock_source_cdbus),
1.141 + Control(Clock_gate_cdbus, Clock_change_enable_cdbus, Clock_busy_cdbus),
1.142 + Divider(Clock_divider_cdbus)),
1.143 +
1.144 + clock_cim(Source(mux_dev, Clock_source_cim),
1.145 + Control(Clock_gate_cim, Clock_change_enable_cim, Clock_busy_cim),
1.146 + Divider(Clock_divider_cim)),
1.147 +
1.148 + clock_cpu(Source(mux_core, Clock_source_cpu),
1.149 + Control(Field::undefined, Clock_change_enable_cpu, Clock_busy_cpu),
1.150 + Divider(Clock_divider_cpu)),
1.151 +
1.152 + clock_ddr(Source(mux_core, Clock_source_ddr),
1.153 + Control(Clock_gate_ddr, Clock_change_enable_ddr, Clock_busy_ddr),
1.154 + Divider(Clock_divider_ddr)),
1.155 +
1.156 + clock_hclock0(Source(mux_core, Clock_source_hclock0),
1.157 + Control(Clock_gate_ahb0, Clock_change_enable_ahb0),
1.158 + Divider(Clock_divider_hclock0)),
1.159 +
1.160 + clock_hclock2(Source(mux_ahb2_apb),
1.161 + Control(Clock_gate_apb0, Clock_change_enable_ahb2),
1.162 + Divider(Clock_divider_hclock2)),
1.163 +
1.164 + clock_lcd_pixel(Source(mux_dev, Clock_source_lcd),
1.165 + Control(Clock_gate_lcd_pixel, Clock_change_enable_lcd, Clock_busy_lcd),
1.166 + Divider(Clock_divider_lcd)),
1.167 +
1.168 + clock_mac(Source(mux_dev, Clock_source_mac),
1.169 + Control(Clock_gate_gmac0, Clock_change_enable_mac, Clock_busy_mac),
1.170 + Divider(Clock_divider_mac)),
1.171 +
1.172 + clock_msc(Source(mux_dev, Clock_source_msc0),
1.173 + Control(Clock_gate_msc0, Clock_change_enable_msc0, Clock_busy_msc0),
1.174 + Divider(Clock_divider_msc0)),
1.175 +
1.176 + clock_msc0(Source(mux_dev, Clock_source_msc0),
1.177 + Control(Clock_gate_msc0, Clock_change_enable_msc0, Clock_busy_msc0),
1.178 + Divider(Clock_divider_msc0)),
1.179 +
1.180 + clock_msc1(Source(mux_dev, Clock_source_msc1),
1.181 + Control(Clock_gate_msc1, Clock_change_enable_msc1, Clock_busy_msc1),
1.182 + Divider(Clock_divider_msc1)),
1.183 +
1.184 + clock_pclock((Source(mux_ahb2_apb)),
1.185 + (Control(Clock_gate_apb0)),
1.186 + (Divider(Clock_divider_pclock))),
1.187 +
1.188 + clock_pwm(Source(mux_dev, Clock_source_pwm),
1.189 + Control(Clock_gate_pwm, Clock_change_enable_pwm, Clock_busy_pwm),
1.190 + Divider(Clock_divider_pwm)),
1.191 +
1.192 + clock_pwm0(Source(mux_dev, Clock_source_pwm),
1.193 + Control(Clock_gate_pwm, Clock_change_enable_pwm, Clock_busy_pwm),
1.194 + Divider(Clock_divider_pwm)),
1.195 +
1.196 + clock_sfc(Source(mux_dev, Clock_source_sfc),
1.197 + Control(Clock_gate_sfc, Clock_change_enable_sfc, Clock_busy_sfc),
1.198 + Divider(Clock_divider_sfc)),
1.199 +
1.200 + clock_ssi(Source(mux_dev, Clock_source_ssi),
1.201 + Control(Clock_gate_ssi0, Clock_change_enable_ssi, Clock_busy_ssi),
1.202 + Divider(Clock_divider_ssi));
1.203 +
1.204 static Clock_divided_i2s clock_i2s0_rx(Source(mux_i2s, Clock_source_i2s),
1.205 Control(Clock_gate_i2s0_rx, Clock_change_enable_i2s),
1.206 Divider_i2s(Clock_divider_i2s0_m, Clock_divider_i2s0_n,
1.207 @@ -357,20 +360,20 @@
1.208 Divider_i2s(Clock_divider_i2s1_m, Clock_divider_i2s1_n,
1.209 Clock_divider_i2s1_d));
1.210
1.211 -static Pll clock_pll_A(Source(mux_external),
1.212 - Control_pll(Pll_enable_A, Pll_stable_A, Pll_bypass_A),
1.213 - Divider_pll(Pll_multiplier_A, Pll_input_division_A,
1.214 - Pll_output_division0_A, Pll_output_division1_A)),
1.215 +static Pll clock_pll_A(Source(mux_external),
1.216 + Control_pll(Pll_enable_A, Pll_stable_A, Pll_bypass_A),
1.217 + Divider_pll(Pll_multiplier_A, Pll_input_division_A,
1.218 + Pll_output_division0_A, Pll_output_division1_A)),
1.219
1.220 - clock_pll_E(Source(mux_external),
1.221 - Control_pll(Pll_enable_E, Pll_stable_E, Pll_bypass_E),
1.222 - Divider_pll(Pll_multiplier_E, Pll_input_division_E,
1.223 - Pll_output_division0_E, Pll_output_division1_E)),
1.224 + clock_pll_E(Source(mux_external),
1.225 + Control_pll(Pll_enable_E, Pll_stable_E, Pll_bypass_E),
1.226 + Divider_pll(Pll_multiplier_E, Pll_input_division_E,
1.227 + Pll_output_division0_E, Pll_output_division1_E)),
1.228
1.229 - clock_pll_M(Source(mux_external),
1.230 - Control_pll(Pll_enable_M, Pll_stable_M, Pll_bypass_M),
1.231 - Divider_pll(Pll_multiplier_M, Pll_input_division_M,
1.232 - Pll_output_division0_M, Pll_output_division1_M));
1.233 + clock_pll_M(Source(mux_external),
1.234 + Control_pll(Pll_enable_M, Pll_stable_M, Pll_bypass_M),
1.235 + Divider_pll(Pll_multiplier_M, Pll_input_division_M,
1.236 + Pll_output_division0_M, Pll_output_division1_M));
1.237
1.238
1.239
1.240 @@ -473,7 +476,7 @@
1.241 int
1.242 Cpm_x1600_chip::get_parameters(enum Clock_identifiers clock, uint32_t parameters[])
1.243 {
1.244 - Clock_divided *clk = dynamic_cast<Clock_divided *>(clocks[clock]);
1.245 + Clock_divided_base *clk = dynamic_cast<Clock_divided_base *>(clocks[clock]);
1.246
1.247 if (clk != NULL)
1.248 return clk->get_parameters(_cpm_regs, parameters);
1.249 @@ -484,7 +487,7 @@
1.250 void
1.251 Cpm_x1600_chip::set_parameters(enum Clock_identifiers clock, uint32_t parameters[])
1.252 {
1.253 - Clock_divided *clk = dynamic_cast<Clock_divided *>(clocks[clock]);
1.254 + Clock_divided_base *clk = dynamic_cast<Clock_divided_base *>(clocks[clock]);
1.255
1.256 if (clk != NULL)
1.257 clk->set_parameters(_cpm_regs, parameters);
1.258 @@ -540,7 +543,7 @@
1.259
1.260 // Switch to the MPLL and attempt to set the divider.
1.261
1.262 - Clock *lcd = dynamic_cast<Clock *>(clocks[Clock_lcd_pixel]);
1.263 + Clock_divided_base *lcd = dynamic_cast<Clock_divided_base *>(clocks[Clock_lcd_pixel]);
1.264 Clock_base *pll = clocks[Clock_pll_M];
1.265
1.266 if (lcd != NULL)