1 /* 2 * MSC (MMC/SD controller) peripheral support. 3 * 4 * Copyright (C) 2024 Paul Boddie <paul@boddie.org.uk> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 19 * Boston, MA 02110-1301, USA 20 */ 21 22 #include <l4/devices/hw_mmio_register_block.h> 23 #include <l4/sys/irq.h> 24 #include <l4/util/util.h> 25 26 #include <math.h> 27 #include <stdio.h> 28 29 #include "msc-common.h" 30 #include "msc-defs.h" 31 32 33 34 // Command frame: 35 // byte: start (1), direction (1), command (6) 36 // 4 bytes: argument 37 // byte: CRC (7), end (1) 38 39 // IO_RW_DIRECT argument: 40 // Argument MSB to LSB: R/W (1), function number (3), read after write flag (1), 41 // stuff (1), register address (17), stuff (1), 42 // write data or stuff (8) 43 // 0x88000c08: W, function = 0, read after write, register address = 6 (CCCR), 44 // data = 8 (reset) 45 46 const uint32_t Io_rw_direct_reset = 0x88000c08; 47 48 // (IO_)SEND_OP_COND argument and default voltage range expected in R3, R4: 49 // Argument MSB to LSB: stuff (8), voltage range (16), reserved (8) 50 // 0x00ff8000: voltage range 2.7 - 3.6V 51 52 const uint32_t Ocr_default_voltage_range = 0x00ff8000; 53 54 // SEND_IF_COND argument and default voltage range expected in R7: 55 // Argument MSB to LSB: stuff (20), voltage supplied (4), check (8) 56 // 0x000001aa: voltage range 2.7 - 3.6V, check = 0b10101010 57 58 const uint32_t If_cond_default_voltage_range = 0x000001aa; 59 60 61 62 // Utilities. 63 64 static enum Command_data_control_bits 65 encode_bus_width(uint8_t width) 66 { 67 switch (width) 68 { 69 case 4: return Cdc_bus_width_field_4bit; 70 case 1: return Cdc_bus_width_field_1bit; 71 default: return Cdc_bus_width_field_1bit; 72 } 73 } 74 75 76 77 // Channel abstraction. 78 79 Msc_channel::Msc_channel(l4_addr_t msc_start, l4_addr_t addr, l4_cap_idx_t irq, 80 Cpm_chip *cpm, enum Clock_identifiers clock) 81 : _msc_start(msc_start), _irq(irq), _cpm(cpm), _clock(clock) 82 { 83 _regs = new Hw::Mmio_register_block<32>(addr); 84 } 85 86 Msc_channel::~Msc_channel() 87 { 88 } 89 90 // Utility methods. 91 // NOTE: Also defined in the CPM abstraction, should be consolidated. 92 93 uint32_t 94 Msc_channel::get_field(uint32_t reg, uint32_t mask, uint8_t shift) 95 { 96 return (_regs[reg] & (mask << shift)) >> shift; 97 } 98 99 void 100 Msc_channel::set_field(uint32_t reg, uint32_t mask, uint8_t shift, uint32_t value) 101 { 102 _regs[reg] = (_regs[reg] & (~(mask << shift))) | ((mask & value) << shift); 103 } 104 105 bool 106 Msc_channel::set_clock_frequency(uint64_t frequency) 107 { 108 uint64_t division = _cpm->get_frequency(_clock) / frequency; 109 double divider = ceil(log2(division)); 110 111 if ((divider < 0) || (divider > Clock_rate_field_mask)) 112 return false; 113 114 set_field(Msc_clock_rate, Clock_rate_field_mask, Clock_rate_field_shift, 115 (uint32_t) divider); 116 117 return true; 118 } 119 120 void 121 Msc_channel::reset() 122 { 123 _regs[Msc_control] = _regs[Msc_control] | Control_reset; 124 125 while (_regs[Msc_status] & Status_resetting); 126 } 127 128 void 129 Msc_channel::start_clock() 130 { 131 set_field(Msc_control, Control_clock_control_field_mask, 132 Control_clock_control_field_shift, Control_clock_control_start); 133 134 while (!(_regs[Msc_status] & Status_clock_enabled)); 135 } 136 137 void 138 Msc_channel::stop_clock() 139 { 140 set_field(Msc_control, Control_clock_control_field_mask, 141 Control_clock_control_field_shift, Control_clock_control_stop); 142 143 while (_regs[Msc_status] & Status_clock_enabled); 144 } 145 146 void 147 Msc_channel::ack_irq(uint32_t flags) 148 { 149 // Clear the flags by setting them. 150 151 _regs[Msc_interrupt_flag] = _regs[Msc_interrupt_flag] | flags; 152 } 153 154 void 155 Msc_channel::unmask_irq(uint32_t flags) 156 { 157 ack_irq(flags); 158 159 if (_regs[Msc_interrupt_mask] & flags) 160 _regs[Msc_interrupt_mask] = _regs[Msc_interrupt_mask] & ~flags; 161 } 162 163 bool 164 Msc_channel::command_will_write(uint8_t index) 165 { 166 // NOTE: Probably incomplete coverage. 167 168 switch (index) 169 { 170 case Command_write_dat_until_stop: return true; 171 case Command_write_block: return true; 172 case Command_write_multiple_block: return true; 173 case Command_program_cid: return true; 174 case Command_program_csd: return true; 175 case Command_lock_unlock: return true; 176 default: return false; 177 } 178 } 179 180 bool 181 Msc_channel::app_command_will_write(uint8_t index) 182 { 183 // NOTE: Probably incomplete coverage. 184 185 (void) index; 186 187 return false; 188 } 189 190 bool 191 Msc_channel::command_with_data(uint8_t index) 192 { 193 // NOTE: Probably incomplete coverage. 194 195 switch (index) 196 { 197 case Command_read_dat_until_stop: return true; 198 case Command_read_single_block: return true; 199 case Command_read_multiple_block: return true; 200 case Command_write_dat_until_stop: return true; 201 case Command_write_block: return true; 202 case Command_write_multiple_block: return true; 203 case Command_program_cid: return true; 204 case Command_program_csd: return true; 205 case Command_lock_unlock: return true; 206 default: return false; 207 } 208 } 209 210 bool 211 Msc_channel::app_command_with_data(uint8_t index) 212 { 213 // NOTE: Probably incomplete coverage. 214 215 switch (index) 216 { 217 case App_command_sd_status: return true; 218 case App_command_send_num_wr_blocks: return true; 219 case App_command_send_scr: return true; 220 default: return false; 221 } 222 } 223 224 bool 225 Msc_channel::command_uses_busy(uint8_t index) 226 { 227 // NOTE: Probably incomplete coverage. 228 229 switch (index) 230 { 231 case Command_select_deselect_card: return true; 232 case Command_stop_transmission: return true; 233 default: return false; 234 } 235 } 236 237 bool 238 Msc_channel::app_command_uses_busy(uint8_t index) 239 { 240 // NOTE: Probably incomplete coverage. 241 242 (void) index; 243 244 return false; 245 } 246 247 uint8_t 248 Msc_channel::get_response_format(uint8_t index) 249 { 250 // NOTE: Probably incomplete coverage. 251 252 switch (index) 253 { 254 // Common commands without response. 255 256 case Command_go_idle_state: return 0; 257 case Command_set_dsr: return 0; 258 case Command_go_inactive_state: return 0; 259 260 // Common commands with response. 261 262 case Command_send_op_cond: return 3; 263 case Command_all_send_cid: return 2; 264 case Command_send_csd: return 2; 265 case Command_send_cid: return 2; 266 267 // SDIO only. 268 269 case Command_io_send_op_cond: return 4; 270 case Command_io_rw_direct: return 5; 271 272 // SDMEM only. 273 274 case Command_send_relative_addr: return 6; 275 case Command_send_if_cond: return 7; 276 277 // All other commands. 278 279 default: return 1; 280 } 281 } 282 283 uint8_t 284 Msc_channel::get_app_response_format(uint8_t index) 285 { 286 // NOTE: Probably incomplete coverage. 287 288 switch (index) 289 { 290 // SDMEM only. 291 292 case App_command_sd_send_op_cond: return 3; 293 294 // All other commands. 295 296 default: return 1; 297 } 298 } 299 300 // Read a response directly from the FIFO. 301 302 void 303 Msc_channel::read_response(uint16_t *buffer, uint8_t units) 304 { 305 uint8_t unit = units; 306 307 while (unit > 0) 308 { 309 uint32_t data = _regs[Msc_response_fifo]; 310 311 // Ignore the upper byte of the last unit in small transfers since it is the 312 // lower byte from the previous unit not shifted out of the register. 313 314 unit--; 315 316 if ((unit == 0) && (units == 3)) 317 buffer[unit] = (data & 0xff) << 8; 318 else 319 buffer[unit] = data; 320 } 321 } 322 323 // Send an application-specific command. 324 325 bool 326 Msc_channel::send_app_command(uint8_t index, uint32_t arg) 327 { 328 if (!send_command(Command_app_cmd, _cards[_card].rca << 16)) 329 return false; 330 331 return send_command(index, arg, get_app_response_format(index), 332 app_command_with_data(index), 333 app_command_will_write(index), 334 app_command_uses_busy(index)); 335 } 336 337 // Send a common MMC/SD command. 338 339 bool 340 Msc_channel::send_command(uint8_t index, uint32_t arg) 341 { 342 return send_command(index, arg, get_response_format(index), 343 command_with_data(index), 344 command_will_write(index), 345 command_uses_busy(index)); 346 } 347 348 // Initiate a command having the given index and using the given argument, 349 // employing the specified response format and involving a data transfer if 350 // indicated. 351 352 bool 353 Msc_channel::send_command(uint8_t index, uint32_t arg, uint8_t response_format, 354 bool data, bool write, bool busy) 355 { 356 stop_clock(); 357 358 // Enable DMA for data transfers. 359 // NOTE: Needed for JZ4780 and later SoCs. 360 361 _regs[Msc_dma_control] = (data ? Dma_select_common_dma | Dma_enable : Dma_disable); 362 363 // Set the command index and argument. 364 365 _regs[Msc_command_index] = index; 366 _regs[Msc_command_argument] = arg; 367 368 // Configure the response format and data bus width. 369 370 set_field(Msc_command_data_control, Cdc_response_format_field_mask, 371 Cdc_response_format_field_shift, response_format); 372 373 // NOTE: May need to set the SD bus width. 374 375 set_field(Msc_command_data_control, Cdc_bus_width_field_mask, 376 Cdc_bus_width_field_shift, encode_bus_width(_cards[_card].bus_width)); 377 378 set_field(Msc_command_data_control, Cdc_recv_fifo_level_field_mask, 379 Cdc_recv_fifo_level_field_shift, Cdc_fifo_level_16); 380 381 set_field(Msc_command_data_control, Cdc_trans_fifo_level_field_mask, 382 Cdc_trans_fifo_level_field_shift, Cdc_fifo_level_16); 383 384 // Set and clear control bits appropriate to the command. 385 // NOTE: Pre-JZ4780 SoCs enable DMA in this register. 386 387 _regs[Msc_command_data_control] = _regs[Msc_command_data_control] | 388 // (data ? Cdc_dma_enable : Cdc_dma_disable) | 389 (busy ? Cdc_expect_busy : Cdc_do_not_expect_busy) | 390 (data ? Cdc_data_with_command : Cdc_no_data_with_command) | 391 (write ? Cdc_write_operation : Cdc_read_operation); 392 393 _regs[Msc_command_data_control] = _regs[Msc_command_data_control] & 394 ~( 395 // (data ? Cdc_dma_disable : Cdc_dma_enable) | 396 (busy ? Cdc_do_not_expect_busy : Cdc_expect_busy) | 397 (data ? Cdc_no_data_with_command : Cdc_data_with_command) | 398 (write ? Cdc_read_operation : Cdc_write_operation) | 399 Cdc_stream_block | Cdc_init_sequence); 400 401 // Unmask interrupts, start the clock, then initiate the command. 402 403 uint32_t flags = Int_end_command_response | Int_response_timeout; 404 405 unmask_irq(flags); 406 start_clock(); 407 408 _regs[Msc_control] = _regs[Msc_control] | Control_start_operation; 409 410 // Wait for command completion. 411 412 if (!wait_for_irq(flags)) 413 return false; 414 415 // Determine whether a timeout occurred. 416 417 bool have_response = !((_regs[Msc_interrupt_flag] & Int_response_timeout) || 418 (_regs[Msc_status] & Status_response_crc_error) || 419 (_regs[Msc_status] & Status_timeout_response)); 420 421 // Acknowledge the response interrupts and return the status. 422 423 ack_irq(flags); 424 return have_response; 425 } 426 427 // Wait indefinitely for an interrupt request, returning true if one was delivered. 428 429 bool 430 Msc_channel::wait_for_irq(uint32_t flags) 431 { 432 return !l4_error(l4_irq_receive(_irq, L4_IPC_NEVER)) && 433 (_regs[Msc_interrupt_flag] & flags); 434 } 435 436 // Wait up to the given timeout (in microseconds) for an interrupt request, 437 // returning true if one was delivered. 438 439 bool 440 Msc_channel::wait_for_irq(uint32_t flags, unsigned int timeout) 441 { 442 return !l4_error(l4_irq_receive(_irq, l4_timeout(L4_IPC_TIMEOUT_NEVER, 443 l4util_micros2l4to(timeout)))) && 444 (_regs[Msc_interrupt_flag] & flags); 445 } 446 447 448 449 // Check the voltage range of the SD card, potentially establishing that it is 450 // a high capacity card. Return false if the voltage range is incompatible. 451 452 bool 453 Msc_channel::check_sd() 454 { 455 struct R7 r7; 456 457 // Send an interface condition command. 458 // A card may not respond to this command. 459 460 if (!send_command(Command_send_if_cond, If_cond_default_voltage_range)) 461 return true; 462 463 read_response((uint16_t *) &r7, Response_size_R7); 464 465 // Reject any card not supporting the default voltage range. 466 467 if (r7.check_voltage.raw != If_cond_default_voltage_range) 468 return false; 469 470 return true; 471 } 472 473 // Check the voltage range of the SDIO card, inactivating it if incompatible. 474 475 void 476 Msc_channel::init_sdio() 477 { 478 struct R4 r4; 479 uint32_t ocr = 0; 480 481 // Reset any SDIO card or IO unit in a combined memory/IO card. 482 // A non-SDIO card may not respond to this command. 483 484 if (!send_command(Command_io_rw_direct, Io_rw_direct_reset)) 485 return; 486 487 // Attempt to assert the operating conditions. 488 489 do 490 { 491 // Obtain OCR (operating conditions register) values for any IO card. 492 // Without a response, the card may have inactivated itself due to voltage 493 // range incompatibility reasons. 494 495 if (!send_command(Command_io_send_op_cond, ocr)) 496 return; 497 498 read_response((uint16_t *) &r4, Response_size_R4); 499 500 // Finish if no IO functions provided. 501 // NOTE: Should only need to check this the first time. 502 503 if (r4.number_io_functions == 0) 504 return; 505 506 if (r4.ocr != Ocr_default_voltage_range) 507 { 508 ocr = Ocr_default_voltage_range; 509 continue; 510 } 511 } 512 while (!r4.ready); 513 } 514 515 void 516 Msc_channel::init_sdmem() 517 { 518 struct R3 r3; 519 520 // Incorporate the HCS bit into the OCR for SDMEM. 521 522 uint32_t ocr = Ocr_high_capacity_storage; 523 524 do 525 { 526 if (!send_app_command(App_command_sd_send_op_cond, ocr)) 527 return; 528 529 read_response((uint16_t *) &r3, Response_size_R3); 530 531 if (r3.ocr != Ocr_default_voltage_range) 532 { 533 ocr = Ocr_default_voltage_range | Ocr_high_capacity_storage; 534 continue; 535 } 536 } 537 while (!(r3.ocr & Ocr_card_powered_up)); 538 } 539 540 void 541 Msc_channel::init_mmc() 542 { 543 // Obtain OCR (operating conditions register) values for each card using 544 // send_op_cond command variants without argument, or assert operating 545 // conditions with argument to avoid handling card responses. Where responses 546 // are solicited, the host must determine a suitable argument and reissue the 547 // command. 548 549 struct R3 r3; 550 uint32_t ocr = 0; 551 552 do 553 { 554 if (!send_command(Command_send_op_cond, ocr)) 555 return; 556 557 read_response((uint16_t *) &r3, Response_size_R3); 558 559 if (r3.ocr != Ocr_default_voltage_range) 560 { 561 ocr = Ocr_default_voltage_range; 562 continue; 563 } 564 } 565 while (!(r3.ocr & Ocr_card_powered_up)); 566 } 567 568 void 569 Msc_channel::identify_cards() 570 { 571 struct R2 r2; 572 struct R6 r6; 573 574 _num_cards = 0; 575 576 while (send_command(Command_all_send_cid, 0)) 577 { 578 read_response((uint16_t *) &r2, Response_size_R2); 579 580 _cards[_num_cards].cid = r2.payload.cid; 581 582 printf("card: %d\n", _num_cards); 583 printf("date: %d %d\n", r2.payload.cid.month, r2.payload.cid.year); 584 printf("serial: %d\n", r2.payload.cid.serial); 585 printf("revision: %d\n", r2.payload.cid.revision); 586 printf("name: %c%c%c%c%c\n", r2.payload.cid.name[4], r2.payload.cid.name[3], 587 r2.payload.cid.name[2], r2.payload.cid.name[1], 588 r2.payload.cid.name[0]); 589 printf("oem: %d\n", r2.payload.cid.oem); 590 printf("manufacturer: %d\n", r2.payload.cid.manufacturer); 591 592 // Try and obtain a card-issued address. 593 594 if (send_command(Command_send_relative_addr, 0)) 595 { 596 read_response((uint16_t *) &r6, Response_size_R6); 597 _cards[_num_cards].rca = r6.rca; 598 } 599 600 // Try and assign an address. 601 // Employ 1-based relative addressing. 602 603 else if (send_command(Command_set_relative_addr, _num_cards + 1)) 604 _cards[_num_cards].rca = _num_cards + 1; 605 606 // Otherwise, stop identification. 607 608 else 609 return; 610 611 // Set the default bus width to be determined. 612 613 _cards[_num_cards].bus_width = 0; 614 615 _num_cards++; 616 } 617 } 618 619 void 620 Msc_channel::query_cards() 621 { 622 struct R2 r2; 623 struct R3 r3; 624 uint8_t card; 625 626 for (card = 0; card < _num_cards; card++) 627 { 628 // Employ 1-based relative addressing. 629 630 if (!send_command(Command_send_csd, _cards[card].rca << 16)) 631 return; 632 633 read_response((uint16_t *) &r2, Response_size_R2); 634 635 _cards[card].csd = r2.payload.csd; 636 637 struct CSD *csd = &_cards[card].csd; 638 639 printf("card: %d\n", card); 640 printf("csd: %d\n", csd->csd); 641 printf("copy: %s\n", csd->copy ? "copied" : "original"); 642 printf("card command classes: %03x\n", csd->card_command_classes); 643 printf("device (size multiplier): %d %d\n", csd->device_size + 1, 644 1 << (csd->device_size_multiplier + 2)); 645 printf("device size: %d\n", (1 << csd->read_blocklen) * 646 (csd->device_size + 1) * 647 (1 << (csd->device_size_multiplier + 2))); 648 printf("transfer speed: %d MHz\n", csd->tran_speed == 0x32 ? 25 : 50); 649 printf("format group: %d %d\n", csd->format, r2.payload.csd.format_group); 650 printf("write time factor: %d\n", 1 << csd->write_time_factor); 651 printf("write protect (temp perm): %s %s\n", csd->temp_write_prot ? "yes" : "no", 652 csd->perm_write_prot ? "yes" : "no"); 653 printf("write protect group (enable size): %s %d\n", csd->write_prot_group_enable ? "yes" : "no", 654 csd->write_prot_group_size + 1); 655 printf("write block (partial length): %s %d\n", csd->write_block_partial ? "yes" : "no", 656 1 << csd->write_blocklen); 657 printf("read block (partial length): %s %d\n", csd->read_block_partial ? "yes" : "no", 658 1 << csd->read_blocklen); 659 printf("erase: sector single: %d %s\n", csd->erase_sector_size + 1, 660 csd->erase_single_block_enable ? "yes" : "no"); 661 printf("misalign: read write: %s %s\n", csd->read_block_misalign ? "yes" : "no", 662 csd->write_block_misalign ? "yes" : "no"); 663 printf("max read current (min max): %d %d\n", csd->max_read_current_min, 664 csd->max_read_current_max); 665 printf("max write current (min max): %d %d\n", csd->max_write_current_min, 666 csd->max_write_current_max); 667 printf("read access time (1 2): %d %d\n", csd->data_read_access_time_1, 668 csd->data_read_access_time_2); 669 printf("DSR: %s\n", csd->dsr_implemented ? "yes" : "no"); 670 671 // Query the OCR again now that we can associate it with a specific card. 672 673 if (!send_app_command(App_command_read_ocr, 0)) 674 return; 675 676 read_response((uint16_t *) &r3, Response_size_R3); 677 678 _cards[card].ocr = r3.ocr; 679 } 680 } 681 682 683 684 // Enable the controller and identify cards. 685 686 void 687 Msc_channel::enable() 688 { 689 // NOTE: X1600 and other recent SoCs only. 690 691 _regs[Msc_low_power_mode] = _regs[Msc_low_power_mode] & ~Low_power_mode_enable; 692 693 stop_clock(); 694 reset(); 695 696 // Slow the clock for initialisation. 697 // NOTE: Should produce an error. 698 699 if (!set_clock_frequency(400000)) 700 return; 701 702 send_command(Command_go_idle_state, 0); 703 704 if (check_sd()) 705 { 706 init_sdio(); 707 init_sdmem(); 708 } 709 710 init_mmc(); 711 identify_cards(); 712 query_cards(); 713 714 // Initially, no card is selected. 715 716 _card = -1; 717 } 718 719 // Obtain the card details. 720 721 struct msc_card * 722 Msc_channel::get_cards() 723 { 724 return _cards; 725 } 726 727 // Return the number of active cards. 728 729 uint8_t 730 Msc_channel::num_cards() 731 { 732 return _num_cards; 733 } 734 735 // Receive data from the selected card. 736 737 uint32_t 738 Msc_channel::recv_data(struct dma_region *region, uint32_t count) 739 { 740 if (count > region->size) 741 return 0; 742 743 uint32_t flags = Int_data_transfer_done; 744 745 unmask_irq(flags); 746 747 uint32_t to_transfer = transfer(_msc_start + Msc_recv_data_fifo, region->paddr, true, count); 748 749 wait_for_irq(flags); 750 ack_irq(flags); 751 752 if (!to_transfer || 753 (_regs[Msc_status] & Status_read_crc_error) || 754 (_regs[Msc_status] & Status_timeout_read)) 755 return 0; 756 757 return to_transfer; 758 } 759 760 // Send data to the selected card. 761 762 uint32_t 763 Msc_channel::send_data(struct dma_region *region, uint32_t count) 764 { 765 if (count > region->size) 766 return 0; 767 768 uint32_t flags = Int_data_transfer_done; 769 770 unmask_irq(flags); 771 772 uint32_t to_transfer = transfer(region->paddr, _msc_start + Msc_trans_data_fifo, false, count); 773 774 wait_for_irq(flags); 775 ack_irq(flags); 776 777 if (!to_transfer || 778 (_regs[Msc_status] & Status_write_crc_error_data) || 779 (_regs[Msc_status] & Status_write_crc_error_no_status)) 780 return 0; 781 782 return to_transfer; 783 } 784 785 // Read blocks from the indicated card into a memory region. 786 787 uint32_t 788 Msc_channel::read_blocks(uint8_t card, struct dma_region *region, 789 uint32_t block_address, uint32_t block_count) 790 { 791 uint32_t block_size = 1 << _cards[card].csd.read_blocklen; 792 struct R1 r1; 793 794 // Select the requested card. 795 796 if (_card != card) 797 { 798 // Choose an appropriate clock frequency for the card. 799 // NOTE: Should produce an error. 800 801 if (!set_clock_frequency(_cards[card].csd.tran_speed == 0x32 ? 802 25000000 : 50000000)) 803 return 0; 804 805 if (!send_command(Command_select_deselect_card, _cards[card].rca << 16)) 806 return 0; 807 808 read_response((uint16_t *) &r1, Response_size_R1); 809 810 if (r1.status & R1_status_error_mask) 811 return 0; 812 813 _card = card; 814 } 815 816 // NOTE: SMEM cards should allow bus width setting with the SCR register 817 // NOTE: describing the permitted values. 818 // NOTE: SDIO cards have their bus width set in CCCR via CMD52. 819 820 if (!_cards[card].bus_width) 821 { 822 if (send_app_command(App_command_set_bus_width, Bus_width_4bit)) 823 _cards[card].bus_width = 4; 824 else 825 _cards[card].bus_width = 1; 826 } 827 828 if (!send_command(Command_set_blocklen, block_size)) 829 return 0; 830 831 read_response((uint16_t *) &r1, Response_size_R1); 832 833 if (r1.status & R1_status_error_mask) 834 return 0; 835 836 // NOTE: Consider issuing a predefined block count command to any multiple 837 // NOTE: block operation, at least for cards that support it. 838 839 // Apply block count and size properties to the issued command. 840 841 _regs[Msc_block_count] = block_count; 842 _regs[Msc_block_length] = block_size; 843 844 // Where CCS = 0, byte addressing is used. Otherwise, block addressing is used. 845 846 uint32_t address; 847 848 if (_cards[card].ocr & Ocr_high_capacity_storage) 849 address = block_address; 850 else 851 address = block_address * block_size; 852 853 if (!send_command(block_count == 1 ? Command_read_single_block 854 : Command_read_multiple_block, address)) 855 return 0; 856 857 read_response((uint16_t *) &r1, Response_size_R1); 858 859 if (r1.status & R1_status_error_mask) 860 return 0; 861 862 // NOTE: Use Msc_block_success_count instead. 863 864 uint32_t transferred = recv_data(region, block_size * block_count); 865 866 if (block_count > 1) 867 send_command(Command_stop_transmission, 0); 868 869 return transferred; 870 } 871 872 873 874 // Peripheral abstraction. 875 876 Msc_chip::Msc_chip(l4_addr_t msc_start, l4_addr_t start, l4_addr_t end, 877 Cpm_chip *cpm) 878 : _msc_start(msc_start), _start(start), _end(end), _cpm(cpm) 879 { 880 }