1 /* 2 * JZ4780 HDMI peripheral support. 3 * 4 * Copyright (C) 2020 Paul Boddie <paul@boddie.org.uk> 5 * 6 * Techniques and operations introduced from the Linux DRM bridge driver for 7 * Synopsys DW-HDMI whose authors are as follows: 8 * 9 * Copyright (C) 2013-2015 Mentor Graphics Inc. 10 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. 11 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de> 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of 16 * the License, or (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 26 * Boston, MA 02110-1301, USA 27 * 28 * ---- 29 * 30 * Some acronyms: 31 * 32 * CEC (Consumer Electronics Control) is a HDMI device control interface for up 33 * to 15 devices. 34 * 35 * CSC (Colour Space Conversion) is the processing needed to convert from one 36 * representation of colours to another. 37 * 38 * HEAC (HDMI Ethernet and Audio Return Channel) is a combination of HEC (HDMI 39 * Ethernet Channel) which provides a 100Mb/s bidirectional link and ARC (Audio 40 * Return Channel) which permits the consumption of audio data from the device. 41 * 42 * MHL (Mobile High-Definition Link) is an adaptation of HDMI for mobile 43 * devices. 44 * 45 * TMDS (Transition-Minimized Differential Signaling) is the method by which 46 * audio, control and video data are all sent to the device. 47 */ 48 49 #include <l4/devices/hdmi-jz4780.h> 50 #include <l4/devices/hw_mmio_register_block.h> 51 #include <l4/devices/lcd-jz4740-config.h> 52 53 #include <l4/sys/irq.h> 54 #include <l4/util/util.h> 55 56 #include <cstdio> 57 58 /* 59 I2C pins: 60 61 HDMI: PF25/SMB4_SDA/DDCSDA, PF24/SMB4_SCK/DDCSCK 62 63 See: http://mipscreator.imgtec.com/CI20/hardware/board/ci20_jz4780_v2.0.pdf 64 */ 65 66 enum Regs 67 { 68 // Identification. 69 70 Design_id = 0x000, // DESIGN_ID 71 Revision_id = 0x001, // REVISION_ID 72 Product_id0 = 0x002, // PRODUCT_ID0 73 Product_id1 = 0x003, // PRODUCT_ID1 74 Config_id0 = 0x004, // CONFIG_ID0 75 Config_id1 = 0x005, // CONFIG_ID1 76 Config_id2 = 0x006, // CONFIG_ID2 77 Config_id3 = 0x007, // CONFIG_ID3 78 79 // Top-level interrupt control. 80 81 Int_mask = 0x1ff, // MUTE 82 83 // Interrupt status and mask for various functions. 84 85 Fc_int_status0 = 0x100, // FC_STAT0 86 Fc_int_status1 = 0x101, // FC_STAT1 87 Fc_int_status2 = 0x102, // FC_STAT2 88 As_int_status = 0x103, // AS_STAT0 89 Phy_int_status = 0x104, // PHY_STAT0 90 Cec_int_status = 0x106, // CEC_STAT0 91 Vp_int_status = 0x107, // VP_STAT0 92 Ahb_dma_audio_int_status = 0x109, // AHBDMAAUD_STAT0 93 94 Fc_int_mask0 = 0x180, // MUTE_FC_STAT0 95 Fc_int_mask1 = 0x181, // MUTE_FC_STAT1 96 Fc_int_mask2 = 0x182, // MUTE_FC_STAT2 97 As_int_mask = 0x183, // MUTE_AS_STAT0 98 Phy_int_mask = 0x184, // MUTE_PHY_STAT0 99 Cec_int_mask = 0x186, // MUTE_CEC_STAT0 100 Vp_int_mask = 0x187, // MUTE_VP_STAT0 101 Ahb_dma_audio_int_mask = 0x189, // MUTE_AHBDMAAUD_STAT0 102 103 // I2C for E-DDC. 104 105 I2c_int_status = 0x105, // I2CM_STAT0 106 I2c_int_mask = 0x185, // MUTE_I2CM_STAT0 107 108 I2c_device_address = 0x7e00, // I2CM_SLAVE 109 I2c_register = 0x7e01, // I2CM_ADDRESS 110 I2c_data_out = 0x7e02, // I2CM_DATAO 111 I2c_data_in = 0x7e03, // I2CM_DATAI 112 I2c_operation = 0x7e04, // I2CM_OPERATION 113 I2c_int_config0 = 0x7e05, // I2CM_INT 114 I2c_int_config1 = 0x7e06, // I2CM_CTLINT 115 I2c_divider = 0x7e07, // I2CM_DIV 116 I2c_segment_address = 0x7e08, // I2CM_SEGADDR 117 I2c_software_reset = 0x7e09, // I2CM_SOFTRSTZ 118 I2c_segment_pointer = 0x7e0a, // I2CM_SEGPTR 119 120 // I2C for PHY. 121 122 I2c_phy_int_status = 0x108, // I2CMPHY_STAT0 123 I2c_phy_int_mask = 0x188, // MUTE_I2CMPHY_STAT0 124 125 I2c_phy_device_address = 0x3020, // PHY_I2CM_SLAVE_ADDR 126 I2c_phy_register = 0x3021, // PHY_I2CM_ADDRESS_ADDR 127 I2c_phy_data_out1 = 0x3022, // PHY_I2CM_DATAO_1_ADDR 128 I2c_phy_data_out0 = 0x3023, // PHY_I2CM_DATAO_0_ADDR 129 I2c_phy_data_in1 = 0x3024, // PHY_I2CM_DATAI_1_ADDR 130 I2c_phy_data_in0 = 0x3025, // PHY_I2CM_DATAI_0_ADDR 131 I2c_phy_operation = 0x3026, // PHY_I2CM_OPERATION_ADDR 132 I2c_phy_int_config0 = 0x3027, // PHY_I2CM_INT_ADDR 133 I2c_phy_int_config1 = 0x3028, // PHY_I2CM_CTLINT_ADDR 134 I2c_phy_divider = 0x3029, // PHY_I2CM_DIV_ADDR 135 I2c_phy_software_reset = 0x302a, // PHY_I2CM_SOFTRSTZ_ADDR 136 137 // PHY registers. 138 139 Phy_config = 0x3000, // PHY_CONF0 140 Phy_test0 = 0x3001, // PHY_TST0 141 Phy_test1 = 0x3002, // PHY_TST1 142 Phy_test2 = 0x3003, // PHY_TST2 143 Phy_status = 0x3004, // PHY_STAT0 144 Phy_int_config = 0x3005, // PHY_INT0 145 Phy_mask = 0x3006, // PHY_MASK0 146 Phy_polarity = 0x3007, // PHY_POL0 147 148 // Main controller registers. 149 150 Main_clock_disable = 0x4001, // MC_CLKDIS 151 Main_software_reset = 0x4002, // MC_SWRSTZ 152 Main_flow_control = 0x4004, // MC_FLOWCTRL 153 Main_reset = 0x4005, // MC_PHYRSTZ 154 Main_heac_phy_reset = 0x4007, // MC_HEACPHY_RST 155 156 // Frame composer registers for input video. 157 158 Fc_video_config = 0x1000, // FC_INVIDCONF 159 Fc_horizontal_active_width0 = 0x1001, // FC_INHACTV0 160 Fc_horizontal_active_width1 = 0x1002, // FC_INHACTV1 161 Fc_horizontal_blank_width0 = 0x1003, // FC_INHBLANK0 162 Fc_horizontal_blank_width1 = 0x1004, // FC_INHBLANK1 163 Fc_vertical_active_height0 = 0x1005, // FC_INVACTV0 164 Fc_vertical_active_height1 = 0x1006, // FC_INVACTV1 165 Fc_vertical_blank_height = 0x1007, // FC_INVBLANK 166 167 // Frame composer registers for sync pulses. 168 169 Fc_hsync_delay0 = 0x1008, // FC_HSYNCINDELAY0 170 Fc_hsync_delay1 = 0x1009, // FC_HSYNCINDELAY1 171 Fc_hsync_width0 = 0x100A, // FC_HSYNCINWIDTH0 172 Fc_hsync_width1 = 0x100B, // FC_HSYNCINWIDTH1 173 Fc_vsync_delay = 0x100C, // FC_VSYNCINDELAY 174 Fc_vsync_height = 0x100D, // FC_VSYNCINWIDTH 175 176 // Frame composer registers for video path configuration. 177 178 Fc_control_duration = 0x1011, // FC_CTRLDUR 179 Fc_ex_control_duration = 0x1012, // FC_EXCTRLDUR 180 Fc_ex_control_space = 0x1013, // FC_EXCTRLSPAC 181 Fc_channel0_preamble = 0x1014, // FC_CH0PREAM 182 Fc_channel1_preamble = 0x1015, // FC_CH1PREAM 183 Fc_channel2_preamble = 0x1016, // FC_CH2PREAM 184 185 // Colour space conversion registers. 186 187 Csc_config = 0x4100, // CSC_CFG 188 Csc_scale = 0x4101, // CSC_SCALE 189 190 // HDCP registers. 191 192 Hdcp_config0 = 0x5000, // A_HDCPCFG0 193 Hdcp_config1 = 0x5001, // A_HDCPCFG1 194 Hdcp_video_polarity = 0x5009, // A_VIDPOLCFG 195 196 // Video sample registers. 197 198 Sample_video_config = 0x0200, // TX_INVID0 199 Sample_video_stuffing = 0x0201, // TX_INSTUFFING 200 Sample_gy_data0 = 0x0202, // TX_GYDATA0 201 Sample_gy_data1 = 0x0203, // TX_GYDATA1 202 Sample_rcr_data0 = 0x0204, // TX_RCRDATA0 203 Sample_rcr_data1 = 0x0205, // TX_RCRDATA1 204 Sample_bcb_data0 = 0x0206, // TX_BCBDATA0 205 Sample_bcb_data1 = 0x0207, // TX_BCBDATA1 206 207 // Video packetizer registers. 208 209 Packet_status = 0x0800, // VP_STATUS 210 Packet_pixel_repeater = 0x0801, // VP_PR_CD 211 Packet_stuffing = 0x0802, // VP_STUFF 212 Packet_remap = 0x0803, // VP_REMAP 213 Packet_config = 0x0804, // VP_CONF 214 }; 215 216 // Identification values. 217 218 enum Product_id_values : unsigned 219 { 220 Product_id0_transmitter = 0xa0, // PRODUCT_ID0_HDMI_TX 221 222 Product_id1_hdcp = 0xc0, // PRODUCT_ID1_HDCP 223 Product_id1_receiver = 0x02, // PRODUCT_ID1_HDMI_RX 224 Product_id1_transmitter = 0x01, // PRODUCT_ID1_HDMI_TX 225 }; 226 227 // Configuration values. 228 229 enum Config_id_values : unsigned 230 { 231 Config_id0_i2s = 0x10, // CONFIG0_I2S 232 Config_id0_cec = 0x02, // CONFIG0_CEC 233 234 Config_id1_ahb = 0x01, // CONFIG1_AHB 235 236 Config2_dwc_hdmi_tx_phy = 0x00, // DWC_HDMI_TX_PHY 237 Config2_dwc_mhl_phy_heac = 0xb2, // DWC_MHL_PHY_HEAC 238 Config2_dwc_mhl_phy = 0xc2, // DWC_MHL_PHY 239 Config2_dwc_hdmi_3d_tx_phy_heac = 0xe2, // DWC_HDMI_3D_TX_PHY_HEAC 240 Config2_dwc_hdmi_3d_tx_phy = 0xf2, // DWC_HDMI_3D_TX_PHY 241 Config2_dwc_hdmi20_tx_phy = 0xf3, // DWC_HDMI20_TX_PHY 242 Config2_vendor_phy = 0xfe, // VENDOR_PHY 243 244 Config_id3_ahb_audio_dma = 0x02, // CONFIG3_AHBAUDDMA 245 Config_id3_gp_audio = 0x01, // CONFIG3_GPAUD 246 }; 247 248 // Status and mask bits. 249 250 enum Int_mask_bits : unsigned 251 { 252 Int_mask_wakeup = 0x02, 253 Int_mask_all = 0x01, 254 }; 255 256 // I2C status and mask bits, also for PHY I2C. 257 258 enum I2c_int_status_bits : unsigned 259 { 260 I2c_int_status_done = 0x02, 261 I2c_int_status_error = 0x01, 262 }; 263 264 // I2C operation bits. 265 266 enum I2c_operation_bits : unsigned 267 { 268 I2c_operation_write = 0x10, 269 I2c_operation_segment_read = 0x02, // not PHY I2C 270 I2c_operation_read = 0x01, 271 }; 272 273 // Device addresses. 274 275 enum I2c_phy_device_addresses : unsigned 276 { 277 I2c_phy_device_phy_gen2 = 0x69, // PHY_I2CM_SLAVE_ADDR_PHY_GEN2 278 I2c_phy_device_phy_heac = 0x49, // PHY_I2CM_SLAVE_ADDR_HEAC_PHY 279 }; 280 281 // Device registers. 282 283 enum I2c_phy_device_registers : unsigned 284 { 285 I2c_phy_3d_tx_clock_cal_ctrl = 0x05, // 3D_TX_PHY_CKCALCTRL 286 I2c_phy_3d_tx_cpce_ctrl = 0x06, // 3D_TX_PHY_CPCE_CTRL 287 I2c_phy_3d_tx_clock_symbol_ctrl = 0x09, // 3D_TX_PHY_CKSYMTXCTRL 288 I2c_phy_3d_tx_vlevel_ctrl = 0x0e, // 3D_TX_PHY_VLEVCTRL 289 I2c_phy_3d_tx_curr_ctrl = 0x10, // 3D_TX_PHY_CURRCTRL 290 I2c_phy_3d_tx_pll_phby_ctrl = 0x13, // 3D_TX_PHY_PLLPHBYCTRL 291 I2c_phy_3d_tx_gmp_ctrl = 0x15, // 3D_TX_PHY_GMPCTRL 292 I2c_phy_3d_tx_msm_ctrl = 0x17, // 3D_TX_PHY_MSM_CTRL 293 I2c_phy_3d_tx_term = 0x19, // 3D_TX_PHY_TXTERM 294 }; 295 296 // PHY I2C register values. 297 298 enum Msm_ctrl_bits : unsigned 299 { 300 Msm_ctrl_clock_output_select_fb = 1 << 3, // 3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK 301 }; 302 303 enum Clock_cal_ctrl_bits : unsigned 304 { 305 Clock_cal_ctrl_override = 1 << 15, // 3D_TX_PHY_CKCALCTRL_OVERRIDE 306 }; 307 308 // Interrupt configuration bits, also for PHY I2C. 309 310 enum I2c_int_config0_bits : unsigned 311 { 312 I2c_int_config0_done_polarity = 0x08, 313 I2c_int_config0_done_mask = 0x04, 314 }; 315 316 enum I2c_int_config1_bits : unsigned 317 { 318 I2c_int_config1_nack_polarity = 0x80, 319 I2c_int_config1_nack_mask = 0x40, 320 I2c_int_config1_arb_polarity = 0x08, 321 I2c_int_config1_arb_mask = 0x04, 322 }; 323 324 // PHY configuration values. 325 326 enum Phy_config_bits : unsigned 327 { 328 Phy_config_powerdown_disable = 0x80, // PHY_CONF0_PDZ_MASK 329 Phy_config_tmds = 0x40, // PHY_CONF0_ENTMDS_MASK 330 Phy_config_svsret = 0x20, // PHY_CONF0_SVSRET_MASK 331 Phy_config_gen2_powerdown = 0x10, // PHY_CONF0_GEN2_PDDQ_MASK 332 Phy_config_gen2_tx_power = 0x08, // PHY_CONF0_GEN2_TXPWRON_MASK 333 Phy_config_gen2_hotplug_detect_rx_sense = 0x04, // PHY_CONF0_GEN2_ENHPDRXSENSE_MASK 334 Phy_config_select_data_enable_polarity = 0x02, // PHY_CONF0_SELDATAENPOL_MASK 335 Phy_config_select_interface_control = 0x01, // PHY_CONF0_SELDIPIF_MASK 336 }; 337 338 enum Phy_test_bits : unsigned 339 { 340 Phy_test0_clear_mask = 0x20, // PHY_TST0_TSTCLR_MASK 341 Phy_test0_enable_mask = 0x10, // PHY_TST0_TSTEN_MASK 342 Phy_test0_clock_mask = 0x01, // PHY_TST0_TSTCLK_MASK 343 }; 344 345 // PHY status and mask values. 346 347 enum Phy_status_bits : unsigned 348 { 349 Phy_status_all = 0xf3, 350 Phy_status_rx_sense_all = 0xf0, 351 Phy_status_rx_sense3 = 0x80, // PHY_RX_SENSE3 352 Phy_status_rx_sense2 = 0x40, // PHY_RX_SENSE2 353 Phy_status_rx_sense1 = 0x20, // PHY_RX_SENSE1 354 Phy_status_rx_sense0 = 0x10, // PHY_RX_SENSE0 355 Phy_status_hotplug_detect = 0x02, // PHY_HPD 356 Phy_status_tx_phy_lock = 0x01, // PHY_TX_PHY_LOCK 357 Phy_status_none = 0, 358 }; 359 360 // PHY interrupt status and mask values. 361 362 enum Phy_int_status_bits : unsigned 363 { 364 Phy_int_status_all = 0x3f, 365 Phy_int_status_rx_sense_all = 0x3c, 366 Phy_int_status_rx_sense3 = 0x20, // IH_PHY_STAT0_RX_SENSE3 367 Phy_int_status_rx_sense2 = 0x10, // IH_PHY_STAT0_RX_SENSE2 368 Phy_int_status_rx_sense1 = 0x08, // IH_PHY_STAT0_RX_SENSE1 369 Phy_int_status_rx_sense0 = 0x04, // IH_PHY_STAT0_RX_SENSE0 370 Phy_int_status_tx_phy_lock = 0x02, // IH_PHY_STAT0_TX_PHY_LOCK 371 Phy_int_status_hotplug_detect = 0x01, // IH_PHY_STAT0_HPD 372 Phy_int_status_none = 0, 373 }; 374 375 // PHY main register values. 376 377 enum Main_heac_phy_reset_bits : unsigned 378 { 379 Main_heac_phy_reset_assert = 0x01, // MC_HEACPHY_RST_ASSERT 380 }; 381 382 enum Main_flow_control_bits : unsigned 383 { 384 Main_flow_control_csc_active = 0x01, // MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH 385 Main_flow_control_csc_inactive = 0x00, // MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS 386 }; 387 388 enum Main_clock_disable_bits : unsigned 389 { 390 Main_clock_disable_hdcp = 0x40, // MC_CLKDIS_HDCPCLK_DISABLE 391 Main_clock_disable_cec = 0x20, // MC_CLKDIS_CECCLK_DISABLE 392 Main_clock_disable_csc = 0x10, // MC_CLKDIS_CSCCLK_DISABLE 393 Main_clock_disable_audio = 0x08, // MC_CLKDIS_AUDCLK_DISABLE 394 Main_clock_disable_prep = 0x04, // MC_CLKDIS_PREPCLK_DISABLE 395 Main_clock_disable_tmds = 0x02, // MC_CLKDIS_TMDSCLK_DISABLE 396 Main_clock_disable_pixel = 0x01, // MC_CLKDIS_PIXELCLK_DISABLE 397 }; 398 399 // Frame composer values. 400 401 enum Fc_video_config_bits : unsigned 402 { 403 Fc_video_config_hdcp_keepout_active = 0x80, // FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE 404 Fc_video_config_hdcp_keepout_inactive = 0x00, // FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE 405 Fc_video_config_vsync_active_high = 0x40, // FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH 406 Fc_video_config_vsync_active_low = 0x00, // FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW 407 Fc_video_config_hsync_active_high = 0x20, // FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH 408 Fc_video_config_hsync_active_low = 0x00, // FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW 409 Fc_video_config_data_enable_active_high = 0x10, // FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH 410 Fc_video_config_data_enable_active_low = 0x00, // FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW 411 Fc_video_config_hdmi_mode = 0x08, // FC_INVIDCONF_DVI_MODEZ_HDMI_MODE 412 Fc_video_config_dvi_mode = 0x00, // FC_INVIDCONF_DVI_MODEZ_DVI_MODE 413 Fc_video_config_osc_active_high = 0x02, // FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH 414 Fc_video_config_osc_active_low = 0x00, // FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW 415 Fc_video_config_interlaced = 0x01, // FC_INVIDCONF_IN_I_P_INTERLACED 416 Fc_video_config_progressive = 0x00, // FC_INVIDCONF_IN_I_P_PROGRESSIVE 417 }; 418 419 enum Fc_int_status2_bits : unsigned 420 { 421 Fc_int_status2_overflow = 0x03, // FC_STAT2_OVERFLOW_MASK 422 Fc_int_status2_overflow_low = 0x02, // FC_STAT2_LOW_PRIORITY_OVERFLOW 423 Fc_int_status2_overflow_high = 0x01 // FC_STAT2_HIGH_PRIORITY_OVERFLOW, 424 }; 425 426 // Colour space conversion values. 427 428 enum Csc_config_bits : unsigned 429 { 430 Csc_config_interpolation_mask = 0x30, // CSC_CFG_INTMODE_MASK 431 Csc_config_interpolation_disable = 0x00, // CSC_CFG_INTMODE_DISABLE 432 Csc_config_interpolation_form1 = 0x10, // CSC_CFG_INTMODE_CHROMA_INT_FORMULA1 433 Csc_config_interpolation_form2 = 0x20, // CSC_CFG_INTMODE_CHROMA_INT_FORMULA2 434 Csc_config_decimation_mask = 0x3, // CSC_CFG_DECMODE_MASK 435 Csc_config_decimation_disable = 0x0, // CSC_CFG_DECMODE_DISABLE 436 Csc_config_decimation_form1 = 0x1, // CSC_CFG_DECMODE_CHROMA_INT_FORMULA1 437 Csc_config_decimation_form2 = 0x2, // CSC_CFG_DECMODE_CHROMA_INT_FORMULA2 438 Csc_config_decimation_form3 = 0x3, // CSC_CFG_DECMODE_CHROMA_INT_FORMULA3 439 }; 440 441 enum Csc_scale_bits : unsigned 442 { 443 Csc_scale_colour_depth_mask = 0xf0, // CSC_SCALE_CSC_COLORDE_PTH_MASK 444 Csc_scale_colour_depth_24bpp = 0x00, // CSC_SCALE_CSC_COLORDE_PTH_24BPP 445 Csc_scale_colour_depth_30bpp = 0x50, // CSC_SCALE_CSC_COLORDE_PTH_30BPP 446 Csc_scale_colour_depth_36bpp = 0x60, // CSC_SCALE_CSC_COLORDE_PTH_36BPP 447 Csc_scale_colour_depth_48bpp = 0x70, // CSC_SCALE_CSC_COLORDE_PTH_48BPP 448 Csc_scale_mask = 0x03, // CSC_SCALE_CSCSCALE_MASK 449 }; 450 451 // HDCP register values. 452 453 enum Hdcp_config0_bits : unsigned 454 { 455 Hdcp_config0_rxdetect_enable = 0x4, // A_HDCPCFG0_RXDETECT_ENABLE 456 }; 457 458 enum Hdcp_config1_bits : unsigned 459 { 460 Hdcp_config1_encryption_disable = 0x2, // A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE 461 }; 462 463 enum Hdcp_video_polarity_bits : unsigned 464 { 465 Hdcp_video_polarity_data_enable_active_high = 0x10, // A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH 466 }; 467 468 // Video sample register values. 469 470 enum Sample_video_config_bits : unsigned 471 { 472 Sample_video_config_data_enable_active = 0x80, // TX_INVID0_INTERNAL_DE_GENERATOR_ENABLE 473 Sample_video_config_mapping_mask = 0x1f, // TX_INVID0_VIDEO_MAPPING_MASK 474 }; 475 476 enum Sample_video_stuffing_bits : unsigned 477 { 478 Sample_video_stuffing_bdb_data = 0x04, // TX_INSTUFFING_BDBDATA_STUFFING_ENABLE 479 Sample_video_stuffing_rcr_data = 0x02, // TX_INSTUFFING_RCRDATA_STUFFING_ENABLE 480 Sample_video_stuffing_gy_data = 0x01, // TX_INSTUFFING_GYDATA_STUFFING_ENABLE 481 }; 482 483 // Video packetizer register values. 484 485 enum Packet_stuffing_bits : unsigned 486 { 487 Packet_stuffing_default_phase = 0x20, // VP_STUFF_IDEFAULT_PHASE_MASK 488 Packet_stuffing_ifix_pp_to_last = 0x10, // VP_STUFF_IFIX_PP_TO_LAST_MASK 489 Packet_stuffing_icx = 0x08, // VP_STUFF_ICX_GOTO_P0_ST_MASK 490 Packet_stuffing_ycc422 = 0x04, // VP_STUFF_YCC422_STUFFING_STUFFING_MODE 491 Packet_stuffing_pp = 0x02, // VP_STUFF_PP_STUFFING_STUFFING_MODE 492 Packet_stuffing_pr = 0x01, // VP_STUFF_PR_STUFFING_STUFFING_MODE 493 }; 494 495 enum Packet_config_bits : unsigned 496 { 497 Packet_config_bypass_enable = 0x40, // VP_CONF_BYPASS_EN_ENABLE 498 Packet_config_pp_enable = 0x20, // VP_CONF_PP_EN_ENABLE 499 Packet_config_pr_enable = 0x10, // VP_CONF_PR_EN_ENABLE 500 Packet_config_ycc422_enable = 0x8, // VP_CONF_YCC422_EN_ENABLE 501 Packet_config_bypass_select_packetizer = 0x4, // VP_CONF_BYPASS_SELECT_VID_PACKETIZER 502 Packet_config_output_selector_mask = 0x3, // VP_CONF_OUTPUT_SELECTOR_MASK 503 Packet_config_output_selector_bypass = 0x3, // VP_CONF_OUTPUT_SELECTOR_BYPASS 504 Packet_config_output_selector_ycc422 = 0x1, // VP_CONF_OUTPUT_SELECTOR_YCC422 505 Packet_config_output_selector_pp = 0x0, // VP_CONF_OUTPUT_SELECTOR_PP 506 }; 507 508 enum Packet_remap_bits : unsigned 509 { 510 Packet_remap_mask = 0x3, // VP_REMAP_MASK 511 Packet_remap_ycc422_24bit = 0x2, // VP_REMAP_YCC422_24bit 512 Packet_remap_ycc422_20bit = 0x1, // VP_REMAP_YCC422_20bit 513 Packet_remap_ycc422_16bit = 0x0, // VP_REMAP_YCC422_16bit 514 }; 515 516 enum Packet_pixel_repeater_bits : unsigned 517 { 518 Packet_pixel_repeater_depth_mask = 0xf0, // VP_PR_CD_COLOR_DEPTH_MASK 519 Packet_pixel_repeater_depth_offset = 4, // VP_PR_CD_COLOR_DEPTH_OFFSET 520 Packet_pixel_repeater_factor_mask = 0x0f, // VP_PR_CD_DESIRED_PR_FACTOR_MASK 521 Packet_pixel_repeater_factor_offset = 0, // VP_PR_CD_DESIRED_PR_FACTOR_OFFSET 522 }; 523 524 525 526 // PHY capabilities. 527 528 static const Phy_capabilities phy_capabilities[] = { 529 // name gen svsret configure 530 {Config2_dwc_hdmi_tx_phy, "DWC_HDMI_TX_PHY", 1, false, false}, 531 {Config2_dwc_mhl_phy_heac, "DWC_MHL_PHY_HEAC", 2, true, true}, 532 {Config2_dwc_mhl_phy, "DWC_MHL_PHY", 2, true, true}, 533 {Config2_dwc_hdmi_3d_tx_phy_heac, "DWC_HDMI_3D_TX_PHY_HEAC", 2, false, true}, 534 {Config2_dwc_hdmi_3d_tx_phy, "DWC_HDMI_3D_TX_PHY", 2, false, true}, 535 {Config2_dwc_hdmi20_tx_phy, "DWC_HDMI20_TX_PHY", 2, true, true}, 536 {0, "Vendor PHY", 0, false, false}, 537 }; 538 539 540 541 // PHY configuration, adopting the Linux driver's tables of values. 542 543 static const struct Phy_mpll_config phy_mpll_config[] = { 544 // 8bpc 10bpc 12bpc 545 // pixelclock cpce gmp cpce gmp cpce gmp 546 { 45250000, { {0x01e0, 0x0000}, {0x21e1, 0x0000}, {0x41e2, 0x0000} } }, 547 { 92500000, { {0x0140, 0x0005}, {0x2141, 0x0005}, {0x4142, 0x0005} } }, 548 { 148500000, { {0x00a0, 0x000a}, {0x20a1, 0x000a}, {0x40a2, 0x000a} } }, 549 { 216000000, { {0x00a0, 0x000a}, {0x2001, 0x000f}, {0x4002, 0x000f} } }, 550 { ~0UL, { {0x0000, 0x0000}, {0x0000, 0x0000}, {0x0000, 0x0000} } } 551 }; 552 553 static const struct Phy_curr_ctrl phy_curr_ctrl[] = { 554 // pixelclock 8bpc 10bpc 12bpc 555 { 54000000, {0x091c, 0x091c, 0x06dc} }, 556 { 58400000, {0x091c, 0x06dc, 0x06dc} }, 557 { 72000000, {0x06dc, 0x06dc, 0x091c} }, 558 { 74250000, {0x06dc, 0x0b5c, 0x091c} }, 559 { 118800000, {0x091c, 0x091c, 0x06dc} }, 560 { 216000000, {0x06dc, 0x0b5c, 0x091c} }, 561 { ~0UL, {0x0000, 0x0000, 0x0000} } 562 }; 563 564 static const struct Phy_config phy_config[] = { 565 // pixelclock symbol term vlevel 566 { 216000000, 0x800d, 0x0005, 0x01ad}, 567 { ~0UL, 0x0000, 0x0000, 0x0000} 568 }; 569 570 571 572 // Initialise the HDMI peripheral. 573 574 Hdmi_jz4780_chip::Hdmi_jz4780_chip(l4_addr_t start, l4_addr_t end, 575 l4_cap_idx_t irq, 576 struct Jz4740_lcd_panel *panel) 577 : _start(start), _end(end), _irq(irq), _panel(panel) 578 { 579 // 8-bit registers with 2-bit address shifting. 580 581 _regs = new Hw::Mmio_register_block<8>(start, 2); 582 583 // Initialise I2C state for DDC. 584 585 _segment_read = false; 586 _device_register = 0; 587 588 // Initialise I2C state for PHY initialisation. 589 590 _phy_device_register = 0; 591 592 // Initialise identifying details and capabilities of the hardware. 593 594 get_identification(); 595 596 // Reset interrupts to a minimal, enabled state. 597 598 irq_init(); 599 600 // Set up DDC and PHY communication. 601 602 i2c_init(I2c_software_reset, I2c_divider, I2c_int_config0, I2c_int_config1, 603 I2c_int_status, I2c_int_mask); 604 i2c_init(I2c_phy_software_reset, I2c_phy_divider, I2c_phy_int_config0, I2c_phy_int_config1, 605 I2c_phy_int_status, I2c_phy_int_mask); 606 607 // Enable PHY interrupts. 608 609 phy_irq_init(); 610 } 611 612 // Pixel clock frequency calculation. 613 614 unsigned long Hdmi_jz4780_chip::get_pixelclock() 615 { 616 return _pixelclock; 617 618 /* Calculated frequency, which may not be the actual pixelclock frequency... 619 620 return (_panel->line_start + _panel->width + _panel->line_end + _panel->hsync) * 621 (_panel->frame_start + _panel->height + _panel->frame_end + _panel->vsync) * 622 _panel->frame_rate; 623 */ 624 } 625 626 627 628 // Update a register by enabling/setting or disabling/clearing the given bits. 629 630 void Hdmi_jz4780_chip::reg_update(uint32_t reg, uint32_t bits, bool enable) 631 { 632 if (enable) 633 _regs[reg] = _regs[reg] | bits; 634 else 635 _regs[reg] = _regs[reg] & ~bits; 636 } 637 638 // Update a field. The bits must be shifted to coincide with the mask. 639 640 void Hdmi_jz4780_chip::reg_update_field(uint32_t reg, uint32_t mask, uint32_t bits) 641 { 642 _regs[reg] = (_regs[reg] & ~(mask)) | (bits & mask); 643 } 644 645 void Hdmi_jz4780_chip::reg_fill_field(uint32_t reg, uint32_t mask) 646 { 647 _regs[reg] = _regs[reg] | mask; 648 } 649 650 651 652 // Chipset querying. 653 654 void Hdmi_jz4780_chip::get_identification() 655 { 656 _version = (_regs[Design_id] << 8) | _regs[Revision_id]; 657 _phy_type = _regs[Config_id2]; 658 659 // Initialise a member to any matching capabilities or leave it as the "null" 660 // entry. 661 662 _phy_def = phy_capabilities; 663 664 while (_phy_def->gen && (_phy_def->type != _phy_type)) 665 _phy_def++; 666 } 667 668 void Hdmi_jz4780_chip::get_version(uint8_t *major, uint16_t *minor) 669 { 670 *major = (_version >> 12) & 0xfff; 671 *minor = _version & 0xfff; 672 } 673 674 void Hdmi_jz4780_chip::get_phy_capabilities(const struct Phy_capabilities **phy_def) 675 { 676 *phy_def = _phy_def; 677 } 678 679 680 681 // Initialisation. 682 683 void Hdmi_jz4780_chip::irq_init() 684 { 685 // Disable interrupts. 686 687 _regs[Int_mask] = _regs[Int_mask] | (Int_mask_wakeup | Int_mask_all); 688 689 // Mask all interrupts. 690 691 _regs[Fc_int_mask0] = 0xff; 692 _regs[Fc_int_mask1] = 0xff; 693 _regs[Fc_int_mask2] = 0xff; 694 _regs[As_int_mask] = 0xff; 695 _regs[Phy_int_mask] = 0xff; 696 _regs[I2c_int_mask] = 0xff; 697 _regs[I2c_phy_int_mask] = 0xff; 698 _regs[Cec_int_mask] = 0xff; 699 _regs[Vp_int_mask] = 0xff; 700 _regs[Ahb_dma_audio_int_mask] = 0xff; 701 702 // Enable interrupts. 703 704 _regs[Int_mask] = _regs[Int_mask] & ~(Int_mask_wakeup | Int_mask_all); 705 } 706 707 void Hdmi_jz4780_chip::phy_irq_init() 708 { 709 // Set PHY interrupt polarities. 710 711 _regs[Phy_polarity] = Phy_status_all; 712 713 // Enable/unmask second-level interrupts. 714 715 _regs[Phy_mask] = _regs[Phy_mask] & ~(Phy_status_all); 716 717 // Clear pending interrupts. 718 719 _regs[Phy_int_status] = Phy_int_status_all; 720 721 // Enable/unmask interrupts. 722 723 _regs[Phy_int_mask] = _regs[Phy_int_mask] & ~(Phy_int_status_all); 724 } 725 726 727 728 // I2C support. 729 730 void Hdmi_jz4780_chip::i2c_init(uint32_t reset, uint32_t divider, 731 uint32_t config0, uint32_t config1, 732 uint32_t status, uint32_t mask) 733 { 734 // Software reset. 735 736 _regs[reset] = 0; 737 738 // Standard mode (100kHz). 739 740 _regs[divider] = 0; 741 742 // Set interrupt polarities. 743 744 _regs[config0] = I2c_int_config0_done_polarity; 745 _regs[config1] = I2c_int_config1_nack_polarity | I2c_int_config1_arb_polarity; 746 747 // Clear and mask/mute interrupts. 748 749 _regs[status] = I2c_int_status_done | I2c_int_status_error; 750 _regs[mask] = I2c_int_status_done | I2c_int_status_error; 751 } 752 753 long Hdmi_jz4780_chip::i2c_wait(uint32_t status) 754 { 755 long err; 756 uint8_t int_status; 757 l4_msgtag_t tag; 758 759 do 760 { 761 tag = l4_irq_receive(_irq, L4_IPC_NEVER); 762 763 err = l4_ipc_error(tag, l4_utcb()); 764 if (err) 765 return err; 766 767 int_status = _regs[status]; 768 769 // Test for an error condition. 770 771 if (int_status & I2c_int_status_error) 772 return -L4_EIO; 773 774 // Acknowledge the interrupt. 775 776 _regs[status] = int_status; 777 778 } while (!(int_status & I2c_int_status_done)); 779 780 return L4_EOK; 781 } 782 783 int Hdmi_jz4780_chip::i2c_read(uint8_t *buf, unsigned int length) 784 { 785 unsigned int i; 786 long err; 787 788 // Unmask interrupts. 789 790 _regs[I2c_int_mask] = 0; 791 792 for (i = 0; i < length; i++) 793 { 794 // Increment the device register. 795 796 _regs[I2c_register] = _device_register++; 797 _regs[I2c_operation] = _segment_read ? I2c_operation_segment_read 798 : I2c_operation_read; 799 800 // Wait and then read. 801 802 err = i2c_wait(I2c_int_status); 803 if (err) 804 break; 805 806 buf[i] = _regs[I2c_data_in]; 807 } 808 809 // Mask interrupts again. 810 811 _regs[I2c_int_mask] = I2c_int_status_done | I2c_int_status_error; 812 813 return i; 814 } 815 816 int Hdmi_jz4780_chip::i2c_phy_write(uint8_t address, uint16_t value) 817 { 818 i2c_phy_set_address(address); 819 return i2c_phy_write(&value, 1); 820 } 821 822 int Hdmi_jz4780_chip::i2c_phy_write(uint16_t *buf, unsigned int length) 823 { 824 unsigned int i; 825 long err; 826 827 // Unmask interrupts. 828 829 _regs[I2c_phy_int_mask] = 0; 830 831 for (i = 0; i < length; i++) 832 { 833 // Increment the device register. 834 835 _regs[I2c_phy_register] = _device_register++; 836 _regs[I2c_phy_operation] = I2c_operation_write; 837 838 // Write and then wait. 839 840 _regs[I2c_phy_data_out1] = (buf[i] >> 8) & 0xff; 841 _regs[I2c_phy_data_out0] = buf[i] & 0xff; 842 843 err = i2c_wait(I2c_phy_int_status); 844 if (err) 845 break; 846 } 847 848 // Mask interrupts again. 849 850 _regs[I2c_phy_int_mask] = I2c_int_status_done | I2c_int_status_error; 851 852 return i; 853 } 854 855 void Hdmi_jz4780_chip::i2c_set_address(uint8_t address) 856 { 857 _regs[I2c_device_address] = address; 858 _segment_read = false; 859 i2c_set_register(0); 860 } 861 862 void Hdmi_jz4780_chip::i2c_phy_set_address(uint8_t address) 863 { 864 // The Linux drivers seem to set the clear field when changing the PHY device 865 // address, presumably because some manual says so. 866 867 _regs[Phy_test0] = _regs[Phy_test0] | Phy_test0_clear_mask; 868 _regs[I2c_phy_device_address] = address; 869 _regs[Phy_test0] = _regs[Phy_test0] & ~Phy_test0_clear_mask; 870 871 i2c_phy_set_register(0); 872 } 873 874 void Hdmi_jz4780_chip::i2c_set_segment(uint8_t segment) 875 { 876 _regs[I2c_segment_address] = 0x30; 877 _regs[I2c_segment_pointer] = segment; 878 _segment_read = true; 879 i2c_set_register(0); 880 } 881 882 void Hdmi_jz4780_chip::i2c_set_register(uint8_t device_register) 883 { 884 _device_register = device_register; 885 } 886 887 void Hdmi_jz4780_chip::i2c_phy_set_register(uint8_t device_register) 888 { 889 _phy_device_register = device_register; 890 } 891 892 893 894 // PHY operations. 895 896 void Hdmi_jz4780_chip::phy_enable_powerdown(bool enable) 897 { 898 reg_update(Phy_config, Phy_config_powerdown_disable, !enable); 899 } 900 901 void Hdmi_jz4780_chip::phy_enable_tmds(bool enable) 902 { 903 reg_update(Phy_config, Phy_config_tmds, enable); 904 } 905 906 void Hdmi_jz4780_chip::phy_enable_svsret(bool enable) 907 { 908 reg_update(Phy_config, Phy_config_svsret, enable); 909 } 910 911 void Hdmi_jz4780_chip::phy_enable_gen2_powerdown(bool enable) 912 { 913 reg_update(Phy_config, Phy_config_gen2_powerdown, enable); 914 } 915 916 void Hdmi_jz4780_chip::phy_enable_gen2_tx_power(bool enable) 917 { 918 reg_update(Phy_config, Phy_config_gen2_tx_power, enable); 919 } 920 921 void Hdmi_jz4780_chip::phy_enable_interface(bool enable) 922 { 923 reg_update(Phy_config, Phy_config_select_data_enable_polarity, enable); 924 reg_update(Phy_config, Phy_config_select_interface_control, !enable); 925 } 926 927 // Configure the PHY. Various things not supported by the JZ4780 PHY are ignored 928 // such as the TDMS clock ratio (dependent on HDMI 2 and content scrambling). 929 930 long Hdmi_jz4780_chip::phy_configure() 931 { 932 long err; 933 934 phy_power_off(); 935 936 if (_phy_def->svsret) 937 phy_enable_svsret(true); 938 939 phy_reset(); 940 941 _regs[Main_heac_phy_reset] = Main_heac_phy_reset_assert; 942 943 i2c_phy_set_address(I2c_phy_device_phy_gen2); 944 945 if (_phy_def->configure) 946 { 947 err = phy_configure_specific(); 948 if (err) 949 return err; 950 } 951 952 // NOTE: TMDS clock delay here in Linux driver. 953 954 phy_power_on(); 955 956 return L4_EOK; 957 } 958 959 // Configure for the JZ4780 specifically. 960 961 long Hdmi_jz4780_chip::phy_configure_specific() 962 { 963 const struct Phy_mpll_config *m = phy_mpll_config; 964 const struct Phy_curr_ctrl *c = phy_curr_ctrl; 965 const struct Phy_config *p = phy_config; 966 unsigned long pixelclock = get_pixelclock(); 967 968 // Find MPLL, CURR_CTRL and PHY configuration settings appropriate for the 969 // pixel clock frequency. 970 971 while (m->pixelclock && (pixelclock > m->pixelclock)) 972 m++; 973 974 while (c->pixelclock && (pixelclock > c->pixelclock)) 975 c++; 976 977 while (p->pixelclock && (pixelclock > p->pixelclock)) 978 p++; 979 980 printf("MPLL for %ld; CURR_CTRL for %ld; PHY for %ld\n", m->pixelclock, c->pixelclock, p->pixelclock); 981 982 if (!m->pixelclock || !c->pixelclock || !p->pixelclock) 983 return -L4_EINVAL; 984 985 // Using values for 8bpc from the tables. 986 987 // Initialise MPLL. 988 989 i2c_phy_write(I2c_phy_3d_tx_cpce_ctrl, m->res[Phy_resolution_8bpc].cpce); 990 i2c_phy_write(I2c_phy_3d_tx_gmp_ctrl, m->res[Phy_resolution_8bpc].gmp); 991 992 // Initialise CURRCTRL. 993 994 i2c_phy_write(I2c_phy_3d_tx_cpce_ctrl, c->curr[Phy_resolution_8bpc]); 995 996 // Initialise PHY_CONFIG. 997 998 i2c_phy_write(I2c_phy_3d_tx_pll_phby_ctrl, 0); 999 i2c_phy_write(I2c_phy_3d_tx_msm_ctrl, Msm_ctrl_clock_output_select_fb); 1000 1001 i2c_phy_write(I2c_phy_3d_tx_term, p->term); 1002 i2c_phy_write(I2c_phy_3d_tx_clock_symbol_ctrl, p->symbol); 1003 i2c_phy_write(I2c_phy_3d_tx_vlevel_ctrl, p->vlevel); 1004 1005 // Override and disable clock termination. 1006 1007 i2c_phy_write(I2c_phy_3d_tx_clock_cal_ctrl, Clock_cal_ctrl_override); 1008 1009 return L4_EOK; 1010 } 1011 1012 long Hdmi_jz4780_chip::phy_init() 1013 { 1014 printf("phy_init...\n"); 1015 1016 long err; 1017 int i; 1018 1019 // Initialisation repeated for HDMI PHY specification reasons. 1020 1021 for (i = 0; i < 2; i++) 1022 { 1023 phy_enable_interface(true); 1024 err = phy_configure(); 1025 if (err) 1026 return err; 1027 } 1028 1029 return L4_EOK; 1030 } 1031 1032 void Hdmi_jz4780_chip::phy_reset() 1033 { 1034 _regs[Main_reset] = 1; 1035 _regs[Main_reset] = 0; 1036 } 1037 1038 void Hdmi_jz4780_chip::phy_power_off() 1039 { 1040 printf("phy_power_off...\n"); 1041 1042 if (_phy_def && (_phy_def->gen == 1)) 1043 { 1044 phy_enable_tmds(false); 1045 phy_enable_powerdown(true); 1046 return; 1047 } 1048 1049 phy_enable_gen2_tx_power(false); 1050 1051 wait_for_tx_phy_lock(0); 1052 1053 phy_enable_gen2_powerdown(true); 1054 } 1055 1056 void Hdmi_jz4780_chip::phy_power_on() 1057 { 1058 printf("phy_power_on...\n"); 1059 1060 if (_phy_def && (_phy_def->gen == 1)) 1061 { 1062 phy_enable_powerdown(false); 1063 phy_enable_tmds(false); 1064 phy_enable_tmds(true); 1065 return; 1066 } 1067 1068 phy_enable_gen2_tx_power(true); 1069 phy_enable_gen2_powerdown(false); 1070 1071 wait_for_tx_phy_lock(1); 1072 } 1073 1074 1075 1076 // Hotplug detection. 1077 1078 bool Hdmi_jz4780_chip::connected() 1079 { 1080 return (_regs[Phy_status] & Phy_status_hotplug_detect) != 0; 1081 } 1082 1083 long Hdmi_jz4780_chip::wait_for_connection() 1084 { 1085 return wait_for_phy_irq(Phy_int_status_hotplug_detect, Phy_status_hotplug_detect, 1086 Phy_status_hotplug_detect); 1087 } 1088 1089 // General PHY interrupt handling. 1090 1091 long Hdmi_jz4780_chip::wait_for_phy_irq(uint32_t int_status_flags, 1092 uint32_t status_flags, 1093 uint32_t status_values) 1094 { 1095 long err; 1096 uint8_t int_status, status; 1097 uint8_t status_unchanged = ~(status_values) & status_flags; 1098 l4_msgtag_t tag; 1099 1100 do 1101 { 1102 tag = l4_irq_receive(_irq, L4_IPC_NEVER); 1103 1104 err = l4_ipc_error(tag, l4_utcb()); 1105 if (err) 1106 return err; 1107 1108 // Obtain the details. 1109 1110 int_status = _regs[Phy_int_status]; 1111 status = _regs[Phy_status]; 1112 1113 // Acknowledge the interrupt. 1114 1115 _regs[Phy_int_status] = int_status_flags; 1116 1117 // Continue without a handled event. 1118 // An event is handled when detected and when the status differs from 1119 // the unchanged state. 1120 1121 printf("Status: %x versus %x\n", status & status_flags, status_unchanged); 1122 1123 } while (!((int_status & int_status_flags) && 1124 ((status & status_flags) ^ status_unchanged))); 1125 1126 return L4_EOK; 1127 } 1128 1129 // Wait for TX_PHY_LOCK to become high or low. 1130 1131 long Hdmi_jz4780_chip::wait_for_tx_phy_lock(int level) 1132 { 1133 if (!!(_regs[Phy_status] & Phy_status_tx_phy_lock) == level) 1134 return L4_EOK; 1135 1136 return wait_for_phy_irq(Phy_int_status_tx_phy_lock, Phy_status_tx_phy_lock, 1137 level ? Phy_status_tx_phy_lock : Phy_status_none); 1138 } 1139 1140 1141 1142 // Output setup operations. 1143 1144 long Hdmi_jz4780_chip::enable(unsigned long pixelclock) 1145 { 1146 _pixelclock = pixelclock; 1147 1148 // Disable frame composer overflow interrupts. 1149 1150 enable_overflow_irq(false); 1151 1152 // NOTE: Here, CEA modes are normally detected and thus the output encoding. 1153 // NOTE: Instead, a fixed RGB output encoding and format is used. 1154 // NOTE: Meanwhile, the input encoding and format will also be fixed to a RGB 1155 // NOTE: representation. 1156 1157 // _bits_per_channel = 8; 1158 // _data_enable_polarity = true; 1159 1160 // HDMI initialisation "step B.1": video frame initialisation. 1161 1162 frame_init(); 1163 1164 // HDMI initialisation "step B.2": PHY initialisation. 1165 1166 long err = phy_init(); 1167 if (err) 1168 return err; 1169 1170 // HDMI initialisation "step B.3": video signal initialisation. 1171 1172 data_path_init(); 1173 1174 // With audio, various clock updates are needed. 1175 1176 // NOTE: DVI mode is being assumed for now, for simplicity. 1177 1178 // In non-DVI mode, the AVI, vendor-specific infoframe and regular infoframe 1179 // are set up. 1180 1181 packet_init(); 1182 csc_init(); 1183 sample_init(); 1184 hdcp_init(); 1185 1186 // Enable frame composer overflow interrupts. 1187 1188 enable_overflow_irq(true); 1189 1190 return L4_EOK; 1191 } 1192 1193 void Hdmi_jz4780_chip::enable_overflow_irq(bool enable) 1194 { 1195 reg_update(Fc_int_mask2, Fc_int_status2_overflow, !enable); 1196 } 1197 1198 void Hdmi_jz4780_chip::frame_init() 1199 { 1200 printf("frame_init...\n"); 1201 1202 // Initialise the video configuration. This is rather like the initialisation 1203 // of the LCD controller. The sync and data enable polarities are set up, plus 1204 // extras like HDCP, DVI mode, progressive/interlace. 1205 // NOTE: Here, the JZ4740-specific configuration is used to store the picture 1206 // NOTE: properties, but a neutral structure should be adopted. 1207 1208 uint8_t config = 0; 1209 1210 config |= (_panel->config & Jz4740_lcd_hsync_negative) 1211 ? Fc_video_config_hsync_active_low 1212 : Fc_video_config_hsync_active_high; 1213 1214 config |= (_panel->config & Jz4740_lcd_vsync_negative) 1215 ? Fc_video_config_vsync_active_low 1216 : Fc_video_config_vsync_active_high; 1217 1218 config |= (_panel->config & Jz4740_lcd_de_negative) 1219 ? Fc_video_config_data_enable_active_low 1220 : Fc_video_config_data_enable_active_high; 1221 1222 // NOTE: Only supporting DVI mode so far. 1223 1224 config |= Fc_video_config_dvi_mode; 1225 1226 // NOTE: Not supporting HDCP. 1227 1228 config |= Fc_video_config_hdcp_keepout_inactive; 1229 1230 // NOTE: Only supporting progressive scan so far. 1231 1232 config |= Fc_video_config_progressive; 1233 config |= Fc_video_config_osc_active_low; 1234 1235 _regs[Fc_video_config] = config; 1236 1237 printf("Fc_video_config (%x) = %x\n", Fc_video_config, (uint8_t) _regs[Fc_video_config]); 1238 1239 // Then, the frame characteristics (visible area, sync pulse) are set. Indeed, 1240 // the frame area details should be practically the same as those used by the 1241 // LCD controller. 1242 1243 uint16_t hblank = _panel->line_start + _panel->line_end + _panel->hsync, 1244 vblank = _panel->frame_start + _panel->frame_end + _panel->vsync, 1245 hsync_delay = _panel->line_end, 1246 vsync_delay = _panel->frame_end, 1247 hsync_width = _panel->hsync, 1248 vsync_height = _panel->vsync; 1249 1250 _regs[Fc_horizontal_active_width1] = (_panel->width >> 8) & 0xff; 1251 _regs[Fc_horizontal_active_width0] = _panel->width & 0xff; 1252 1253 _regs[Fc_horizontal_blank_width1] = (hblank >> 8) & 0xff; 1254 _regs[Fc_horizontal_blank_width0] = hblank & 0xff; 1255 1256 _regs[Fc_vertical_active_height1] = (_panel->height >> 8) & 0xff; 1257 _regs[Fc_vertical_active_height0] = _panel->height & 0xff; 1258 1259 _regs[Fc_vertical_blank_height] = vblank & 0xff; 1260 1261 _regs[Fc_hsync_delay1] = (hsync_delay >> 8) & 0xff; 1262 _regs[Fc_hsync_delay0] = hsync_delay & 0xff; 1263 1264 _regs[Fc_vsync_delay] = vsync_delay & 0xff; 1265 1266 _regs[Fc_hsync_width1] = (hsync_width >> 8) & 0xff; 1267 _regs[Fc_hsync_width0] = hsync_width & 0xff; 1268 1269 _regs[Fc_vsync_height] = vsync_height & 0xff; 1270 } 1271 1272 void Hdmi_jz4780_chip::data_path_init() 1273 { 1274 printf("data_path_init...\n"); 1275 1276 // Initialise the path of the video data. Here, the elements of the data 1277 // stream are defined such as the control period duration, data channel 1278 // characteristics, pixel and TMDS clocks, and the involvement of colour space 1279 // conversion. 1280 1281 // Control period minimum duration. 1282 1283 _regs[Fc_control_duration] = 12; 1284 _regs[Fc_ex_control_duration] = 32; 1285 _regs[Fc_ex_control_space] = 1; 1286 1287 // Set to fill TMDS data channels. 1288 1289 _regs[Fc_channel0_preamble] = 0x0b; 1290 _regs[Fc_channel1_preamble] = 0x16; 1291 _regs[Fc_channel2_preamble] = 0x21; 1292 1293 // Apparent two-stage clock activation. 1294 1295 uint8_t clock_disable = Main_clock_disable_hdcp | 1296 Main_clock_disable_csc | 1297 Main_clock_disable_audio | 1298 Main_clock_disable_prep | 1299 Main_clock_disable_tmds; 1300 1301 // Activate the pixel clock. 1302 1303 _regs[Main_clock_disable] = clock_disable; 1304 1305 // Then activate the TMDS clock. 1306 1307 clock_disable &= ~(Main_clock_disable_tmds); 1308 _regs[Main_clock_disable] = clock_disable; 1309 1310 // NOTE: Bypass colour space conversion for now. 1311 1312 _regs[Main_flow_control] = Main_flow_control_csc_inactive; 1313 } 1314 1315 void Hdmi_jz4780_chip::packet_init() 1316 { 1317 printf("packet_init...\n"); 1318 1319 // Initialise the video packet details. 1320 // NOTE: With 24bpp RGB output only for now, no pixel repetition. 1321 1322 int colour_depth = 4; 1323 1324 _regs[Packet_pixel_repeater] = 1325 ((colour_depth << Packet_pixel_repeater_depth_offset) & 1326 Packet_pixel_repeater_depth_mask); 1327 1328 _regs[Packet_remap] = Packet_remap_ycc422_16bit; 1329 1330 reg_fill_field(Packet_stuffing, Packet_stuffing_pr | 1331 Packet_stuffing_default_phase | 1332 Packet_stuffing_pp | 1333 Packet_stuffing_ycc422); 1334 1335 // Disable pixel repeater. 1336 1337 reg_update_field(Packet_config, Packet_config_pr_enable | 1338 Packet_config_bypass_select_packetizer | 1339 Packet_config_bypass_enable | 1340 Packet_config_pp_enable | 1341 Packet_config_ycc422_enable | 1342 Packet_config_output_selector_mask, 1343 Packet_config_bypass_select_packetizer | 1344 Packet_config_bypass_enable | 1345 Packet_config_output_selector_bypass); 1346 } 1347 1348 void Hdmi_jz4780_chip::csc_init() 1349 { 1350 printf("csc_init...\n"); 1351 1352 // Initialise the colour space conversion details. 1353 // NOTE: No conversion will be done yet (see data_path_init). 1354 1355 _regs[Csc_config] = Csc_config_interpolation_disable | 1356 Csc_config_decimation_disable; 1357 1358 // NOTE: Use 8bpc (24bpp) for now. 1359 1360 reg_update_field(Csc_scale, Csc_scale_colour_depth_mask, Csc_scale_colour_depth_24bpp); 1361 1362 // NOTE: Coefficients should be set here. 1363 } 1364 1365 void Hdmi_jz4780_chip::sample_init() 1366 { 1367 printf("sample_init...\n"); 1368 1369 // Initialise the mapping of video input data. 1370 // NOTE: With 24bpp RGB input only for now. 1371 1372 int colour_format = 0x01; 1373 1374 // Data enable inactive. 1375 1376 _regs[Sample_video_config] = (colour_format & Sample_video_config_mapping_mask); 1377 1378 // Transmission stuffing when data enable is inactive. 1379 1380 _regs[Sample_video_stuffing] = Sample_video_stuffing_bdb_data | 1381 Sample_video_stuffing_rcr_data | 1382 Sample_video_stuffing_gy_data; 1383 1384 _regs[Sample_gy_data0] = 0; 1385 _regs[Sample_gy_data1] = 0; 1386 _regs[Sample_rcr_data0] = 0; 1387 _regs[Sample_rcr_data1] = 0; 1388 _regs[Sample_bcb_data0] = 0; 1389 _regs[Sample_bcb_data1] = 0; 1390 } 1391 1392 void Hdmi_jz4780_chip::hdcp_init() 1393 { 1394 printf("hdcp_init...\n"); 1395 1396 // Initialise HDCP registers, mostly turning things off. 1397 1398 reg_update(Hdcp_config0, Hdcp_config0_rxdetect_enable, false); 1399 1400 reg_update(Hdcp_video_polarity, 1401 Hdcp_video_polarity_data_enable_active_high, 1402 !(_panel->config & Jz4740_lcd_de_negative)); 1403 1404 reg_update(Hdcp_config1, Hdcp_config1_encryption_disable, true); 1405 } 1406 1407 1408 1409 // C language interface functions. 1410 1411 void *jz4780_hdmi_init(l4_addr_t start, l4_addr_t end, l4_cap_idx_t irq, 1412 struct Jz4740_lcd_panel *panel) 1413 { 1414 return (void *) new Hdmi_jz4780_chip(start, end, irq, panel); 1415 } 1416 1417 void jz4780_hdmi_get_version(void *hdmi, uint8_t *major, uint16_t *minor) 1418 { 1419 static_cast<Hdmi_jz4780_chip *>(hdmi)->get_version(major, minor); 1420 } 1421 1422 void jz4780_hdmi_get_phy_capabilities(void *hdmi, const struct Phy_capabilities **phy_def) 1423 { 1424 static_cast<Hdmi_jz4780_chip *>(hdmi)->get_phy_capabilities(phy_def); 1425 } 1426 1427 int jz4780_hdmi_i2c_read(void *hdmi, uint8_t *buf, unsigned int length) 1428 { 1429 return static_cast<Hdmi_jz4780_chip *>(hdmi)->i2c_read(buf, length); 1430 } 1431 1432 void jz4780_hdmi_i2c_set_address(void *hdmi, uint8_t address) 1433 { 1434 static_cast<Hdmi_jz4780_chip *>(hdmi)->i2c_set_address(address); 1435 } 1436 1437 void jz4780_hdmi_i2c_set_segment(void *hdmi, uint8_t segment) 1438 { 1439 static_cast<Hdmi_jz4780_chip *>(hdmi)->i2c_set_segment(segment); 1440 } 1441 1442 void jz4780_hdmi_i2c_set_register(void *hdmi, uint8_t device_register) 1443 { 1444 static_cast<Hdmi_jz4780_chip *>(hdmi)->i2c_set_register(device_register); 1445 } 1446 1447 int jz4780_hdmi_connected(void *hdmi) 1448 { 1449 return (int) static_cast<Hdmi_jz4780_chip *>(hdmi)->connected(); 1450 } 1451 1452 long jz4780_hdmi_wait_for_connection(void *hdmi) 1453 { 1454 return static_cast<Hdmi_jz4780_chip *>(hdmi)->wait_for_connection(); 1455 } 1456 1457 long jz4780_hdmi_enable(void *hdmi, unsigned long pixelclock) 1458 { 1459 return static_cast<Hdmi_jz4780_chip *>(hdmi)->enable(pixelclock); 1460 }