1 /* 2 * MSC (MMC/SD controller) peripheral support. 3 * 4 * Copyright (C) 2024 Paul Boddie <paul@boddie.org.uk> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 19 * Boston, MA 02110-1301, USA 20 */ 21 22 #include <l4/devices/hw_mmio_register_block.h> 23 #include <l4/sys/irq.h> 24 #include <l4/util/util.h> 25 26 #include <stdio.h> 27 28 #include "msc-common.h" 29 30 31 32 // Register locations for each channel. 33 34 enum Regs : unsigned 35 { 36 Msc_control = 0x000, // MSC_CTRL 37 Msc_status = 0x004, // MSC_STAT 38 Msc_clock_rate = 0x008, // MSC_CLKRT 39 Msc_command_data_control = 0x00c, // MSC_CMDAT 40 Msc_response_timeout = 0x010, // MSC_RESTO 41 Msc_read_timeout = 0x014, // MSC_RDTO 42 Msc_block_length = 0x018, // MSC_BLKLEN 43 Msc_block_count = 0x01c, // MSC_NOB 44 Msc_block_success_count = 0x020, // MSC_SNOB 45 Msc_interrupt_mask = 0x024, // MSC_IMASK 46 Msc_interrupt_flag = 0x028, // MSC_IFLG/MSC_IREG 47 Msc_command_index = 0x02c, // MSC_CMD 48 Msc_command_argument = 0x030, // MSC_ARG 49 Msc_response_fifo = 0x034, // MSC_RES 50 Msc_recv_data_fifo = 0x038, // MSC_RXFIFO 51 Msc_trans_data_fifo = 0x03c, // MSC_TXFIFO 52 53 // JZ4780/X1600 only. 54 55 Msc_low_power_mode = 0x040, // MSC_LPM 56 Msc_dma_control = 0x044, // MSC_DMAC 57 Msc_dma_descriptor_address = 0x048, // MSC_DMANDA 58 Msc_dma_data_address = 0x04c, // MSC_DMADA 59 Msc_dma_data_length = 0x050, // MSC_DMALEN 60 Msc_dma_command = 0x054, // MSC_DMACMD 61 Msc_control2 = 0x058, // MSC_CTRL2 62 Msc_rtfifo_data_counter = 0x05c, // MSC_RTCNT 63 64 // Channel block size/offset. 65 66 Msc_channel_offset = 0x10000, 67 }; 68 69 // Field definitions. 70 71 enum Control_bits : unsigned 72 { 73 // JZ4780/X1600 only. 74 75 Control_send_ccsd = 0x8000, // SEND_CCSD 76 Control_send_ccsd_automatically = 0x4000, // SEND_CCSD 77 78 // Common. 79 80 Control_exit_multiple = 0x0080, // EXIT_MULTIPLE 81 Control_exit_transfer = 0x0040, // EXIT_TRANSFER 82 Control_start_read_wait = 0x0020, // START_READ_WAIT 83 Control_stop_read_wait = 0x0010, // STOP_READ_WAIT 84 Control_reset = 0x0008, // RESET 85 Control_start_operation = 0x0004, // START_OP 86 87 Control_clock_control_field_mask = 0x3, // CLOCK_CTRL 88 Control_clock_control_start = 2, 89 Control_clock_control_stop = 1, 90 Control_clock_control_field_shift = 0, 91 }; 92 93 enum Control2_bits : unsigned 94 { 95 // JZ4780/X1600 only. 96 97 Control2_pin_level_polarity_field_mask = 0x1f, // PIP 98 Control2_pin_level_polarity_field_shift = 24, 99 100 // JZ4780 only. 101 102 Control2_reset_enable = 0x00800000, // RST_EN 103 104 // JZ4780/X1600 only. 105 106 Control2_stop_read_operation_mode = 0x00000010, // STPRM 107 108 // JZ4780 only. 109 110 Control2_signal_voltage_change = 0x00000008, // SVC 111 112 // JZ4780/X1600 only. 113 114 Control2_speed_mode_field_mask = 0x7, // SMS 115 Control2_speed_mode_default = 0, // = 0 116 Control2_speed_mode_high = 1, // = 1 117 Control2_speed_mode_sdr12 = 2, // = 2 118 Control2_speed_mode_sdr25 = 3, // = 3 119 Control2_speed_mode_sdr50 = 4, // = 4 120 Control2_speed_mode_field_shift = 0, 121 }; 122 123 enum Status_bits : unsigned 124 { 125 // JZ4780/X1600 only. 126 127 Status_auto_cmd12_done = 0x80000000, // AUTO_CMD12_DONE 128 129 // JZ4780 only. 130 131 Status_auto_cmd23_done = 0x40000000, // AUTO_CMD23_DONE 132 Status_signal_voltage_change = 0x20000000, // SVS 133 134 // JZ4780/X1600 only. 135 136 Status_pin_level_field_mask = 0x1f, // PIN_LEVEL 137 Status_pin_level_field_shift = 24, 138 139 Status_boot_crc_error = 0x00100000, // BCE 140 Status_boot_data_end = 0x00080000, // BDE 141 Status_boot_ack_error = 0x00040000, // BAE 142 Status_boot_ack_received = 0x00020000, // BAR 143 Status_dma_end = 0x00010000, // DMAEND 144 145 // Common. 146 147 Status_resetting = 0x8000, // IS_RESETTING 148 Status_sdio_interrupt_active = 0x4000, // SDIO_INT_ACTIVE 149 Status_programming_done = 0x2000, // PRG_DONE 150 Status_data_transfer_done = 0x1000, // DATA_TRAN_DONE 151 Status_end_command_response = 0x0800, // END_CMD_RES 152 Status_data_fifo_almost_full = 0x0400, // DATA_FIFO_AFULL 153 Status_read_wait = 0x0200, // IS_READWAIT 154 Status_clock_enabled = 0x0100, // CLK_EN 155 Status_data_fifo_full = 0x0080, // DATA_FIFO_FULL 156 Status_data_fifo_empty = 0x0040, // DATA_FIFO_EMPTY 157 Status_response_crc_error = 0x0020, // CRC_RES_ERR 158 Status_read_crc_error = 0x0010, // CRC_READ_ERROR 159 Status_write_crc_error_no_status = 0x0008, // CRC_WRITE_ERROR (2) 160 Status_write_crc_error_data = 0x0004, // CRC_WRITE_ERROR (1) 161 Status_timeout_response = 0x0002, // TIME_OUT_RES 162 Status_timeout_read = 0x0001, // TIME_OUT_READ 163 }; 164 165 enum Clock_rate_bits : unsigned 166 { 167 Clock_rate_field_mask = 0x7, // CLK_RATE 168 Clock_rate_field_shift = 0, 169 }; 170 171 enum Command_data_control_bits : unsigned 172 { 173 // JZ4780/X1600 only. 174 175 Cdc_ccs_expected = 0x80000000, // CCS_EXPECTED 176 Cdc_read_ce_ata = 0x40000000, // READ_CEATA 177 Cdc_disable_boot = 0x08000000, // DIS_BOOT 178 Cdc_expect_boot_ack = 0x02000000, // EXP_BOOT_ACK 179 Cdc_alternative_boot_mode = 0x01000000, // BOOT_MODE 180 181 // JZ4780 only. 182 183 Cdc_auto_cmd23 = 0x00040000, // AUTO_CMD23 184 185 // JZ4780/X1600 only. 186 187 Cdc_sdio_interrupt_2cycle = 0x00020000, // SDIO_PRDT 188 Cdc_auto_cmd12 = 0x00010000, // AUTO_CMD12 189 190 Cdc_recv_fifo_level_field_mask = 0x3, // RTRG 191 Cdc_fifo_level_16 = 0, 192 Cdc_fifo_level_32 = 1, 193 Cdc_fifo_level_64 = 2, 194 Cdc_fifo_level_96 = 3, 195 Cdc_recv_fifo_level_field_shift = 14, 196 197 Cdc_trans_fifo_level_field_mask = 0x3, // TTRG 198 Cdc_trans_fifo_level_field_shift = 12, 199 200 // Common. 201 202 Cdc_io_abort = 0x0800, // IO_ABORT 203 204 Cdc_bus_width_field_mask = 0x3, // BUS_WIDTH 205 Cdc_bus_width_field_1bit = 0, // = 0 206 Cdc_bus_width_field_4bit = 2, // = 2 207 Cdc_bus_width_field_shift = 9, 208 209 // JZ4740 only. 210 211 Cdc_dma_enable = 0x0100, // DMA_EN 212 Cdc_dma_disable = 0x0000, 213 214 // Common. 215 216 Cdc_init_sequence = 0x0080, // INIT 217 218 Cdc_expect_busy = 0x0040, // BUSY 219 Cdc_do_not_expect_busy = 0x0000, 220 221 Cdc_stream_block = 0x0020, // STREAM_BLOCK 222 Cdc_not_stream_block = 0x0000, 223 224 Cdc_write_operation = 0x0010, // WRITE_READ 225 Cdc_read_operation = 0x0000, 226 227 Cdc_data_with_command = 0x0008, // DATA_EN 228 Cdc_no_data_with_command = 0x0000, 229 230 Cdc_response_format_field_mask = 0x7, // RESPONSE_FORMAT 231 Cdc_response_format_field_shift = 0, 232 }; 233 234 enum Response_timeout_bits : unsigned 235 { 236 // NOTE: 16-bit value in the JZ4780. 237 // NOTE: 32-bit value in the X1600. 238 239 Response_timeout_mask = 0x000000ff, // RES_TO 240 }; 241 242 enum Read_timeout_bits : unsigned 243 { 244 // NOTE: 16-bit value prior to the JZ4780/X1600. 245 246 Read_timeout_mask = 0xffffffff, // READ_TO 247 }; 248 249 enum Block_length_bits : unsigned 250 { 251 // NOTE: 16-bit value in the JZ4780/X1600. 252 253 Block_length_mask = 0x00000fff, // BLK_LEN 254 }; 255 256 enum Block_count_bits : unsigned 257 { 258 Block_count_mask = 0x0000ffff, // NOB/SNOB 259 }; 260 261 // Interrupt mask/flag bits. 262 263 enum Interrupt_bits : unsigned 264 { 265 // X1600 only. 266 267 Int_dma_data_done = 0x80000000, // DMA_DATA_DONE 268 269 // JZ4780 only. 270 271 Int_auto_cmd23_done = 0x40000000, // AUTO_CMD23_DONE 272 Int_signal_voltage_change = 0x20000000, // SVS 273 274 // JZ4780/X1600 only. 275 276 Int_pin_level_field_mask = 0x1f, // PIN_LEVEL 277 Int_pin_level_field_shift = 24, 278 279 // X1600 only. 280 281 Int_write_request_all_done = 0x00800000, // WR_ALL_DONE 282 283 // JZ4780/X1600 only. 284 285 Int_boot_crc_error = 0x00100000, // BCE 286 Int_boot_data_end = 0x00080000, // BDE 287 Int_boot_ack_error = 0x00040000, // BAE 288 Int_boot_ack_received = 0x00020000, // BAR 289 Int_dma_end = 0x00010000, // DMAEND 290 Int_auto_cmd12_done = 0x00008000, // AUTO_CMD12_DONE 291 Int_data_fifo_full = 0x00004000, // DATA_FIFO_FULL 292 Int_data_fifo_empty = 0x00002000, // DATA_FIFO_EMP 293 Int_crc_response_error = 0x00001000, // CRC_RES_ERR 294 Int_crc_read_error = 0x00000800, // CRC_READ_ERR 295 Int_crc_write_error = 0x00000400, // CRC_WRITE_ERR 296 Int_response_timeout = 0x00000200, // TIME_OUT_RES 297 Int_read_timeout = 0x00000100, // TIME_OUT_READ 298 299 // Common. 300 301 Int_sdio = 0x80, // SDIO 302 Int_trans_fifo_write_request = 0x40, // TXFIFO_WR_REQ 303 Int_recv_fifo_read_request = 0x20, // RXFIFO_RD_REQ 304 Int_end_command_response = 0x04, // END_CMD_RES 305 Int_programming_done = 0x02, // PRG_DONE 306 Int_data_transfer_done = 0x01, // DATA_TRAN_DONE 307 }; 308 309 enum Command_index_bits : unsigned 310 { 311 Command_index_mask = 0x0000003f, // CMD_INDEX 312 }; 313 314 enum Command_argument_bits : unsigned 315 { 316 Command_argument_mask = 0xffffffff, // ARG 317 }; 318 319 enum Response_fifo_bits : unsigned 320 { 321 Response_fifo_mask = 0x0000ffff, // DATA 322 }; 323 324 enum Recv_data_fifo_bits : unsigned 325 { 326 Recv_data_fifo_mask = 0xffffffff, // DATA 327 }; 328 329 enum Trans_data_fifo_bits : unsigned 330 { 331 Trans_data_fifo_mask = 0xffffffff, // DATA 332 }; 333 334 enum Low_power_mode_bits : unsigned 335 { 336 Low_power_mode_enable = 0x00000001, // LPM 337 }; 338 339 enum Dma_control_bits : unsigned 340 { 341 Dma_mode_specify_transfer_length = 0x80, // MODE_SEL 342 343 Dma_address_offset_field_mask = 0x3, // AOFST 344 Dma_address_offset_field_shift = 5, 345 346 Dma_align_enable = 0x10, // ALIGNEN 347 348 Dma_burst_type_field_mask = 0x3, // INCR 349 Dma_burst_type_incr16 = 0, 350 Dma_burst_type_incr32 = 1, 351 Dma_burst_type_incr64 = 2, 352 Dma_burst_type_field_shift = 2, 353 354 Dma_select_common_dma = 0x02, // DMASEL 355 Dma_select_special_dma = 0x00, 356 357 Dma_enable = 0x01, // DMAEN 358 Dma_disable = 0x00, 359 }; 360 361 362 363 // Command indexes. 364 365 enum Command_index : unsigned 366 { 367 Command_go_idle_state = 0, 368 Command_send_op_cond = 1, 369 Command_all_send_cid = 2, 370 Command_send_relative_addr = 3, // SD 371 Command_set_relative_addr = 3, // MMC 372 Command_set_dsr = 4, 373 Command_io_send_op_cond = 5, // SDIO 374 Command_select_deselect_card = 7, 375 Command_send_if_cond = 8, 376 Command_send_csd = 9, 377 Command_send_cid = 10, 378 Command_read_dat_until_stop = 11, 379 Command_stop_transmission = 12, 380 Command_send_status = 13, 381 Command_go_inactive_state = 15, 382 Command_set_blocklen = 16, 383 Command_read_single_block = 17, 384 Command_read_multiple_block = 18, 385 Command_write_dat_until_stop = 20, 386 Command_set_block_count = 23, 387 Command_write_block = 24, 388 Command_write_multiple_block = 25, 389 Command_program_cid = 26, 390 Command_program_csd = 27, 391 Command_set_write_prot = 28, 392 Command_clr_write_prot = 29, 393 Command_send_write_prot = 30, 394 Command_tag_sector_start = 32, 395 Command_tag_sector_end = 33, 396 Command_untag_sector = 34, 397 Command_tag_erase_group_start = 35, 398 Command_tag_erase_group_end = 36, 399 Command_untag_erase_group = 37, 400 Command_erase = 38, 401 Command_fast_io = 39, 402 Command_go_irq_state = 40, 403 Command_lock_unlock = 42, 404 Command_io_rw_direct = 52, // SDIO 405 Command_app_cmd = 55, 406 Command_gen_cmd = 56, 407 }; 408 409 // Application-specific command indexes, used by first issuing Command_app_cmd. 410 411 enum App_command_index : unsigned 412 { 413 App_command_set_bus_width = 6, 414 App_command_sd_status = 13, 415 App_command_send_num_wr_blocks = 22, 416 App_command_set_wr_block_erase_count = 23, 417 App_command_sd_send_op_cond = 41, 418 App_command_set_clr_card_detect = 42, 419 App_command_send_scr = 51, 420 App_command_read_ocr = 58, 421 }; 422 423 enum Bus_width_bits : unsigned 424 { 425 Bus_width_1bit = 0, 426 Bus_width_4bit = 2, 427 }; 428 429 // Command response sizes in 16-bit units. 430 431 enum Response_sizes : unsigned 432 { 433 Response_size_R1 = 3, 434 Response_size_R2 = 8, // omits the CRC and end bit 435 Response_size_R3 = 3, 436 Response_size_R4 = 3, 437 Response_size_R5 = 3, 438 Response_size_R6 = 3, 439 Response_size_R7 = 3, 440 }; 441 442 // SD_SEND_OP_COND argument flags. 443 444 enum Ocr_argument_flags : unsigned 445 { 446 Ocr_high_capacity_storage = 0x40000000, 447 }; 448 449 // SD_SEND_OP_COND response flags (R3). 450 451 enum Ocr_response_flags : unsigned 452 { 453 Ocr_card_powered_up = 0x80000000, 454 }; 455 456 // R1 status flags. 457 458 enum R1_status_flags : unsigned 459 { 460 R1_status_error_mask = 0xffff0000, 461 }; 462 463 464 465 // MMC response structures. 466 // These are 16-bit aligned to permit conversion to 16-bit arrays. 467 468 struct R1 469 { 470 uint8_t end_crc; 471 uint32_t status; 472 uint8_t index:6, trans_start:2; 473 } __attribute__((packed,aligned(__alignof__(uint16_t)))); 474 475 struct R2 476 { 477 // uint8_t end_crc; (not retrieved) 478 479 union 480 { 481 uint8_t raw[15]; 482 struct CID cid; 483 struct CSD csd; 484 } payload; 485 486 uint8_t reserved_trans_start; 487 } __attribute__((packed,aligned(__alignof__(uint16_t)))); 488 489 struct R3 490 { 491 uint8_t end_reserved; 492 uint32_t ocr; 493 uint8_t reserved_trans_start; 494 } __attribute__((packed,aligned(__alignof__(uint16_t)))); 495 496 // SDIO response structures. 497 498 struct R4 499 { 500 uint8_t end_reserved; 501 uint32_t ocr:24, stuff:3, memory_present:1, number_io_functions:3, ready:1; 502 uint8_t reserved_trans_start; 503 } __attribute__((packed,aligned(__alignof__(uint16_t)))); 504 505 struct R5 506 { 507 uint8_t end_crc; 508 uint8_t data; 509 uint8_t out_of_range:1, invalid_function_number:1, reserved:1, error:1, 510 io_current_state:2, illegal_command:1, crc_error:1; 511 uint16_t stuff; 512 uint8_t index:6, trans_start:2; 513 } __attribute__((packed,aligned(__alignof__(uint16_t)))); 514 515 struct R6 516 { 517 uint8_t end_crc; 518 uint16_t status; 519 uint16_t rca; 520 uint8_t index:6, trans_start:2; 521 } __attribute__((packed,aligned(__alignof__(uint16_t)))); 522 523 struct R7 524 { 525 uint8_t end_crc; 526 527 union 528 { 529 uint32_t check:8, voltage:4, reserved:20; 530 uint32_t raw; 531 } check_voltage; 532 533 uint8_t index:6, trans_start:2; 534 } __attribute__((packed,aligned(__alignof__(uint16_t)))); 535 536 537 538 // Command frame: 539 // byte: start (1), direction (1), command (6) 540 // 4 bytes: argument 541 // byte: CRC (7), end (1) 542 543 // IO_RW_DIRECT argument: 544 // Argument MSB to LSB: R/W (1), function number (3), read after write flag (1), 545 // stuff (1), register address (17), stuff (1), 546 // write data or stuff (8) 547 // 0x88000c08: W, function = 0, read after write, register address = 6 (CCCR), 548 // data = 8 (reset) 549 550 const uint32_t Io_rw_direct_reset = 0x88000c08; 551 552 // (IO_)SEND_OP_COND argument and default voltage range expected in R3, R4: 553 // Argument MSB to LSB: stuff (8), voltage range (16), reserved (8) 554 // 0x00ff8000: voltage range 2.7 - 3.6V 555 556 const uint32_t Ocr_default_voltage_range = 0x00ff8000; 557 558 // SEND_IF_COND argument and default voltage range expected in R7: 559 // Argument MSB to LSB: stuff (20), voltage supplied (4), check (8) 560 // 0x000001aa: voltage range 2.7 - 3.6V, check = 0b10101010 561 562 const uint32_t If_cond_default_voltage_range = 0x000001aa; 563 564 565 566 // Utilities. 567 568 static enum Command_data_control_bits 569 encode_bus_width(uint8_t width) 570 { 571 switch (width) 572 { 573 case 4: return Cdc_bus_width_field_4bit; 574 case 1: return Cdc_bus_width_field_1bit; 575 default: return Cdc_bus_width_field_1bit; 576 } 577 } 578 579 580 581 // Channel abstraction. 582 583 Msc_channel::Msc_channel(l4_addr_t msc_start, l4_addr_t addr, l4_cap_idx_t irq) 584 : _msc_start(msc_start), _irq(irq) 585 { 586 _regs = new Hw::Mmio_register_block<32>(addr); 587 } 588 589 Msc_channel::~Msc_channel() 590 { 591 } 592 593 // Utility methods. 594 // NOTE: Also defined in the CPM abstraction, should be consolidated. 595 596 uint32_t 597 Msc_channel::get_field(uint32_t reg, uint32_t mask, uint8_t shift) 598 { 599 return (_regs[reg] & (mask << shift)) >> shift; 600 } 601 602 void 603 Msc_channel::set_field(uint32_t reg, uint32_t mask, uint8_t shift, uint32_t value) 604 { 605 _regs[reg] = (_regs[reg] & (~(mask << shift))) | ((mask & value) << shift); 606 } 607 608 bool 609 Msc_channel::command_will_write(uint8_t index) 610 { 611 // NOTE: Probably incomplete coverage. 612 613 switch (index) 614 { 615 case Command_write_dat_until_stop: return true; 616 case Command_write_block: return true; 617 case Command_write_multiple_block: return true; 618 case Command_program_cid: return true; 619 case Command_program_csd: return true; 620 case Command_lock_unlock: return true; 621 default: return false; 622 } 623 } 624 625 bool 626 Msc_channel::app_command_will_write(uint8_t index) 627 { 628 // NOTE: Probably incomplete coverage. 629 630 (void) index; 631 632 return false; 633 } 634 635 bool 636 Msc_channel::command_with_data(uint8_t index) 637 { 638 // NOTE: Probably incomplete coverage. 639 640 switch (index) 641 { 642 case Command_read_dat_until_stop: return true; 643 case Command_read_single_block: return true; 644 case Command_read_multiple_block: return true; 645 case Command_write_dat_until_stop: return true; 646 case Command_write_block: return true; 647 case Command_write_multiple_block: return true; 648 case Command_program_cid: return true; 649 case Command_program_csd: return true; 650 case Command_lock_unlock: return true; 651 default: return false; 652 } 653 } 654 655 bool 656 Msc_channel::app_command_with_data(uint8_t index) 657 { 658 // NOTE: Probably incomplete coverage. 659 660 switch (index) 661 { 662 case App_command_sd_status: return true; 663 case App_command_send_num_wr_blocks: return true; 664 case App_command_send_scr: return true; 665 default: return false; 666 } 667 } 668 669 bool 670 Msc_channel::command_uses_busy(uint8_t index) 671 { 672 // NOTE: Probably incomplete coverage. 673 674 switch (index) 675 { 676 case Command_select_deselect_card: return true; 677 case Command_stop_transmission: return true; 678 default: return false; 679 } 680 } 681 682 bool 683 Msc_channel::app_command_uses_busy(uint8_t index) 684 { 685 // NOTE: Probably incomplete coverage. 686 687 (void) index; 688 689 return false; 690 } 691 692 uint8_t 693 Msc_channel::get_response_format(uint8_t index) 694 { 695 // NOTE: Probably incomplete coverage. 696 697 switch (index) 698 { 699 // Common commands without response. 700 701 case Command_go_idle_state: return 0; 702 case Command_set_dsr: return 0; 703 case Command_go_inactive_state: return 0; 704 705 // Common commands with response. 706 707 case Command_send_op_cond: return 3; 708 case Command_all_send_cid: return 2; 709 case Command_send_csd: return 2; 710 case Command_send_cid: return 2; 711 712 // SDIO only. 713 714 case Command_io_send_op_cond: return 4; 715 case Command_io_rw_direct: return 5; 716 717 // SDMEM only. 718 719 case Command_send_relative_addr: return 6; 720 case Command_send_if_cond: return 7; 721 722 // All other commands. 723 724 default: return 1; 725 } 726 } 727 728 uint8_t 729 Msc_channel::get_app_response_format(uint8_t index) 730 { 731 // NOTE: Probably incomplete coverage. 732 733 switch (index) 734 { 735 // SDMEM only. 736 737 case App_command_sd_send_op_cond: return 3; 738 739 // All other commands. 740 741 default: return 1; 742 } 743 } 744 745 // Read a response directly from the FIFO. 746 747 void 748 Msc_channel::read_response(uint16_t *buffer, uint8_t units) 749 { 750 uint8_t unit = units; 751 752 while (unit > 0) 753 { 754 uint32_t data = _regs[Msc_response_fifo]; 755 756 // Ignore the upper byte of the last unit in small transfers since it is the 757 // lower byte from the previous unit not shifted out of the register. 758 759 unit--; 760 761 if ((unit == 0) && (units == 3)) 762 buffer[unit] = (data & 0xff) << 8; 763 else 764 buffer[unit] = data; 765 } 766 } 767 768 void 769 Msc_channel::ack_irq(uint32_t flags) 770 { 771 // Clear the flags by setting them. 772 773 _regs[Msc_interrupt_flag] = _regs[Msc_interrupt_flag] | flags; 774 } 775 776 void 777 Msc_channel::unmask_irq(uint32_t flags) 778 { 779 ack_irq(flags); 780 781 if (_regs[Msc_interrupt_mask] & flags) 782 _regs[Msc_interrupt_mask] = _regs[Msc_interrupt_mask] & ~flags; 783 } 784 785 void 786 Msc_channel::reset() 787 { 788 _regs[Msc_control] = _regs[Msc_control] | Control_reset; 789 790 // NOTE: X1600 and other recent SoCs only. 791 792 _regs[Msc_control] = _regs[Msc_control] & ~Control_reset; 793 794 // Sufficient for other SoCs... 795 796 while (_regs[Msc_status] & Status_resetting); 797 } 798 799 void 800 Msc_channel::start_clock() 801 { 802 set_field(Msc_control, Control_clock_control_field_mask, 803 Control_clock_control_field_shift, Control_clock_control_start); 804 805 while (!(_regs[Msc_status] & Status_clock_enabled)); 806 } 807 808 void 809 Msc_channel::stop_clock() 810 { 811 set_field(Msc_control, Control_clock_control_field_mask, 812 Control_clock_control_field_shift, Control_clock_control_stop); 813 814 while (_regs[Msc_status] & Status_clock_enabled); 815 } 816 817 // Send an application-specific command. 818 819 bool 820 Msc_channel::send_app_command(uint8_t index, uint32_t arg) 821 { 822 if (!send_command(Command_app_cmd, _cards[_card].rca << 16)) 823 return false; 824 825 return send_command(index, arg, get_app_response_format(index), 826 app_command_with_data(index), 827 app_command_will_write(index), 828 app_command_uses_busy(index)); 829 } 830 831 // Send a common MMC/SD command. 832 833 bool 834 Msc_channel::send_command(uint8_t index, uint32_t arg) 835 { 836 return send_command(index, arg, get_response_format(index), 837 command_with_data(index), 838 command_will_write(index), 839 command_uses_busy(index)); 840 } 841 842 // Initiate a command having the given index and using the given argument, 843 // employing the specified response format and involving a data transfer if 844 // indicated. 845 846 bool 847 Msc_channel::send_command(uint8_t index, uint32_t arg, uint8_t response_format, 848 bool data, bool write, bool busy) 849 { 850 stop_clock(); 851 852 // Enable DMA for data transfers. 853 // NOTE: Needed for JZ4780 and later SoCs. 854 855 _regs[Msc_dma_control] = (data ? Dma_select_common_dma | Dma_enable : Dma_disable); 856 857 // Set the command index and argument. 858 859 _regs[Msc_command_index] = index; 860 _regs[Msc_command_argument] = arg; 861 862 // Configure the response format and data bus width. 863 864 set_field(Msc_command_data_control, Cdc_response_format_field_mask, 865 Cdc_response_format_field_shift, response_format); 866 867 // NOTE: May need to set the SD bus width. 868 869 set_field(Msc_command_data_control, Cdc_bus_width_field_mask, 870 Cdc_bus_width_field_shift, encode_bus_width(_cards[_card].bus_width)); 871 872 set_field(Msc_command_data_control, Cdc_recv_fifo_level_field_mask, 873 Cdc_recv_fifo_level_field_shift, Cdc_fifo_level_16); 874 875 set_field(Msc_command_data_control, Cdc_trans_fifo_level_field_mask, 876 Cdc_trans_fifo_level_field_shift, Cdc_fifo_level_16); 877 878 // Set and clear control bits appropriate to the command. 879 // NOTE: Pre-JZ4780 SoCs enable DMA in this register. 880 881 _regs[Msc_command_data_control] = _regs[Msc_command_data_control] | 882 // (data ? Cdc_dma_enable : Cdc_dma_disable) | 883 (busy ? Cdc_expect_busy : Cdc_do_not_expect_busy) | 884 (data ? Cdc_data_with_command : Cdc_no_data_with_command) | 885 (write ? Cdc_write_operation : Cdc_read_operation); 886 887 _regs[Msc_command_data_control] = _regs[Msc_command_data_control] & 888 ~( 889 // (data ? Cdc_dma_disable : Cdc_dma_enable) | 890 (busy ? Cdc_do_not_expect_busy : Cdc_expect_busy) | 891 (data ? Cdc_no_data_with_command : Cdc_data_with_command) | 892 (write ? Cdc_read_operation : Cdc_write_operation) | 893 Cdc_stream_block | Cdc_init_sequence); 894 895 // Unmask interrupts, start the clock, then initiate the command. 896 897 uint32_t flags = Int_end_command_response | Int_response_timeout; 898 899 unmask_irq(flags); 900 start_clock(); 901 902 _regs[Msc_control] = _regs[Msc_control] | Control_start_operation; 903 904 // Wait for command completion. 905 906 if (!wait_for_irq(flags)) 907 return false; 908 909 // Determine whether a timeout occurred. 910 911 bool have_response = !((_regs[Msc_interrupt_flag] & Int_response_timeout) || 912 (_regs[Msc_status] & Status_response_crc_error) || 913 (_regs[Msc_status] & Status_timeout_response)); 914 915 // Acknowledge the response interrupts and return the status. 916 917 ack_irq(flags); 918 return have_response; 919 } 920 921 // Wait indefinitely for an interrupt request, returning true if one was delivered. 922 923 bool 924 Msc_channel::wait_for_irq(uint32_t flags) 925 { 926 return !l4_error(l4_irq_receive(_irq, L4_IPC_NEVER)) && 927 (_regs[Msc_interrupt_flag] & flags); 928 } 929 930 // Wait up to the given timeout (in microseconds) for an interrupt request, 931 // returning true if one was delivered. 932 933 bool 934 Msc_channel::wait_for_irq(uint32_t flags, unsigned int timeout) 935 { 936 return !l4_error(l4_irq_receive(_irq, l4_timeout(L4_IPC_TIMEOUT_NEVER, 937 l4util_micros2l4to(timeout)))) && 938 (_regs[Msc_interrupt_flag] & flags); 939 } 940 941 942 943 // Check the voltage range of the SD card, potentially establishing that it is 944 // a high capacity card. Return false if the voltage range is incompatible. 945 946 bool 947 Msc_channel::check_sd() 948 { 949 struct R7 r7; 950 951 // Send an interface condition command. 952 // A card may not respond to this command. 953 954 if (!send_command(Command_send_if_cond, If_cond_default_voltage_range)) 955 return true; 956 957 read_response((uint16_t *) &r7, Response_size_R7); 958 959 // Reject any card not supporting the default voltage range. 960 961 if (r7.check_voltage.raw != If_cond_default_voltage_range) 962 return false; 963 964 return true; 965 } 966 967 // Check the voltage range of the SDIO card, inactivating it if incompatible. 968 969 void 970 Msc_channel::init_sdio() 971 { 972 struct R4 r4; 973 uint32_t ocr = 0; 974 975 // Reset any SDIO card or IO unit in a combined memory/IO card. 976 // A non-SDIO card may not respond to this command. 977 978 if (!send_command(Command_io_rw_direct, Io_rw_direct_reset)) 979 return; 980 981 // Attempt to assert the operating conditions. 982 983 do 984 { 985 // Obtain OCR (operating conditions register) values for any IO card. 986 // Without a response, the card may have inactivated itself due to voltage 987 // range incompatibility reasons. 988 989 if (!send_command(Command_io_send_op_cond, ocr)) 990 return; 991 992 read_response((uint16_t *) &r4, Response_size_R4); 993 994 // Finish if no IO functions provided. 995 // NOTE: Should only need to check this the first time. 996 997 if (r4.number_io_functions == 0) 998 return; 999 1000 if (r4.ocr != Ocr_default_voltage_range) 1001 { 1002 ocr = Ocr_default_voltage_range; 1003 continue; 1004 } 1005 } 1006 while (!r4.ready); 1007 } 1008 1009 void 1010 Msc_channel::init_sdmem() 1011 { 1012 struct R3 r3; 1013 1014 // Incorporate the HCS bit into the OCR for SDMEM. 1015 1016 uint32_t ocr = Ocr_high_capacity_storage; 1017 1018 do 1019 { 1020 if (!send_app_command(App_command_sd_send_op_cond, ocr)) 1021 return; 1022 1023 read_response((uint16_t *) &r3, Response_size_R3); 1024 1025 if (r3.ocr != Ocr_default_voltage_range) 1026 { 1027 ocr = Ocr_default_voltage_range | Ocr_high_capacity_storage; 1028 continue; 1029 } 1030 } 1031 while (!(r3.ocr & Ocr_card_powered_up)); 1032 } 1033 1034 void 1035 Msc_channel::init_mmc() 1036 { 1037 // Obtain OCR (operating conditions register) values for each card using 1038 // send_op_cond command variants without argument, or assert operating 1039 // conditions with argument to avoid handling card responses. Where responses 1040 // are solicited, the host must determine a suitable argument and reissue the 1041 // command. 1042 1043 struct R3 r3; 1044 uint32_t ocr = 0; 1045 1046 do 1047 { 1048 if (!send_command(Command_send_op_cond, ocr)) 1049 return; 1050 1051 read_response((uint16_t *) &r3, Response_size_R3); 1052 1053 if (r3.ocr != Ocr_default_voltage_range) 1054 { 1055 ocr = Ocr_default_voltage_range; 1056 continue; 1057 } 1058 } 1059 while (!(r3.ocr & Ocr_card_powered_up)); 1060 } 1061 1062 void 1063 Msc_channel::identify_cards() 1064 { 1065 struct R2 r2; 1066 struct R6 r6; 1067 1068 _num_cards = 0; 1069 1070 while (send_command(Command_all_send_cid, 0)) 1071 { 1072 read_response((uint16_t *) &r2, Response_size_R2); 1073 1074 _cards[_num_cards].cid = r2.payload.cid; 1075 1076 printf("card: %d\n", _num_cards); 1077 printf("date: %d %d\n", r2.payload.cid.month, r2.payload.cid.year); 1078 printf("serial: %d\n", r2.payload.cid.serial); 1079 printf("revision: %d\n", r2.payload.cid.revision); 1080 printf("name: %c%c%c%c%c\n", r2.payload.cid.name[4], r2.payload.cid.name[3], 1081 r2.payload.cid.name[2], r2.payload.cid.name[1], 1082 r2.payload.cid.name[0]); 1083 printf("oem: %d\n", r2.payload.cid.oem); 1084 printf("manufacturer: %d\n", r2.payload.cid.manufacturer); 1085 1086 // Try and obtain a card-issued address. 1087 1088 if (send_command(Command_send_relative_addr, 0)) 1089 { 1090 read_response((uint16_t *) &r6, Response_size_R6); 1091 _cards[_num_cards].rca = r6.rca; 1092 } 1093 1094 // Try and assign an address. 1095 // Employ 1-based relative addressing. 1096 1097 else if (send_command(Command_set_relative_addr, _num_cards + 1)) 1098 _cards[_num_cards].rca = _num_cards + 1; 1099 1100 // Otherwise, stop identification. 1101 1102 else 1103 return; 1104 1105 // Set the default bus width to be determined. 1106 1107 _cards[_num_cards].bus_width = 0; 1108 1109 _num_cards++; 1110 } 1111 } 1112 1113 void 1114 Msc_channel::query_cards() 1115 { 1116 struct R2 r2; 1117 struct R3 r3; 1118 uint8_t card; 1119 1120 for (card = 0; card < _num_cards; card++) 1121 { 1122 // Employ 1-based relative addressing. 1123 1124 if (!send_command(Command_send_csd, _cards[card].rca << 16)) 1125 return; 1126 1127 read_response((uint16_t *) &r2, Response_size_R2); 1128 1129 _cards[card].csd = r2.payload.csd; 1130 1131 struct CSD *csd = &_cards[card].csd; 1132 1133 printf("card: %d\n", card); 1134 printf("csd: %d\n", csd->csd); 1135 printf("copy: %s\n", csd->copy ? "copied" : "original"); 1136 printf("card command classes: %03x\n", csd->card_command_classes); 1137 printf("device (size multiplier): %d %d\n", csd->device_size + 1, 1138 1 << (csd->device_size_multiplier + 2)); 1139 printf("device size: %d\n", (1 << csd->read_blocklen) * 1140 (csd->device_size + 1) * 1141 (1 << (csd->device_size_multiplier + 2))); 1142 printf("transfer speed: %d MHz\n", csd->tran_speed == 0x32 ? 25 : 50); 1143 printf("format group: %d %d\n", csd->format, r2.payload.csd.format_group); 1144 printf("write time factor: %d\n", 1 << csd->write_time_factor); 1145 printf("write protect (temp perm): %s %s\n", csd->temp_write_prot ? "yes" : "no", 1146 csd->perm_write_prot ? "yes" : "no"); 1147 printf("write protect group (enable size): %s %d\n", csd->write_prot_group_enable ? "yes" : "no", 1148 csd->write_prot_group_size + 1); 1149 printf("write block (partial length): %s %d\n", csd->write_block_partial ? "yes" : "no", 1150 1 << csd->write_blocklen); 1151 printf("read block (partial length): %s %d\n", csd->read_block_partial ? "yes" : "no", 1152 1 << csd->read_blocklen); 1153 printf("erase: sector single: %d %s\n", csd->erase_sector_size + 1, 1154 csd->erase_single_block_enable ? "yes" : "no"); 1155 printf("misalign: read write: %s %s\n", csd->read_block_misalign ? "yes" : "no", 1156 csd->write_block_misalign ? "yes" : "no"); 1157 printf("max read current (min max): %d %d\n", csd->max_read_current_min, 1158 csd->max_read_current_max); 1159 printf("max write current (min max): %d %d\n", csd->max_write_current_min, 1160 csd->max_write_current_max); 1161 printf("read access time (1 2): %d %d\n", csd->data_read_access_time_1, 1162 csd->data_read_access_time_2); 1163 printf("DSR: %s\n", csd->dsr_implemented ? "yes" : "no"); 1164 1165 // Query the OCR again now that we can associate it with a specific card. 1166 1167 if (!send_app_command(App_command_read_ocr, 0)) 1168 return; 1169 1170 read_response((uint16_t *) &r3, Response_size_R3); 1171 1172 _cards[card].ocr = r3.ocr; 1173 } 1174 } 1175 1176 1177 1178 // Enable the controller and identify cards. 1179 1180 void 1181 Msc_channel::enable() 1182 { 1183 // NOTE: X1600 and other recent SoCs only. 1184 1185 _regs[Msc_low_power_mode] = _regs[Msc_low_power_mode] & ~Low_power_mode_enable; 1186 1187 stop_clock(); 1188 reset(); 1189 1190 // Slow the clock for initialisation. 1191 // NOTE: Should use the CPM module to deduce the appropriate divider value. 1192 1193 set_field(Msc_clock_rate, Clock_rate_field_mask, Clock_rate_field_shift, 7); 1194 1195 send_command(Command_go_idle_state, 0); 1196 1197 if (check_sd()) 1198 { 1199 init_sdio(); 1200 init_sdmem(); 1201 } 1202 1203 init_mmc(); 1204 identify_cards(); 1205 query_cards(); 1206 1207 // Restore the clock. 1208 // NOTE: Should use the CPM module to deduce the appropriate divider value. 1209 1210 set_field(Msc_clock_rate, Clock_rate_field_mask, Clock_rate_field_shift, 1); 1211 1212 // Initially, no card is selected. 1213 1214 _card = -1; 1215 } 1216 1217 // Obtain the card details. 1218 1219 struct msc_card * 1220 Msc_channel::get_cards() 1221 { 1222 return _cards; 1223 } 1224 1225 // Return the number of active cards. 1226 1227 uint8_t 1228 Msc_channel::num_cards() 1229 { 1230 return _num_cards; 1231 } 1232 1233 // Receive data from the selected card. 1234 1235 uint32_t 1236 Msc_channel::recv_data(l4re_dma_space_dma_addr_t paddr, uint32_t count) 1237 { 1238 uint32_t flags = Int_data_transfer_done; 1239 1240 unmask_irq(flags); 1241 1242 uint32_t to_transfer = transfer(_msc_start + Msc_recv_data_fifo, paddr, true, count); 1243 1244 wait_for_irq(flags); 1245 ack_irq(flags); 1246 1247 if (!to_transfer || 1248 (_regs[Msc_status] & Status_read_crc_error) || 1249 (_regs[Msc_status] & Status_timeout_read)) 1250 return 0; 1251 1252 return to_transfer; 1253 } 1254 1255 // Send data to the selected card. 1256 1257 uint32_t 1258 Msc_channel::send_data(l4re_dma_space_dma_addr_t paddr, uint32_t count) 1259 { 1260 uint32_t flags = Int_data_transfer_done; 1261 1262 unmask_irq(flags); 1263 1264 uint32_t to_transfer = transfer(paddr, _msc_start + Msc_trans_data_fifo, false, count); 1265 1266 wait_for_irq(flags); 1267 ack_irq(flags); 1268 1269 if (!to_transfer || 1270 (_regs[Msc_status] & Status_write_crc_error_data) || 1271 (_regs[Msc_status] & Status_write_crc_error_no_status)) 1272 return 0; 1273 1274 return to_transfer; 1275 } 1276 1277 // Read blocks from the indicated card into a memory region. 1278 1279 uint32_t 1280 Msc_channel::read_blocks(uint8_t card, l4re_dma_space_dma_addr_t paddr, 1281 uint32_t block_address, uint32_t block_count) 1282 { 1283 uint32_t block_size = 1 << _cards[card].csd.read_blocklen; 1284 struct R1 r1; 1285 1286 // Select the requested card. 1287 1288 if (_card != card) 1289 { 1290 if (!send_command(Command_select_deselect_card, _cards[card].rca << 16)) 1291 return 0; 1292 1293 read_response((uint16_t *) &r1, Response_size_R1); 1294 1295 if (r1.status & R1_status_error_mask) 1296 return 0; 1297 1298 _card = card; 1299 } 1300 1301 // NOTE: SMEM cards should allow bus width setting with the SCR register 1302 // NOTE: describing the permitted values. 1303 // NOTE: SDIO cards have their bus width set in CCCR via CMD52. 1304 1305 if (!_cards[card].bus_width) 1306 { 1307 if (send_app_command(App_command_set_bus_width, Bus_width_4bit)) 1308 _cards[card].bus_width = 4; 1309 else 1310 _cards[card].bus_width = 1; 1311 } 1312 1313 if (!send_command(Command_set_blocklen, block_size)) 1314 return 0; 1315 1316 read_response((uint16_t *) &r1, Response_size_R1); 1317 1318 if (r1.status & R1_status_error_mask) 1319 return 0; 1320 1321 // NOTE: Consider issuing a predefined block count command to any multiple 1322 // NOTE: block operation, at least for cards that support it. 1323 1324 // Apply block count and size properties to the issued command. 1325 1326 _regs[Msc_block_count] = block_count; 1327 _regs[Msc_block_length] = block_size; 1328 1329 // Where CCS = 0, byte addressing is used. Otherwise, block addressing is used. 1330 1331 uint32_t address; 1332 1333 if (_cards[card].ocr & Ocr_high_capacity_storage) 1334 address = block_address; 1335 else 1336 address = block_address * block_size; 1337 1338 if (!send_command(block_count == 1 ? Command_read_single_block 1339 : Command_read_multiple_block, address)) 1340 return 0; 1341 1342 read_response((uint16_t *) &r1, Response_size_R1); 1343 1344 if (r1.status & R1_status_error_mask) 1345 return 0; 1346 1347 // NOTE: Use Msc_block_success_count instead. 1348 1349 uint32_t transferred = recv_data(paddr, block_size * block_count); 1350 1351 if (block_count > 1) 1352 send_command(Command_stop_transmission, 0); 1353 1354 return transferred; 1355 } 1356 1357 1358 1359 // Peripheral abstraction. 1360 1361 Msc_chip::Msc_chip(l4_addr_t msc_start, l4_addr_t start, l4_addr_t end) 1362 : _msc_start(msc_start), _start(start), _end(end) 1363 { 1364 }