1 /* 2 * I2C support for the X1600. 3 * 4 * Copyright (C) 2017, 2018, 2021, 2023 Paul Boddie <paul@boddie.org.uk> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 19 * Boston, MA 02110-1301, USA 20 */ 21 22 #include <l4/devices/i2c-x1600.h> 23 #include <l4/devices/hw_mmio_register_block.h> 24 25 #include <l4/sys/icu.h> 26 #include <l4/util/util.h> 27 #include <sys/time.h> 28 29 /* NOTE: This peripheral is very similar to the JZ4780 with the registers 30 renamed to I2C from SMB, with a few high speed registers added, and 31 with I2C_SDAHD appearing at a different location. */ 32 33 enum Regs 34 { 35 I2c_control = 0x000, // I2C_CON 36 I2c_target_address = 0x004, // I2C_TAR 37 I2c_slave_address = 0x008, // I2C_SAR 38 I2c_master_code = 0x00c, // I2C_HS_MADDR 39 I2c_data_command = 0x010, // I2C_DC 40 Std_high_count = 0x014, // I2C_SHCNT 41 Std_low_count = 0x018, // I2C_SLCNT 42 Fast_high_count = 0x01c, // I2C_FHCNT 43 Fast_low_count = 0x020, // I2C_FLCNT 44 High_high_count = 0x024, // I2C_HHCNT 45 High_low_count = 0x028, // I2C_HLCNT 46 Int_status = 0x02c, // I2C_INTST (read-only) 47 Int_mask = 0x030, // I2C_INTM 48 Int_raw_status = 0x034, // I2C_RINTST (read-only) 49 Rx_fifo_thold = 0x038, // I2C_RXTL 50 Tx_fifo_thold = 0x03c, // I2C_TXTL 51 Int_combined_clear = 0x040, // I2C_CINT (read-only) 52 Int_rx_uf_clear = 0x044, // I2C_CRXUF (read-only) 53 Int_rx_of_clear = 0x048, // I2C_CRXOF (read-only) 54 Int_tx_of_clear = 0x04c, // I2C_CTXOF (read-only) 55 Int_rd_req_clear = 0x050, // I2C_CRXREQ (read-only) 56 Int_tx_abort_clear = 0x054, // I2C_CTXABT (read-only) 57 Int_rx_done_clear = 0x058, // I2C_CRXDN (read-only) 58 Int_activity_clear = 0x05c, // I2C_CACT (read-only) 59 Int_stop_clear = 0x060, // I2C_CSTP (read-only) 60 Int_start_clear = 0x064, // I2C_CSTT (read-only) 61 Int_call_clear = 0x068, // I2C_CGC (read-only) 62 I2c_enable = 0x06c, // I2C_ENB 63 I2c_status = 0x070, // I2C_ST (read-only) 64 Tx_fifo_count = 0x074, // I2C_TXFLR (read-only) 65 Rx_fifo_count = 0x078, // I2C_RXFLR (read-only) 66 I2c_sda_hold_time = 0x07c, // I2C_SDAHD 67 Trans_abort_status = 0x080, // I2C_ABTSRC (read-only) 68 Slv_data_nack = 0x084, // I2CSDNACK 69 I2c_dma_ctrl = 0x088, // I2C_DMACR 70 I2c_trans_data_lvl = 0x08c, // I2C_DMATDLR 71 I2c_recv_data_lvl = 0x090, // I2C_DMARDLR 72 I2c_sda_setup_time = 0x094, // I2C_SDASU 73 I2c_ack_call = 0x098, // I2C_ACKGC 74 I2c_enable_status = 0x09c, // I2C_ENBST (read-only) 75 I2c_spike_suppress = 0x0a0, // I2C_FSPKLEN 76 77 I2c_block_offset = 0x1000 78 }; 79 80 enum I2c_control_bits : unsigned 81 { 82 I2c_disable_slave = 0x40, // SLVDIS (slave disabled) 83 I2c_enable_restart = 0x20, // RESTART 84 I2c_master_10bit = 0x10, // MATP (read-only) 85 I2c_slave_10bit = 0x08, // SATP 86 I2c_speed_mode_mask = 0x06, // SPEED 87 I2c_enable_master = 0x01, // MD (master enabled) 88 I2c_speed_bit = 1, // SPD 89 }; 90 91 enum I2c_speed_mode_values : unsigned 92 { 93 I2c_speed_standard = 1, 94 I2c_speed_fast = 2, 95 I2c_speed_high = 3, 96 }; 97 98 enum I2c_enable_bits : unsigned 99 { 100 I2c_enable_enabled = 0x01, // I2CEN 101 }; 102 103 enum I2c_status_bits : unsigned 104 { 105 I2c_status_master_act = 0x20, // MSTACT (master active) 106 I2c_status_rx_nempty = 0x08, // RFNE (read queue not empty) 107 I2c_status_tx_empty = 0x04, // TFE (write queue empty) 108 I2c_status_tx_nfull = 0x02, // TFNF (write queue not full) 109 I2c_status_active = 0x01, // ACT (device active as master or slave) 110 }; 111 112 enum I2c_target_bits : unsigned 113 { 114 I2c_target_master_10bit = 0x1000, 115 I2c_target_special = 0x0800, // SPECIAL: perform general call or start byte 116 I2c_target_start_byte = 0x0400, // Special: start byte (1) or general call (0) 117 I2c_target_10bits = 0x3ff, // Mask for 10-bit address 118 I2c_target_7bits = 0x7f, // Mask for 7-bit address 119 }; 120 121 enum I2c_hold_control_bits : unsigned 122 { 123 /* The hold enable flag has been removed since the JZ4780 and the hold time 124 field widened. */ 125 126 I2c_hold_mask = 0xffff, 127 }; 128 129 enum I2c_setup_control_bits : unsigned 130 { 131 I2c_setup_mask = 0x0ff, // SDASU 132 }; 133 134 enum I2c_command_bits : unsigned 135 { 136 I2c_command_restart = 0x400, // RESTART: explicit restart before next byte 137 I2c_command_stop = 0x200, // STOP: explicit stop after next byte 138 I2c_command_no_stop = 0x000, 139 I2c_command_read = 0x100, // CMD 140 I2c_command_write = 0x000, // CMD 141 }; 142 143 enum I2c_fifo_bits : unsigned 144 { 145 I2c_fifo_limit = 64, // RXTL, TXTL (256 noted in field description) 146 }; 147 148 enum Int_bits : unsigned 149 { 150 Int_call = 0x800, // IGC (general call received) 151 Int_start = 0x400, // ISTT (start/restart condition occurred) 152 Int_stop = 0x200, // ISTP (stop condition occurred) 153 Int_activity = 0x100, // IACT (bus activity interrupt) 154 Int_rx_done = 0x080, // RXDN (read from master device done) 155 Int_tx_abort = 0x040, // TXABT (transmit abort) 156 Int_rd_req = 0x020, // RDREQ (read request from master device) 157 Int_tx_empty = 0x010, // TXEMP (threshold reached or passed) 158 Int_tx_of = 0x008, // TXOF (overflow when writing to queue) 159 Int_rx_full = 0x004, // RXFL (threshold reached or exceeded) 160 Int_rx_of = 0x002, // RXOF (overflow from device) 161 Int_rx_uf = 0x001, // RXUF (underflow when reading from queue) 162 }; 163 164 165 166 // Initialise a channel. 167 168 I2c_x1600_channel::I2c_x1600_channel(l4_addr_t start, 169 enum Clock_identifiers clock, 170 Cpm_x1600_chip *cpm, 171 uint32_t frequency) 172 : _cpm(cpm), _frequency(frequency) 173 { 174 _regs = new Hw::Mmio_register_block<32>(start); 175 _cpm->start_clock(clock); 176 } 177 178 // Enable the channel. 179 180 void 181 I2c_x1600_channel::enable() 182 { 183 _regs[I2c_enable] = I2c_enable_enabled; 184 while (!(_regs[I2c_enable_status] & I2c_enable_enabled)); 185 } 186 187 // Disable the channel. 188 189 void 190 I2c_x1600_channel::disable() 191 { 192 _regs[I2c_enable] = 0; 193 while (_regs[I2c_enable_status] & I2c_enable_enabled); 194 } 195 196 // Return the configured frequency. 197 198 uint32_t 199 I2c_x1600_channel::get_frequency() 200 { 201 return _frequency; 202 } 203 204 // Set the frequency-related peripheral parameters. 205 206 void 207 I2c_x1600_channel::set_frequency() 208 { 209 // The APB clock (PCLK) is used to drive I2C transfers. Its value must be 210 // obtained from the CPM unit. It is known as I2C_DEV_CLK here and is scaled 211 // to kHz in order to keep the numbers easily representable, as is the bus 212 // frequency. 213 214 uint32_t i2c_dev_clk = _cpm->get_frequency(Clock_pclock) / 1000; 215 216 // Note that this is not I2C_DEV_CLK but the actual I2C bus frequency. 217 218 uint32_t i2c_clk = _frequency / 1000; 219 220 // Select the appropriate speed. 221 222 unsigned int speed = (i2c_clk <= 100) ? I2c_speed_standard 223 : (i2c_clk <= 400 ? I2c_speed_fast 224 : I2c_speed_high); 225 226 // NOTE: Permit broader configuration elsewhere. 227 228 _regs[I2c_control] = (speed << I2c_speed_bit) | 229 I2c_disable_slave | 230 I2c_enable_restart | 231 I2c_enable_master; 232 233 // According to the programming manual, if the PCLK period is T{I2C_DEV_CLK} 234 // then the I2C clock period is... 235 236 // T{SCL} = T{SCL_high} + T{SCL_low} 237 238 // Where... 239 240 // T{SCL_low} = T{I2C_DEV_CLK} * (#cycles for low signal) 241 // T{SCL_high} = T{I2C_DEV_CLK} * (#cycles for high signal) 242 243 // Since, with minimum periods being defined... 244 245 // T{SCL} >= T{min_SCL} 246 // T{SCL_low} >= T{min_SCL_low} 247 // T{SCL_high} >= T{min_SCL_high} 248 // T{min_SCL} = T{min_SCL_low} + T{min_SCL_high} 249 250 // Then the following applies... 251 252 // T{I2C_DEV_CLK} * (#cycles for low signal)) >= T{min_SCL_low} 253 // T{I2C_DEV_CLK} * (#cycles for high signal) >= T{min_SCL_high} 254 255 // To work with different clock speeds while maintaining the low-to-high 256 // ratios: 257 258 // T{min_SCL_low} = T{min_SCL} * T{min_SCL_low} / T{min_SCL} 259 // = T{min_SCL} * (T{min_SCL_low} / (T{min_SCL_low} + T{min_SCL_high})) 260 261 // T{min_SCL_high} = T{min_SCL} * T{min_SCL_high} / T{min_SCL} 262 // = T{min_SCL} * (T{min_SCL_high} / (T{min_SCL_low} + T{min_SCL_high})) 263 264 // Constraints are given with respect to the high and low count registers. 265 266 // #cycles for high signal = I2CxHCNT + 8 267 // #cycles for low signal = I2CxLCNT + 1 268 269 // From earlier, this yields... 270 271 // T{I2C_DEV_CLK} * (I2CxLCNT + 1) >= T{min_SCL_low} 272 // T{I2C_DEV_CLK} * (I2CxHCNT + 8) >= T{min_SCL_high} 273 274 // Rearranging... 275 276 // I2CxLCNT >= (T{min_SCL_low} / T{I2C_DEV_CLK}) - 1 277 // >= T{min_SCL_low} * I2C_DEV_CLK - 1 278 279 // I2CxHCNT >= (T{min_SCL_high} / T{I2C_DEV_CLK}) - 8 280 // >= T{min_SCL_high} * I2C_DEV_CLK - 8 281 282 // Introducing the definitions for the high and low periods... 283 284 // I2CxLCNT >= T{min_SCL} * (T{min_SCL_low} / (T{min_SCL_low} + T{min_SCL_high})) * I2C_DEV_CLK - 1 285 // >= (T{min_SCL_low} / T{min_SCL}) * I2C_DEV_CLK / I2C_BUS_CLK - 1 286 287 // I2CxHCNT >= T{min_SCL} * (T{min_SCL_high} / (T{min_SCL_low} + T{min_SCL_high})) * I2C_DEV_CLK - 8 288 // >= (T{min_SCL_high} / T{min_SCL}) * I2C_DEV_CLK / I2C_BUS_CLK - 8 289 290 uint32_t high_reg, low_reg; 291 uint32_t high_count, low_count; 292 int32_t hold_count; 293 uint32_t setup_count; 294 295 // Level hold times: 296 297 // Standard Fast High 298 // SCL low 4.7us 1.3us 0.5us 299 // SCL high 4.0us 0.6us 0.26us + 300 // SCL period 8.7us 1.9us 0.76us = 301 302 // See: UM10204 "I2C-bus specification and user manual" 303 // Table 10: t{LOW} and t{HIGH} 304 305 if (i2c_clk <= 100) // 100 kHz 306 { 307 low_count = (i2c_dev_clk * 47) / (i2c_clk * 87) - 1; 308 high_count = (i2c_dev_clk * 40) / (i2c_clk * 87) - 8; 309 low_reg = Std_low_count; 310 high_reg = Std_high_count; 311 } 312 else if (i2c_clk <= 400) // 400 kHz 313 { 314 low_count = (i2c_dev_clk * 13) / (i2c_clk * 19) - 1; 315 high_count = (i2c_dev_clk * 6) / (i2c_clk * 19) - 8; 316 low_reg = Fast_low_count; 317 high_reg = Fast_high_count; 318 } 319 else // > 400 kHz 320 { 321 // Note how the frequencies are scaled to accommodate the extra precision 322 // required. 323 324 low_count = (i2c_dev_clk / 10 * 50) / (i2c_clk / 10 * 76) - 1; 325 high_count = (i2c_dev_clk / 10 * 26) / (i2c_clk / 10 * 76) - 8; 326 low_reg = High_low_count; 327 high_reg = High_high_count; 328 } 329 330 // Minimum counts are 8 and 6 for low and high respectively. 331 332 _regs[low_reg] = low_count < 8 ? 8 : low_count; 333 _regs[high_reg] = high_count < 6 ? 6 : high_count; 334 335 // Data hold and setup times: 336 337 // Standard Fast High 338 // t{HD;DAT} 300ns 300ns 300ns 339 // t{SU;DAT} 250ns 100ns 50ns 340 341 // See: UM10204 "I2C-bus specification and user manual" 342 // Table 10: t{HD;DAT} and t{SU;DAT}, also note [3] 343 344 // T{delay} = (I2CSDAHD + 2) * T{I2C_DEV_CLK} 345 // I2CSDAHD = T{delay} / T{I2C_DEV_CLK} - 2 346 // I2CSDAHD = I2C_DEV_CLK * T{delay} - 2 347 348 // Since the device clock is in kHz (scaled down by 1000) and the times are 349 // given in ns (scaled up by 1000000000), a division of 1000000 is introduced. 350 351 hold_count = (i2c_dev_clk * 300) / 1000000 - 1; 352 353 _regs[I2c_sda_hold_time] = (_regs[I2c_sda_hold_time] & ~I2c_hold_mask) | 354 (hold_count < 0 ? 0 355 : (hold_count < (int) I2c_hold_mask ? (uint32_t) hold_count 356 : I2c_hold_mask)); 357 358 // I2C_SDASU is apparently not used in master mode. 359 360 // T{delay} = (I2CSDASU - 1) * T{I2C_DEV_CLK} 361 // I2CSDASU = T{delay} / T{I2C_DEV_CLK} + 1 362 // I2CSDASU = I2C_DEV_CLK * T{delay} + 1 363 364 if (i2c_clk <= 100) 365 setup_count = (i2c_dev_clk * 250) / 1000000 + 1; 366 else if (i2c_clk <= 400) 367 setup_count = (i2c_dev_clk * 100) / 1000000 + 1; 368 else 369 setup_count = (i2c_dev_clk * 50) / 1000000 + 1; 370 371 _regs[I2c_sda_setup_time] = (_regs[I2c_sda_setup_time] & ~I2c_setup_mask) | 372 (setup_count < I2c_setup_mask ? setup_count : I2c_setup_mask); 373 } 374 375 // Set the target address and enable transfer. 376 // NOTE: Only supporting 7-bit addresses currently. 377 378 void 379 I2c_x1600_channel::set_target(uint8_t address) 380 { 381 disable(); 382 set_frequency(); 383 _regs[I2c_target_address] = address & I2c_target_7bits; 384 init_parameters(); 385 enable(); 386 } 387 388 389 390 // Reset interrupt flags upon certain conditions. 391 392 void 393 I2c_x1600_channel::reset_flags() 394 { 395 volatile uint32_t r; 396 397 _regs[Int_mask] = 0; 398 399 // Read from the register to clear interrupts. 400 401 r = _regs[Int_combined_clear]; 402 (void) r; 403 } 404 405 // Initialise interrupt flags and queue thresholds for reading and writing. 406 407 void 408 I2c_x1600_channel::init_parameters() 409 { 410 // Handle read queue conditions for data, write queue conditions for commands. 411 412 reset_flags(); 413 414 _regs[Tx_fifo_thold] = 0; // write when 0 in queue 415 } 416 417 418 419 // Return whether the device is active. 420 421 int 422 I2c_x1600_channel::active() 423 { 424 return _regs[I2c_status] & I2c_status_master_act; 425 } 426 427 // Return whether data is available to receive. 428 429 int 430 I2c_x1600_channel::have_input() 431 { 432 return _regs[I2c_status] & I2c_status_rx_nempty; 433 } 434 435 // Return whether data is queued for sending. 436 437 int 438 I2c_x1600_channel::have_output() 439 { 440 return !(_regs[I2c_status] & I2c_status_tx_empty); 441 } 442 443 // Return whether data can be queued for sending. 444 445 int 446 I2c_x1600_channel::can_send() 447 { 448 return _regs[I2c_status] & I2c_status_tx_nfull; 449 } 450 451 // Return whether a receive operation has failed. 452 453 int 454 I2c_x1600_channel::read_failed() 455 { 456 return _regs[Int_status] & Int_rx_of; 457 } 458 459 // Return whether a send operation has failed. 460 461 int 462 I2c_x1600_channel::write_failed() 463 { 464 return _regs[Int_status] & Int_tx_abort; 465 } 466 467 int 468 I2c_x1600_channel::read_done() 469 { 470 return _pos == _total; 471 } 472 473 int 474 I2c_x1600_channel::write_done() 475 { 476 return (_reqpos == _total) && !have_output(); 477 } 478 479 unsigned 480 I2c_x1600_channel::have_read() 481 { 482 return _pos; 483 } 484 485 unsigned 486 I2c_x1600_channel::have_written() 487 { 488 return _reqpos; 489 } 490 491 int 492 I2c_x1600_channel::failed() 493 { 494 return _fail; 495 } 496 497 498 499 // Send read commands for empty queue entries. 500 501 void 502 I2c_x1600_channel::queue_reads() 503 { 504 unsigned int remaining = _total - _reqpos; 505 unsigned int queued = _reqpos - _pos; 506 unsigned int can_queue = I2c_fifo_limit - queued; 507 508 // Keep the number of reads in progress below the length of the read queue. 509 510 if (!can_queue) 511 return; 512 513 // At most, only queue as many reads as are remaining. 514 515 if (remaining < can_queue) 516 can_queue = remaining; 517 518 // Queue read requests for any remaining queue entries. 519 520 while (can_queue && can_send()) 521 { 522 uint32_t stop = _stop && (_reqpos == _total - 1) ? I2c_command_stop : I2c_command_no_stop; 523 524 _regs[I2c_data_command] = I2c_command_read | stop; 525 _reqpos++; 526 can_queue--; 527 } 528 529 // Update the threshold to be notified of any reduced remaining amount. 530 531 set_read_threshold(); 532 } 533 534 // Send write commands for empty queue entries. 535 536 void 537 I2c_x1600_channel::queue_writes() 538 { 539 unsigned int remaining = _total - _reqpos; 540 unsigned int can_queue = I2c_fifo_limit; 541 542 if (remaining < can_queue) 543 can_queue = remaining; 544 545 // Queue write requests for any remaining queue entries. 546 547 while (can_queue && can_send()) 548 { 549 uint32_t stop = _stop && (_reqpos == _total - 1) ? I2c_command_stop : I2c_command_no_stop; 550 551 _regs[I2c_data_command] = I2c_command_write | _buf[_reqpos] | stop; 552 _reqpos++; 553 can_queue--; 554 } 555 } 556 557 // Store read command results from the queue. 558 559 void 560 I2c_x1600_channel::store_reads() 561 { 562 // Read any input and store it in the buffer. 563 564 while (have_input() && (_pos < _reqpos)) 565 { 566 _buf[_pos] = _regs[I2c_data_command] & 0xff; 567 _pos++; 568 } 569 } 570 571 void 572 I2c_x1600_channel::set_read_threshold() 573 { 574 unsigned int queued = _reqpos - _pos; 575 576 if (!queued) 577 return; 578 579 // Read all expected. 580 581 _regs[Rx_fifo_thold] = queued - 1; 582 } 583 584 // Read from the target device. 585 586 void 587 I2c_x1600_channel::start_read(uint8_t buf[], unsigned int total, int stop) 588 { 589 _buf = buf; 590 _total = total; 591 _pos = 0; 592 _reqpos = 0; 593 _fail = 0; 594 _stop = stop; 595 596 reset_flags(); 597 598 _regs[Int_mask] = Int_rx_full | // read condition (reading needed) 599 Int_rx_of | // abort condition 600 Int_tx_abort; // general abort condition 601 602 // Perform initial read requests. 603 604 read(); 605 } 606 607 void 608 I2c_x1600_channel::read() 609 { 610 // Test for the general transfer abort condition. 611 612 if (read_failed() || write_failed()) 613 { 614 _fail = 1; 615 _regs[Int_mask] = 0; 616 disable(); 617 enable(); 618 return; 619 } 620 621 if (_regs[Int_status] & Int_rx_full) 622 store_reads(); 623 624 // Always attempt to queue more read requests. 625 626 queue_reads(); 627 } 628 629 // Write to the target device. 630 631 void 632 I2c_x1600_channel::start_write(uint8_t buf[], unsigned int total, int stop) 633 { 634 _buf = buf; 635 _total = total; 636 _reqpos = 0; 637 _fail = 0; 638 _stop = stop; 639 640 reset_flags(); 641 642 // Enable interrupts for further writes. 643 644 _regs[Int_mask] = Int_tx_empty | // write condition (writing needed) 645 Int_tx_abort; // abort condition 646 647 // Perform initial writes. 648 649 write(); 650 } 651 652 void 653 I2c_x1600_channel::write() 654 { 655 if (write_failed()) 656 { 657 _fail = 1; 658 _regs[Int_mask] = 0; 659 disable(); 660 enable(); 661 return; 662 } 663 664 if (_regs[Int_status] & Int_tx_empty) 665 queue_writes(); 666 } 667 668 // Explicitly stop communication. 669 670 void 671 I2c_x1600_channel::stop() 672 { 673 } 674 675 676 677 // Initialise the I2C controller. 678 679 I2c_x1600_chip::I2c_x1600_chip(l4_addr_t start, l4_addr_t end, 680 Cpm_x1600_chip *cpm, 681 uint32_t frequency) 682 : _start(start), _end(end), _cpm(cpm), _frequency(frequency) 683 { 684 } 685 686 // Obtain a channel object. 687 688 I2c_x1600_channel * 689 I2c_x1600_chip::get_channel(uint8_t channel) 690 { 691 l4_addr_t block = _start + channel * I2c_block_offset; 692 enum Clock_identifiers clocks[] = {Clock_i2c0, Clock_i2c1}; 693 694 if (channel < 2) 695 return new I2c_x1600_channel(block, clocks[channel], _cpm, _frequency); 696 else 697 throw -L4_EINVAL; 698 } 699 700 701 702 // C language interface functions. 703 704 void *x1600_i2c_init(l4_addr_t start, l4_addr_t end, void *cpm, uint32_t frequency) 705 { 706 return (void *) new I2c_x1600_chip(start, end, static_cast<Cpm_x1600_chip *>(cpm), frequency); 707 } 708 709 void *x1600_i2c_get_channel(void *i2c, uint8_t channel) 710 { 711 return static_cast<I2c_x1600_chip *>(i2c)->get_channel(channel); 712 } 713 714 uint32_t x1600_i2c_get_frequency(void *i2c_channel) 715 { 716 return static_cast<I2c_x1600_channel *>(i2c_channel)->get_frequency(); 717 } 718 719 void x1600_i2c_set_target(void *i2c_channel, uint8_t addr) 720 { 721 static_cast<I2c_x1600_channel *>(i2c_channel)->set_target(addr); 722 } 723 724 void x1600_i2c_start_read(void *i2c_channel, uint8_t buf[], unsigned int total, 725 int stop) 726 { 727 static_cast<I2c_x1600_channel *>(i2c_channel)->start_read(buf, total, stop); 728 } 729 730 void x1600_i2c_read(void *i2c_channel) 731 { 732 static_cast<I2c_x1600_channel *>(i2c_channel)->read(); 733 } 734 735 void x1600_i2c_start_write(void *i2c_channel, uint8_t buf[], unsigned int total, 736 int stop) 737 { 738 static_cast<I2c_x1600_channel *>(i2c_channel)->start_write(buf, total, stop); 739 } 740 741 void x1600_i2c_write(void *i2c_channel) 742 { 743 static_cast<I2c_x1600_channel *>(i2c_channel)->write(); 744 } 745 746 int x1600_i2c_read_done(void *i2c_channel) 747 { 748 return static_cast<I2c_x1600_channel *>(i2c_channel)->read_done(); 749 } 750 751 int x1600_i2c_write_done(void *i2c_channel) 752 { 753 return static_cast<I2c_x1600_channel *>(i2c_channel)->write_done(); 754 } 755 756 unsigned int x1600_i2c_have_read(void *i2c_channel) 757 { 758 return static_cast<I2c_x1600_channel *>(i2c_channel)->have_read(); 759 } 760 761 unsigned int x1600_i2c_have_written(void *i2c_channel) 762 { 763 return static_cast<I2c_x1600_channel *>(i2c_channel)->have_written(); 764 } 765 766 int x1600_i2c_failed(void *i2c_channel) 767 { 768 return static_cast<I2c_x1600_channel *>(i2c_channel)->failed(); 769 }