1 /* 2 * MSC (MMC/SD controller) peripheral support. 3 * 4 * Copyright (C) 2024 Paul Boddie <paul@boddie.org.uk> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 19 * Boston, MA 02110-1301, USA 20 */ 21 22 #include <l4/devices/hw_mmio_register_block.h> 23 #include <l4/sys/irq.h> 24 #include <l4/sys/rcv_endpoint.h> 25 #include <l4/util/util.h> 26 27 #include <systypes/thread.h> 28 29 #include <math.h> 30 #include <stdio.h> 31 32 #include "msc-defs.h" 33 #include "msc-generic.h" 34 35 36 37 // Command frame: 38 // byte: start (1), direction (1), command (6) 39 // 4 bytes: argument 40 // byte: CRC (7), end (1) 41 42 // IO_RW_DIRECT argument: 43 // Argument MSB to LSB: R/W (1), function number (3), read after write flag (1), 44 // stuff (1), register address (17), stuff (1), 45 // write data or stuff (8) 46 // 0x88000c08: W, function = 0, read after write, register address = 6 (CCCR), 47 // data = 8 (reset) 48 49 const uint32_t Io_rw_direct_reset = 0x88000c08; 50 51 // (IO_)SEND_OP_COND argument and default voltage range expected in R3, R4: 52 // Argument MSB to LSB: stuff (8), voltage range (16), reserved (8) 53 // 0x00ff8000: voltage range 2.7 - 3.6V 54 55 const uint32_t Ocr_default_voltage_range = 0x00ff8000; 56 57 // SEND_IF_COND argument and default voltage range expected in R7: 58 // Argument MSB to LSB: stuff (20), voltage supplied (4), check (8) 59 // 0x000001aa: voltage range 2.7 - 3.6V, check = 0b10101010 60 61 const uint32_t If_cond_default_voltage_range = 0x000001aa; 62 63 64 65 // Utilities. 66 67 static enum Command_data_control_bits 68 encode_bus_width(uint8_t width) 69 { 70 switch (width) 71 { 72 case 4: return Cdc_bus_width_4bit; 73 case 1: return Cdc_bus_width_1bit; 74 default: return Cdc_bus_width_1bit; 75 } 76 } 77 78 79 80 // Channel abstraction. 81 82 Msc_channel::Msc_channel(l4_addr_t msc_start, l4_addr_t addr, l4_cap_idx_t irq, 83 Cpm_chip *cpm, enum Clock_identifiers clock) 84 : _msc_start(msc_start), _irq(irq), _cpm(cpm), _clock(clock) 85 { 86 _regs = new Hw::Mmio_register_block<32>(addr); 87 } 88 89 Msc_channel::~Msc_channel() 90 { 91 } 92 93 // Utility methods. 94 // NOTE: Also defined in the CPM abstraction, should be consolidated. 95 96 uint32_t 97 Msc_channel::get_field(uint32_t reg, uint32_t mask, uint8_t shift) 98 { 99 return (_regs[reg] & (mask << shift)) >> shift; 100 } 101 102 void 103 Msc_channel::set_field(uint32_t reg, uint32_t mask, uint8_t shift, uint32_t value) 104 { 105 _regs[reg] = (_regs[reg] & (~(mask << shift))) | ((mask & value) << shift); 106 } 107 108 bool 109 Msc_channel::set_clock_frequency(uint64_t frequency) 110 { 111 uint64_t division = _cpm->get_frequency(_clock) / frequency; 112 double divider = ceil(log2(division)); 113 114 if ((divider < 0) || (divider > Clock_rate_field_mask)) 115 return false; 116 117 set_field(Msc_clock_rate, Clock_rate_field_mask, Clock_rate_field_shift, 118 (uint32_t) divider); 119 120 return true; 121 } 122 123 void 124 Msc_channel::reset() 125 { 126 _regs[Msc_control] = _regs[Msc_control] | Control_reset; 127 128 while (_regs[Msc_status] & Status_resetting); 129 } 130 131 void 132 Msc_channel::start_clock() 133 { 134 set_field(Msc_control, Control_clock_control_field_mask, 135 Control_clock_control_field_shift, Control_clock_control_start); 136 137 while (!(_regs[Msc_status] & Status_clock_enabled)); 138 } 139 140 void 141 Msc_channel::stop_clock() 142 { 143 set_field(Msc_control, Control_clock_control_field_mask, 144 Control_clock_control_field_shift, Control_clock_control_stop); 145 146 while (_regs[Msc_status] & Status_clock_enabled); 147 } 148 149 void 150 Msc_channel::ack_irq(uint32_t flags) 151 { 152 // Clear the flags by setting them. 153 154 _regs[Msc_interrupt_flag] = _regs[Msc_interrupt_flag] | flags; 155 } 156 157 void 158 Msc_channel::unmask_irq(uint32_t flags) 159 { 160 ack_irq(flags); 161 162 if (_regs[Msc_interrupt_mask] & flags) 163 _regs[Msc_interrupt_mask] = _regs[Msc_interrupt_mask] & ~flags; 164 } 165 166 bool 167 Msc_channel::have_dma_enable_in_command() 168 { 169 return false; 170 } 171 172 bool 173 Msc_channel::have_dma_selection() 174 { 175 return true; 176 } 177 178 bool 179 Msc_channel::command_will_write(uint8_t index) 180 { 181 // NOTE: Probably incomplete coverage. 182 183 switch (index) 184 { 185 case Command_write_dat_until_stop: return true; 186 case Command_write_block: return true; 187 case Command_write_multiple_block: return true; 188 case Command_program_cid: return true; 189 case Command_program_csd: return true; 190 case Command_lock_unlock: return true; 191 default: return false; 192 } 193 } 194 195 bool 196 Msc_channel::app_command_will_write(uint8_t index) 197 { 198 // NOTE: Probably incomplete coverage. 199 200 (void) index; 201 202 return false; 203 } 204 205 bool 206 Msc_channel::command_with_data(uint8_t index) 207 { 208 // NOTE: Probably incomplete coverage. 209 210 switch (index) 211 { 212 case Command_read_dat_until_stop: return true; 213 case Command_read_single_block: return true; 214 case Command_read_multiple_block: return true; 215 case Command_write_dat_until_stop: return true; 216 case Command_write_block: return true; 217 case Command_write_multiple_block: return true; 218 case Command_program_cid: return true; 219 case Command_program_csd: return true; 220 case Command_lock_unlock: return true; 221 default: return false; 222 } 223 } 224 225 bool 226 Msc_channel::app_command_with_data(uint8_t index) 227 { 228 // NOTE: Probably incomplete coverage. 229 230 switch (index) 231 { 232 case App_command_sd_status: return true; 233 case App_command_send_num_wr_blocks: return true; 234 case App_command_send_scr: return true; 235 default: return false; 236 } 237 } 238 239 bool 240 Msc_channel::command_uses_busy(uint8_t index) 241 { 242 // NOTE: Probably incomplete coverage. 243 244 switch (index) 245 { 246 case Command_select_deselect_card: return true; 247 case Command_stop_transmission: return true; 248 default: return false; 249 } 250 } 251 252 bool 253 Msc_channel::app_command_uses_busy(uint8_t index) 254 { 255 // NOTE: Probably incomplete coverage. 256 257 (void) index; 258 259 return false; 260 } 261 262 uint8_t 263 Msc_channel::get_response_format(uint8_t index) 264 { 265 // NOTE: Probably incomplete coverage. 266 267 switch (index) 268 { 269 // Common commands without response. 270 271 case Command_go_idle_state: return 0; 272 case Command_set_dsr: return 0; 273 case Command_go_inactive_state: return 0; 274 275 // Common commands with response. 276 277 case Command_send_op_cond: return 3; 278 case Command_all_send_cid: return 2; 279 case Command_send_csd: return 2; 280 case Command_send_cid: return 2; 281 282 // SDIO only. 283 284 case Command_io_send_op_cond: return 4; 285 case Command_io_rw_direct: return 5; 286 287 // SDMEM only. 288 289 case Command_send_relative_addr: return 6; 290 case Command_send_if_cond: return 7; 291 292 // All other commands. 293 294 default: return 1; 295 } 296 } 297 298 uint8_t 299 Msc_channel::get_app_response_format(uint8_t index) 300 { 301 // NOTE: Probably incomplete coverage. 302 303 switch (index) 304 { 305 // SDMEM only. 306 307 case App_command_sd_send_op_cond: return 3; 308 309 // All other commands. 310 311 default: return 1; 312 } 313 } 314 315 // Read a response directly from the FIFO. 316 317 void 318 Msc_channel::read_response(uint16_t *buffer, uint8_t units) 319 { 320 uint8_t unit = units; 321 322 while (unit > 0) 323 { 324 uint32_t data = _regs[Msc_response_fifo]; 325 326 // Ignore the upper byte of the last unit in small transfers since it is the 327 // lower byte from the previous unit not shifted out of the register. 328 329 unit--; 330 331 if ((unit == 0) && (units == 3)) 332 buffer[unit] = (data & 0xff) << 8; 333 else 334 buffer[unit] = data; 335 } 336 } 337 338 // Send an application-specific command. 339 340 bool 341 Msc_channel::send_app_command(uint8_t index, uint32_t arg) 342 { 343 if (!send_command(Command_app_cmd, _cards[_card].rca << 16)) 344 return false; 345 346 return send_command(index, arg, get_app_response_format(index), 347 app_command_with_data(index), 348 app_command_will_write(index), 349 app_command_uses_busy(index)); 350 } 351 352 // Send a common MMC/SD command. 353 354 bool 355 Msc_channel::send_command(uint8_t index, uint32_t arg) 356 { 357 return send_command(index, arg, get_response_format(index), 358 command_with_data(index), 359 command_will_write(index), 360 command_uses_busy(index)); 361 } 362 363 // Initiate a command having the given index and using the given argument, 364 // employing the specified response format and involving a data transfer if 365 // indicated. 366 367 bool 368 Msc_channel::send_command(uint8_t index, uint32_t arg, uint8_t response_format, 369 bool data, bool write, bool busy) 370 { 371 stop_clock(); 372 373 // Enable DMA for data transfers for JZ4780, X1600 and others that have a 374 // channel-level control selecting special or conventional DMA. 375 376 if (have_dma_selection()) 377 _regs[Msc_dma_control] = (data ? Dma_select_common_dma | Dma_enable : Dma_disable); 378 379 // Set the command index and argument. 380 381 _regs[Msc_command_index] = index; 382 _regs[Msc_command_argument] = arg; 383 384 // Configure the response format and data bus width. 385 386 set_field(Msc_command_data_control, Cdc_response_format_field_mask, 387 Cdc_response_format_field_shift, response_format); 388 389 // NOTE: May need to set the SD bus width. 390 391 set_field(Msc_command_data_control, Cdc_bus_width_field_mask, 392 Cdc_bus_width_field_shift, 393 encode_bus_width(_cards[_card].bus_width)); 394 395 set_field(Msc_command_data_control, Cdc_recv_fifo_level_field_mask, 396 Cdc_recv_fifo_level_field_shift, Cdc_fifo_level_16); 397 398 set_field(Msc_command_data_control, Cdc_trans_fifo_level_field_mask, 399 Cdc_trans_fifo_level_field_shift, Cdc_fifo_level_16); 400 401 // Set and clear control bits appropriate to the command. 402 403 _regs[Msc_command_data_control] = _regs[Msc_command_data_control] | 404 (busy ? Cdc_expect_busy : Cdc_do_not_expect_busy) | 405 (data ? Cdc_data_with_command : Cdc_no_data_with_command) | 406 (write ? Cdc_write_operation : Cdc_read_operation); 407 408 _regs[Msc_command_data_control] = _regs[Msc_command_data_control] & 409 ~((busy ? Cdc_do_not_expect_busy : Cdc_expect_busy) | 410 (data ? Cdc_no_data_with_command : Cdc_data_with_command) | 411 (write ? Cdc_read_operation : Cdc_write_operation) | 412 Cdc_stream_block | Cdc_init_sequence); 413 414 // Pre-JZ4780 SoCs enable DMA in the command/data register. 415 416 if (have_dma_enable_in_command()) 417 set_field(Msc_command_data_control, Cdc_dma_field_mask, Cdc_dma_field_shift, 418 data ? Cdc_dma_enable : Cdc_dma_disable); 419 420 // Unmask interrupts, start the clock, then initiate the command. 421 422 uint32_t flags = Int_end_command_response | Int_response_timeout; 423 424 unmask_irq(flags); 425 start_clock(); 426 427 _regs[Msc_control] = _regs[Msc_control] | Control_start_operation; 428 429 // Wait for command completion. 430 431 if (!wait_for_irq(flags)) 432 return false; 433 434 // Determine whether a timeout occurred. 435 436 bool have_response = !((_regs[Msc_interrupt_flag] & Int_response_timeout) || 437 (_regs[Msc_status] & Status_response_crc_error) || 438 (_regs[Msc_status] & Status_timeout_response)); 439 440 // Acknowledge the response interrupts and return the status. 441 442 ack_irq(flags); 443 return have_response; 444 } 445 446 // Wait indefinitely for an interrupt request, returning true if one was delivered. 447 448 bool 449 Msc_channel::wait_for_irq(uint32_t flags) 450 { 451 if (l4_error(l4_rcv_ep_bind_thread(_irq, get_current_thread(), 0))) 452 return false; 453 454 return !l4_error(l4_irq_receive(_irq, L4_IPC_NEVER)) && 455 (_regs[Msc_interrupt_flag] & flags); 456 } 457 458 // Wait up to the given timeout (in microseconds) for an interrupt request, 459 // returning true if one was delivered. 460 461 bool 462 Msc_channel::wait_for_irq(uint32_t flags, unsigned int timeout) 463 { 464 if (l4_error(l4_rcv_ep_bind_thread(_irq, get_current_thread(), 0))) 465 return false; 466 467 return !l4_error(l4_irq_receive(_irq, l4_timeout(L4_IPC_TIMEOUT_NEVER, 468 l4util_micros2l4to(timeout)))) && 469 (_regs[Msc_interrupt_flag] & flags); 470 } 471 472 473 474 // Check the voltage range of the SD card, potentially establishing that it is 475 // a high capacity card. Return false if the voltage range is incompatible. 476 477 bool 478 Msc_channel::check_sd() 479 { 480 struct R7 r7; 481 482 // Send an interface condition command. 483 // A card may not respond to this command. 484 485 if (!send_command(Command_send_if_cond, If_cond_default_voltage_range)) 486 return true; 487 488 read_response((uint16_t *) &r7, Response_size_R7); 489 490 // Reject any card not supporting the default voltage range. 491 492 if (r7.check_voltage.raw != If_cond_default_voltage_range) 493 return false; 494 495 return true; 496 } 497 498 // Check the voltage range of the SDIO card, inactivating it if incompatible. 499 500 void 501 Msc_channel::init_sdio() 502 { 503 struct R4 r4; 504 uint32_t ocr = 0; 505 506 // Reset any SDIO card or IO unit in a combined memory/IO card. 507 // A non-SDIO card may not respond to this command. 508 509 if (!send_command(Command_io_rw_direct, Io_rw_direct_reset)) 510 return; 511 512 // Attempt to assert the operating conditions. 513 514 do 515 { 516 // Obtain OCR (operating conditions register) values for any IO card. 517 // Without a response, the card may have inactivated itself due to voltage 518 // range incompatibility reasons. 519 520 if (!send_command(Command_io_send_op_cond, ocr)) 521 return; 522 523 read_response((uint16_t *) &r4, Response_size_R4); 524 525 // Finish if no IO functions provided. 526 // NOTE: Should only need to check this the first time. 527 528 if (r4.number_io_functions == 0) 529 return; 530 531 if (r4.ocr != Ocr_default_voltage_range) 532 { 533 ocr = Ocr_default_voltage_range; 534 continue; 535 } 536 } 537 while (!r4.ready); 538 } 539 540 void 541 Msc_channel::init_sdmem() 542 { 543 struct R3 r3; 544 545 // Incorporate the HCS bit into the OCR for SDMEM. 546 547 uint32_t ocr = Ocr_default_voltage_range | Ocr_high_capacity_storage; 548 549 do 550 { 551 if (!send_app_command(App_command_sd_send_op_cond, ocr)) 552 return; 553 554 read_response((uint16_t *) &r3, Response_size_R3); 555 556 if ((r3.ocr & Ocr_default_voltage_range) != Ocr_default_voltage_range) 557 continue; 558 } 559 while (!(r3.ocr & Ocr_card_powered_up)); 560 561 // Set the OCR in the current card since we need the CCS indicator. 562 563 _cards[_num_cards].ocr = r3.ocr; 564 } 565 566 void 567 Msc_channel::init_mmc() 568 { 569 // Obtain OCR (operating conditions register) values for each card using 570 // send_op_cond command variants without argument, or assert operating 571 // conditions with argument to avoid handling card responses. Where responses 572 // are solicited, the host must determine a suitable argument and reissue the 573 // command. 574 575 struct R3 r3; 576 uint32_t ocr = 0; 577 578 do 579 { 580 if (!send_command(Command_send_op_cond, ocr)) 581 return; 582 583 read_response((uint16_t *) &r3, Response_size_R3); 584 585 if (r3.ocr != Ocr_default_voltage_range) 586 { 587 ocr = Ocr_default_voltage_range; 588 continue; 589 } 590 } 591 while (!(r3.ocr & Ocr_card_powered_up)); 592 } 593 594 void 595 Msc_channel::identify_cards() 596 { 597 struct R2 r2; 598 struct R6 r6; 599 600 while (send_command(Command_all_send_cid, 0)) 601 { 602 read_response((uint16_t *) &r2, Response_size_R2); 603 604 _cards[_num_cards].cid = r2.payload.cid; 605 606 printf("card: %d\n", _num_cards); 607 printf("date: %d %d\n", r2.payload.cid.month, r2.payload.cid.year); 608 printf("serial: %d\n", r2.payload.cid.serial); 609 printf("revision: %d\n", r2.payload.cid.revision); 610 printf("name: %c%c%c%c%c\n", r2.payload.cid.name[4], r2.payload.cid.name[3], 611 r2.payload.cid.name[2], r2.payload.cid.name[1], 612 r2.payload.cid.name[0]); 613 printf("oem: %d\n", r2.payload.cid.oem); 614 printf("manufacturer: %d\n", r2.payload.cid.manufacturer); 615 616 // Try and obtain a card-issued address. 617 618 if (send_command(Command_send_relative_addr, 0)) 619 { 620 read_response((uint16_t *) &r6, Response_size_R6); 621 _cards[_num_cards].rca = r6.rca; 622 } 623 624 // Try and assign an address. 625 // Employ 1-based relative addressing. 626 627 else if (send_command(Command_set_relative_addr, _num_cards + 1)) 628 _cards[_num_cards].rca = _num_cards + 1; 629 630 // Otherwise, stop identification. 631 632 else 633 return; 634 635 // Set the default bus width to be determined. 636 637 _cards[_num_cards].bus_width = 0; 638 639 _num_cards++; 640 } 641 } 642 643 void 644 Msc_channel::query_cards() 645 { 646 struct R2 r2; 647 uint8_t card; 648 649 for (card = 0; card < _num_cards; card++) 650 { 651 // Employ 1-based relative addressing. 652 653 if (!send_command(Command_send_csd, _cards[card].rca << 16)) 654 continue; 655 656 read_response((uint16_t *) &r2, Response_size_R2); 657 658 _cards[card].csd = r2.payload.csd; 659 660 struct CSD *csd = &_cards[card].csd; 661 662 printf("card: %d\n", card); 663 printf("csd: %d\n", csd->csd); 664 printf("copy: %s\n", csd->copy ? "copied" : "original"); 665 printf("card command classes: %03x\n", csd->card_command_classes); 666 printf("device (size multiplier): %d %d\n", csd->device_size + 1, 667 1 << (csd->device_size_multiplier + 2)); 668 printf("device size: %d\n", (1 << csd->read_blocklen) * 669 (csd->device_size + 1) * 670 (1 << (csd->device_size_multiplier + 2))); 671 printf("transfer speed: %d MHz\n", csd->tran_speed == 0x32 ? 25 : 50); 672 printf("format group: %d %d\n", csd->format, r2.payload.csd.format_group); 673 printf("write time factor: %d\n", 1 << csd->write_time_factor); 674 printf("write protect (temp perm): %s %s\n", csd->temp_write_prot ? "yes" : "no", 675 csd->perm_write_prot ? "yes" : "no"); 676 printf("write protect group (enable size): %s %d\n", csd->write_prot_group_enable ? "yes" : "no", 677 csd->write_prot_group_size + 1); 678 printf("write block (partial length): %s %d\n", csd->write_block_partial ? "yes" : "no", 679 1 << csd->write_blocklen); 680 printf("read block (partial length): %s %d\n", csd->read_block_partial ? "yes" : "no", 681 1 << csd->read_blocklen); 682 printf("erase: sector single: %d %s\n", csd->erase_sector_size + 1, 683 csd->erase_single_block_enable ? "yes" : "no"); 684 printf("misalign: read write: %s %s\n", csd->read_block_misalign ? "yes" : "no", 685 csd->write_block_misalign ? "yes" : "no"); 686 printf("max read current (min max): %d %d\n", csd->max_read_current_min, 687 csd->max_read_current_max); 688 printf("max write current (min max): %d %d\n", csd->max_write_current_min, 689 csd->max_write_current_max); 690 printf("read access time (1 2): %d %d\n", csd->data_read_access_time_1, 691 csd->data_read_access_time_2); 692 printf("DSR: %s\n", csd->dsr_implemented ? "yes" : "no"); 693 printf("high capacity: %s\n", _cards[card].ocr & Ocr_high_capacity_storage ? "yes" : "no"); 694 } 695 } 696 697 698 699 // Enable the controller and identify cards. 700 701 void 702 Msc_channel::enable() 703 { 704 // NOTE: X1600 and other recent SoCs only. 705 706 _regs[Msc_low_power_mode] = _regs[Msc_low_power_mode] & ~Low_power_mode_enable; 707 708 stop_clock(); 709 reset(); 710 711 // Slow the clock for initialisation. 712 // NOTE: Should produce an error. 713 714 if (!set_clock_frequency(400000)) 715 return; 716 717 send_command(Command_go_idle_state, 0); 718 719 // Reset the number of SDMEM and MMC cards prior to identification. 720 721 _num_cards = 0; 722 723 if (check_sd()) 724 { 725 init_sdio(); 726 init_sdmem(); 727 identify_cards(); 728 } 729 730 init_mmc(); 731 identify_cards(); 732 query_cards(); 733 734 // Initially, no card is selected. 735 736 _card = -1; 737 } 738 739 // Obtain the card details. 740 741 struct msc_card * 742 Msc_channel::get_cards() 743 { 744 return _cards; 745 } 746 747 // Return the number of active cards. 748 749 uint8_t 750 Msc_channel::num_cards() 751 { 752 return _num_cards; 753 } 754 755 // Receive data from the selected card. 756 757 uint32_t 758 Msc_channel::recv_data(struct dma_region *region, uint32_t count) 759 { 760 if (count > region->size) 761 return 0; 762 763 uint32_t flags = Int_data_transfer_done; 764 765 unmask_irq(flags); 766 767 uint32_t to_transfer = transfer(_msc_start + Msc_recv_data_fifo, region->paddr, true, count); 768 769 wait_for_irq(flags); 770 ack_irq(flags); 771 772 if (!to_transfer || 773 (_regs[Msc_status] & Status_read_crc_error) || 774 (_regs[Msc_status] & Status_timeout_read)) 775 return 0; 776 777 return to_transfer; 778 } 779 780 // Send data to the selected card. 781 782 uint32_t 783 Msc_channel::send_data(struct dma_region *region, uint32_t count) 784 { 785 if (count > region->size) 786 return 0; 787 788 uint32_t flags = Int_data_transfer_done; 789 790 unmask_irq(flags); 791 792 uint32_t to_transfer = transfer(region->paddr, _msc_start + Msc_trans_data_fifo, false, count); 793 794 wait_for_irq(flags); 795 ack_irq(flags); 796 797 if (!to_transfer || 798 (_regs[Msc_status] & Status_write_crc_error_data) || 799 (_regs[Msc_status] & Status_write_crc_error_no_status)) 800 return 0; 801 802 return to_transfer; 803 } 804 805 // Read data from the indicated card into a memory region. 806 807 uint32_t 808 Msc_channel::read(uint8_t card, struct dma_region *region, 809 uint64_t address, uint64_t count) 810 { 811 uint32_t block_size = 1 << _cards[card].csd.read_blocklen; 812 813 // Obtain the block address from the byte address and the number of blocks 814 // from the byte count. 815 816 // NOTE: Rejecting addresses and counts that are not multiples of the block 817 // NOTE: size. Should produce an error. 818 819 if ((address % block_size) || (count % block_size)) 820 return 0; 821 822 return read_blocks(card, region, address / block_size, count / block_size); 823 } 824 825 // Read blocks from the indicated card into a memory region. 826 827 uint32_t 828 Msc_channel::read_blocks(uint8_t card, struct dma_region *region, 829 uint32_t block_address, uint32_t block_count) 830 { 831 uint32_t block_size = 1 << _cards[card].csd.read_blocklen; 832 struct R1 r1; 833 834 // Select the requested card. 835 836 if (_card != card) 837 { 838 // Choose an appropriate clock frequency for the card. 839 // NOTE: Should produce an error. 840 841 if (!set_clock_frequency(_cards[card].csd.tran_speed == 0x32 ? 842 25000000 : 50000000)) 843 return 0; 844 845 if (!send_command(Command_select_deselect_card, _cards[card].rca << 16)) 846 return 0; 847 848 read_response((uint16_t *) &r1, Response_size_R1); 849 850 if (r1.status & R1_status_error_mask) 851 return 0; 852 853 _card = card; 854 } 855 856 // NOTE: SMEM cards should allow bus width setting with the SCR register 857 // NOTE: describing the permitted values. 858 // NOTE: SDIO cards have their bus width set in CCCR via CMD52. 859 860 if (!_cards[card].bus_width) 861 { 862 if (send_app_command(App_command_set_bus_width, Bus_width_4bit)) 863 _cards[card].bus_width = 4; 864 else 865 _cards[card].bus_width = 1; 866 } 867 868 if (!send_command(Command_set_blocklen, block_size)) 869 return 0; 870 871 read_response((uint16_t *) &r1, Response_size_R1); 872 873 if (r1.status & R1_status_error_mask) 874 return 0; 875 876 // NOTE: Consider issuing a predefined block count command to any multiple 877 // NOTE: block operation, at least for cards that support it. 878 879 // Apply block count and size properties to the issued command. 880 881 _regs[Msc_block_count] = block_count; 882 _regs[Msc_block_length] = block_size; 883 884 // Where CCS = 0, byte addressing is used. Otherwise, block addressing is used. 885 886 uint32_t address; 887 888 if (_cards[card].ocr & Ocr_high_capacity_storage) 889 address = block_address; 890 else 891 address = block_address * block_size; 892 893 if (!send_command(block_count == 1 ? Command_read_single_block 894 : Command_read_multiple_block, address)) 895 return 0; 896 897 read_response((uint16_t *) &r1, Response_size_R1); 898 899 if (r1.status & R1_status_error_mask) 900 return 0; 901 902 // NOTE: Use Msc_block_success_count instead. 903 904 uint32_t transferred = recv_data(region, block_size * block_count); 905 906 if (block_count > 1) 907 send_command(Command_stop_transmission, 0); 908 909 return transferred; 910 } 911 912 913 914 // Peripheral abstraction. 915 916 Msc_chip::Msc_chip(l4_addr_t msc_start, l4_addr_t start, l4_addr_t end, 917 Cpm_chip *cpm) 918 : _msc_start(msc_start), _start(start), _end(end), _cpm(cpm) 919 { 920 }