1 /* 2 * Common clock functionality. 3 * 4 * Copyright (C) 2023 Paul Boddie <paul@boddie.org.uk> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 19 * Boston, MA 02110-1301, USA 20 */ 21 22 #pragma once 23 24 #ifdef __cplusplus 25 26 #include <l4/devices/clocks.h> 27 #include <l4/devices/hw_register_block.h> 28 #include <l4/sys/types.h> 29 #include <stdint.h> 30 31 /* Forward declaration. */ 32 33 class Clock_base; 34 35 36 37 /* Register access type. */ 38 39 class Cpm_regs 40 { 41 protected: 42 Hw::Register_block<32> _regs; 43 Clock_base **_clocks; 44 45 public: 46 explicit Cpm_regs(l4_addr_t addr, Clock_base *clocks[]); 47 48 // Utility methods. 49 50 uint32_t get_field(uint32_t reg, uint32_t mask, uint8_t shift); 51 void set_field(uint32_t reg, uint32_t mask, uint8_t shift, uint32_t value); 52 53 Clock_base *get_clock(int num); 54 }; 55 56 57 58 // Register field abstraction. 59 60 class Field 61 { 62 uint32_t reg; 63 uint32_t mask; 64 uint8_t bit; 65 bool defined; 66 uint32_t _asserted = 0, _deasserted = 0; 67 68 public: 69 explicit Field() 70 : defined(false) 71 { 72 } 73 74 explicit Field(uint32_t reg, uint32_t mask, uint32_t bit, 75 bool inverted = false) 76 : reg(reg), mask(mask), bit(bit), defined(true) 77 { 78 if (inverted) 79 _deasserted = mask; 80 else 81 _asserted = mask; 82 } 83 84 uint32_t get_field(Cpm_regs ®s); 85 void set_field(Cpm_regs ®s, uint32_t value); 86 87 uint32_t get_asserted() { return _asserted; } 88 uint32_t get_deasserted() { return _deasserted; } 89 90 bool is_defined() { return defined; } 91 uint32_t get_limit() { return mask; } 92 93 // Undefined field object. 94 95 static Field undefined; 96 }; 97 98 99 100 // Clock sources. 101 102 class Mux 103 { 104 int _num_inputs; 105 enum Clock_identifiers *_inputs, _input; 106 107 public: 108 explicit Mux(int num_inputs, enum Clock_identifiers inputs[]) 109 : _num_inputs(num_inputs), _inputs(inputs) 110 { 111 } 112 113 explicit Mux(enum Clock_identifiers input) 114 : _num_inputs(1), _inputs(&_input) 115 { 116 _input = input; 117 } 118 119 explicit Mux() 120 : _num_inputs(0), _inputs(NULL) 121 { 122 } 123 124 int get_number() { return _num_inputs; } 125 enum Clock_identifiers get_input(int num); 126 }; 127 128 129 130 // Controllable clock source. 131 132 class Source 133 { 134 Mux _inputs; 135 Field _source; 136 137 public: 138 explicit Source(Mux inputs, Field source) 139 : _inputs(inputs), _source(source) 140 { 141 } 142 143 explicit Source(Mux inputs) 144 : _inputs(inputs) 145 { 146 } 147 148 explicit Source() 149 { 150 } 151 152 int get_number() { return _inputs.get_number(); } 153 enum Clock_identifiers get_input(int num) { return _inputs.get_input(num); } 154 155 // Clock source. 156 157 uint8_t get_source(Cpm_regs ®s); 158 void set_source(Cpm_regs ®s, uint8_t source); 159 enum Clock_identifiers get_source_clock(Cpm_regs ®s); 160 void set_source_clock(Cpm_regs ®s, enum Clock_identifiers clock); 161 162 // Clock source frequency. 163 164 uint64_t get_frequency(Cpm_regs ®s); 165 }; 166 167 168 169 // Common clock control. 170 171 class Control_base 172 { 173 public: 174 virtual ~Control_base(); 175 176 virtual void change_disable(Cpm_regs ®s); 177 virtual void change_enable(Cpm_regs ®s); 178 179 virtual void wait_busy(Cpm_regs ®s) = 0; 180 virtual int have_clock(Cpm_regs ®s) = 0; 181 virtual void start_clock(Cpm_regs ®s) = 0; 182 virtual void stop_clock(Cpm_regs ®s) = 0; 183 }; 184 185 186 187 // Clock control. 188 189 class Control : public Control_base 190 { 191 Field _gate, _change_enable, _busy; 192 193 public: 194 explicit Control(Field gate, 195 Field change_enable = Field::undefined, 196 Field busy = Field::undefined) 197 : _gate(gate), _change_enable(change_enable), _busy(busy) 198 { 199 } 200 201 explicit Control() 202 : _gate(Field::undefined), _change_enable(Field::undefined), 203 _busy(Field::undefined) 204 { 205 } 206 207 // Clock control. 208 209 void change_disable(Cpm_regs ®s); 210 void change_enable(Cpm_regs ®s); 211 212 void wait_busy(Cpm_regs ®s); 213 int have_clock(Cpm_regs ®s); 214 void start_clock(Cpm_regs ®s); 215 void stop_clock(Cpm_regs ®s); 216 217 // Undefined control object. 218 219 static Control undefined; 220 }; 221 222 223 224 // PLL control. 225 226 class Control_pll : public Control_base 227 { 228 Field _enable, _stable, _bypass; 229 230 // Frequency change sequence state. 231 232 bool _enabled = false; 233 234 // PLL_specific control. 235 236 int have_pll(Cpm_regs ®s); 237 int pll_enabled(Cpm_regs ®s); 238 239 public: 240 explicit Control_pll(Field enable, Field stable, Field bypass) 241 : _enable(enable), _stable(stable), _bypass(bypass) 242 { 243 } 244 245 // Clock control. 246 247 int pll_bypassed(Cpm_regs ®s); 248 249 void pll_bypass(Cpm_regs ®s); 250 void pll_engage(Cpm_regs ®s); 251 252 void change_disable(Cpm_regs ®s); 253 void change_enable(Cpm_regs ®s); 254 255 void wait_busy(Cpm_regs ®s); 256 int have_clock(Cpm_regs ®s); 257 void start_clock(Cpm_regs ®s); 258 void stop_clock(Cpm_regs ®s); 259 }; 260 261 262 263 // Frequency transformation. 264 265 class Divider_base 266 { 267 public: 268 virtual ~Divider_base(); 269 270 // Output frequency. 271 272 virtual uint64_t get_frequency(Cpm_regs ®s, uint64_t source_frequency) = 0; 273 virtual int set_frequency(Cpm_regs ®s, uint64_t source_frequency, uint64_t frequency) = 0; 274 275 // Other operations. 276 277 virtual int get_parameters(Cpm_regs ®s, uint32_t parameters[]) = 0; 278 279 virtual int set_parameters(Cpm_regs ®s, int num_parameters, uint32_t parameters[]) = 0; 280 }; 281 282 283 284 // Simple divider for regular clocks. 285 286 class Divider : public Divider_base 287 { 288 Field _divider; 289 290 public: 291 explicit Divider(Field divider) 292 : _divider(divider) 293 { 294 } 295 296 explicit Divider() 297 : _divider(Field::undefined) 298 { 299 } 300 301 // Clock divider. 302 303 uint32_t get_divider(Cpm_regs ®s); 304 void set_divider(Cpm_regs ®s, uint32_t divider); 305 306 // Output frequency. 307 308 uint64_t get_frequency(Cpm_regs ®s, uint64_t source_frequency); 309 int set_frequency(Cpm_regs ®s, uint64_t source_frequency, uint64_t frequency); 310 311 // Other operations. 312 313 int get_parameters(Cpm_regs ®s, uint32_t parameters[]); 314 int set_parameters(Cpm_regs ®s, int num_parameters, uint32_t parameters[]); 315 }; 316 317 318 319 // Divider for PLLs. 320 321 class Divider_pll : public Divider_base 322 { 323 Field _multiplier, _input_divider, _output_divider0, _output_divider1; 324 double _intermediate_min, _intermediate_max; 325 bool _adjust_by_one; 326 327 // General frequency modifiers. 328 329 uint32_t get_multiplier(Cpm_regs ®s); 330 void set_multiplier(Cpm_regs ®s, uint32_t multiplier); 331 uint32_t get_input_divider(Cpm_regs ®s); 332 void set_input_divider(Cpm_regs ®s, uint32_t divider); 333 uint32_t get_output_divider(Cpm_regs ®s); 334 void set_output_divider(Cpm_regs ®s, uint32_t divider); 335 336 public: 337 338 // Double output divider constructor. 339 340 explicit Divider_pll(Field multiplier, Field input_divider, 341 Field output_divider0, Field output_divider1, 342 double intermediate_min, double intermediate_max, 343 bool adjust_by_one) 344 : _multiplier(multiplier), _input_divider(input_divider), 345 _output_divider0(output_divider0), _output_divider1(output_divider1), 346 _intermediate_min(intermediate_min), _intermediate_max(intermediate_max), 347 _adjust_by_one(adjust_by_one) 348 { 349 } 350 351 // Single output divider constructor. 352 353 explicit Divider_pll(Field multiplier, Field input_divider, 354 Field output_divider, 355 double intermediate_min, double intermediate_max, 356 bool adjust_by_one) 357 : _multiplier(multiplier), _input_divider(input_divider), 358 _output_divider0(output_divider), _output_divider1(Field::undefined), 359 _intermediate_min(intermediate_min), _intermediate_max(intermediate_max), 360 _adjust_by_one(adjust_by_one) 361 { 362 } 363 364 // Output frequency. 365 366 uint64_t get_frequency(Cpm_regs ®s, uint64_t source_frequency); 367 int set_frequency(Cpm_regs ®s, uint64_t source_frequency, uint64_t frequency); 368 369 // Other operations. 370 371 int get_parameters(Cpm_regs ®s, uint32_t parameters[]); 372 int set_parameters(Cpm_regs ®s, int num_parameters, uint32_t parameters[]); 373 }; 374 375 376 377 // Divider for I2S clocks. 378 379 class Divider_i2s : public Divider_base 380 { 381 Field _multiplier, _divider_N, _divider_D, _auto_N, _auto_D; 382 383 // General frequency modifiers. 384 385 uint32_t get_multiplier(Cpm_regs ®s); 386 uint32_t get_divider_N(Cpm_regs ®s); 387 uint32_t get_divider_D(Cpm_regs ®s); 388 389 public: 390 explicit Divider_i2s(Field multiplier, Field divider_N, Field divider_D, 391 Field auto_N, Field auto_D) 392 : _multiplier(multiplier), _divider_N(divider_N), _divider_D(divider_D), 393 _auto_N(auto_N), _auto_D(auto_D) 394 { 395 } 396 397 // Output frequency. 398 399 uint64_t get_frequency(Cpm_regs ®s, uint64_t source_frequency); 400 int set_frequency(Cpm_regs ®s, uint64_t source_frequency, uint64_t frequency); 401 402 // Other operations. 403 404 int get_parameters(Cpm_regs ®s, uint32_t parameters[]); 405 406 int set_parameters(Cpm_regs ®s, int num_parameters, uint32_t parameters[]); 407 }; 408 409 410 411 // Common clock abstraction. 412 413 class Clock_base 414 { 415 public: 416 virtual ~Clock_base(); 417 418 virtual const char *clock_type() { return "unset"; } 419 420 // Clock control. 421 422 virtual int have_clock(Cpm_regs ®s) = 0; 423 virtual void start_clock(Cpm_regs ®s) = 0; 424 virtual void stop_clock(Cpm_regs ®s) = 0; 425 426 // Output frequency. 427 428 virtual uint64_t get_frequency(Cpm_regs ®s) = 0; 429 }; 430 431 432 433 // Null (absent or undefined) clock abstraction. 434 435 class Clock_null : public Clock_base 436 { 437 public: 438 const char *clock_type() { return "null"; } 439 440 // Clock control. 441 442 int have_clock(Cpm_regs ®s); 443 void start_clock(Cpm_regs ®s); 444 void stop_clock(Cpm_regs ®s); 445 446 // Output frequency. 447 448 uint64_t get_frequency(Cpm_regs ®s); 449 }; 450 451 452 453 // Passive (root or input) clock without any source of its own. 454 455 class Clock_passive : public Clock_base 456 { 457 protected: 458 uint64_t _frequency; 459 460 public: 461 explicit Clock_passive(uint64_t frequency) 462 : _frequency(frequency) 463 { 464 } 465 466 const char *clock_type() { return "passive"; } 467 468 // Clock control. 469 470 virtual int have_clock(Cpm_regs ®s); 471 virtual void start_clock(Cpm_regs ®s); 472 virtual void stop_clock(Cpm_regs ®s); 473 474 // Output frequency. 475 476 uint64_t get_frequency(Cpm_regs ®s); 477 }; 478 479 480 481 class Clock_controlled : public Clock_base 482 { 483 protected: 484 virtual Control_base &_get_control() = 0; 485 486 public: 487 488 // Clock control. 489 490 virtual int have_clock(Cpm_regs ®s); 491 virtual void start_clock(Cpm_regs ®s); 492 virtual void stop_clock(Cpm_regs ®s); 493 }; 494 495 496 497 // An actively managed clock with source. 498 499 class Clock_active : public Clock_controlled 500 { 501 protected: 502 Source _source; 503 504 public: 505 explicit Clock_active(Source source) 506 : _source(source) 507 { 508 } 509 510 virtual ~Clock_active(); 511 512 // Clock source. 513 514 virtual uint8_t get_source(Cpm_regs ®s); 515 virtual void set_source(Cpm_regs ®s, uint8_t source); 516 enum Clock_identifiers get_source_clock(Cpm_regs ®s); 517 void set_source_clock(Cpm_regs ®s, enum Clock_identifiers clock); 518 519 // Clock source frequency. 520 521 virtual uint64_t get_source_frequency(Cpm_regs ®s); 522 523 // Output frequency. 524 525 virtual uint64_t get_frequency(Cpm_regs ®s); 526 }; 527 528 529 530 // Divided clock interface. 531 532 class Clock_divided_base : public Clock_active 533 { 534 protected: 535 virtual Divider_base &_get_divider() = 0; 536 537 public: 538 explicit Clock_divided_base(Source source) 539 : Clock_active(source) 540 { 541 } 542 543 virtual ~Clock_divided_base(); 544 545 virtual int get_parameters(Cpm_regs ®s, uint32_t parameters[]); 546 virtual int set_parameters(Cpm_regs ®s, int num_parameters, uint32_t parameters[]); 547 548 // Output frequency. 549 550 virtual uint64_t get_frequency(Cpm_regs ®s); 551 virtual int set_frequency(Cpm_regs ®s, uint64_t frequency); 552 }; 553 554 555 556 // PLL description. 557 558 class Pll : public Clock_divided_base 559 { 560 Control_pll _control; 561 Divider_pll _divider; 562 563 virtual Control_base &_get_control() { return _control; } 564 virtual Divider_base &_get_divider() { return _divider; } 565 566 public: 567 explicit Pll(Source source, Control_pll control, Divider_pll divider) 568 : Clock_divided_base(source), _control(control), _divider(divider) 569 { 570 } 571 572 virtual ~Pll(); 573 574 const char *clock_type() { return "pll"; } 575 576 // Output frequency. 577 578 uint64_t get_frequency(Cpm_regs ®s); 579 int set_frequency(Cpm_regs ®s, uint64_t frequency); 580 }; 581 582 583 584 // Plain clock description. 585 586 class Clock : public Clock_active 587 { 588 Control _control; 589 590 virtual Control_base &_get_control() { return _control; } 591 592 public: 593 explicit Clock(Source source, Control control) 594 : Clock_active(source), _control(control) 595 { 596 } 597 598 explicit Clock(Source source) 599 : Clock_active(source) 600 { 601 } 602 603 const char *clock_type() { return "clock"; } 604 }; 605 606 607 608 // Divided clock description. 609 610 class Clock_divided : public Clock_divided_base 611 { 612 Control _control; 613 Divider _divider; 614 615 virtual Control_base &_get_control() { return _control; } 616 virtual Divider_base &_get_divider() { return _divider; } 617 618 public: 619 explicit Clock_divided(Source source, Control control, Divider divider) 620 : Clock_divided_base(source), _control(control), _divider(divider) 621 { 622 } 623 624 explicit Clock_divided(Source source, Divider divider) 625 : Clock_divided_base(source), _control(Control::undefined), _divider(divider) 626 { 627 } 628 629 const char *clock_type() { return "divided"; } 630 }; 631 632 633 634 // I2S clock description. 635 636 class Clock_divided_i2s : public Clock_divided_base 637 { 638 Control _control; 639 Divider_i2s _divider; 640 641 virtual Control_base &_get_control() { return _control; } 642 virtual Divider_base &_get_divider() { return _divider; } 643 644 public: 645 explicit Clock_divided_i2s(Source source, Control control, Divider_i2s divider) 646 : Clock_divided_base(source), _control(control), _divider(divider) 647 { 648 } 649 650 const char *clock_type() { return "i2s"; } 651 }; 652 653 #endif /* __cplusplus */