1 /* 2 * Clock and power management. This exposes the combined functionality 3 * provided by the jz4780 and related SoCs. The power management 4 * functionality could be exposed using a separate driver. 5 * 6 * Copyright (C) 2017, 2018, 2020, 2021, 2023 Paul Boddie <paul@boddie.org.uk> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 21 * Boston, MA 02110-1301, USA 22 */ 23 24 #include <l4/devices/hw_mmio_register_block.h> 25 #include "cpm-jz4780.h" 26 27 28 29 // Register locations. 30 31 enum Regs : unsigned 32 { 33 Clock_control = 0x000, // CPCCR 34 Low_power_control = 0x004, // LCR 35 Clock_gate0 = 0x020, // CLKGR0 36 Clock_gate1 = 0x028, // CLKGR1 37 Sleep_control = 0x024, // OPCR (oscillator and power control) 38 Clock_status = 0x0d4, // CPCSR 39 40 Divider_bch = 0x0ac, // BCHCDR 41 Divider_cim = 0x07c, // CIMCDR 42 Divider_ddr = 0x02c, // DDRCDR 43 Divider_gpu = 0x088, // GPUCDR 44 Divider_hdmi = 0x08c, // HDMICDR 45 Divider_i2s0 = 0x060, // I2SCDR 46 Divider_i2s1 = 0x0a0, // I2S1CDR 47 Divider_lcd0 = 0x054, // LP0CDR 48 Divider_lcd1 = 0x064, // LP1CDR 49 Divider_msc0 = 0x068, // MSC0CDR 50 Divider_msc1 = 0x0a4, // MSC1CDR 51 Divider_msc2 = 0x0a8, // MSC2CDR 52 Divider_pcm = 0x084, // PCMCDR 53 Divider_ssi = 0x074, // SSICDR 54 Divider_uhc = 0x06c, // UHCCDR 55 Divider_vpu = 0x030, // VPUCDR 56 57 Cpm_interrupt = 0x0b0, // CPM_INTR 58 Cpm_interrupt_en = 0x0b4, // CPM_INTRE 59 Cpm_scratch = 0x034, // CPSPR 60 Cpm_scratch_prot = 0x038, // CPSPPR 61 62 Usb_param_control0 = 0x03c, // USBPCR 63 Usb_reset_detect = 0x040, // USBRDT 64 Usb_vbus_jitter = 0x044, // USBVBFIL 65 Usb_param_control1 = 0x048, // USBPCR1 66 67 Pll_control = 0x00c, // CPPCR 68 Pll_control_A = 0x010, // CPAPCR 69 Pll_control_M = 0x014, // CPMPCR 70 Pll_control_E = 0x018, // CPEPCR 71 Pll_control_V = 0x01c, // CPVPCR 72 }; 73 74 75 76 // Register field definitions. 77 78 static Field Clock_source_main (Clock_control, 3, 30), // SEL_SRC (output to SCLK_A) 79 Clock_source_cpu (Clock_control, 3, 28), // SEL_CPLL (output to CCLK) 80 Clock_source_hclock0 (Clock_control, 3, 26), // SEL_H0PLL (output to AHB0) 81 Clock_source_hclock2 (Clock_control, 3, 24), // SEL_H2PLL (output to AHB2) 82 Clock_source_bch (Divider_bch, 3, 30), // BPCS 83 Clock_source_cim (Divider_cim, 1, 31), // CIMPCS 84 Clock_source_ddr (Divider_ddr, 3, 30), // DCS 85 Clock_source_gpu (Divider_gpu, 3, 30), // GPCS 86 Clock_source_hdmi (Divider_hdmi, 3, 30), // HPCS 87 Clock_source_i2s0 (Divider_i2s0, 3, 30), // I2CS, I2PCS 88 Clock_source_i2s1 (Divider_i2s1, 3, 30), // I2CS, I2PCS 89 Clock_source_lcd0 (Divider_lcd0, 3, 30), // LPCS 90 Clock_source_lcd1 (Divider_lcd1, 3, 30), // LPCS 91 Clock_source_msc (Divider_msc0, 3, 30), // MPCS 92 Clock_source_pcm (Divider_pcm, 7, 29), // PCMS, PCMPCS 93 Clock_source_ssi (Divider_ssi, 3, 30), // SCS, SPCS 94 Clock_source_uhc (Divider_uhc, 3, 30), // UHCS 95 Clock_source_vpu (Divider_vpu, 3, 30), // VCS 96 97 Clock_busy_cpu (Clock_status, 1, 0), 98 Clock_busy_hclock0 (Clock_status, 1, 1), 99 Clock_busy_hclock2 (Clock_status, 1, 2), 100 Clock_busy_bch (Divider_bch, 1, 28), 101 Clock_busy_cim (Divider_cim, 1, 29), 102 Clock_busy_ddr (Divider_ddr, 1, 28), 103 Clock_busy_gpu (Divider_gpu, 1, 28), 104 Clock_busy_hdmi (Divider_hdmi, 1, 28), 105 Clock_busy_i2s0 (Divider_i2s0, 1, 28), 106 Clock_busy_i2s1 (Divider_i2s1, 1, 28), 107 Clock_busy_lcd0 (Divider_lcd0, 1, 27), 108 Clock_busy_lcd1 (Divider_lcd1, 1, 27), 109 Clock_busy_msc0 (Divider_msc0, 1, 28), 110 Clock_busy_msc1 (Divider_msc1, 1, 28), 111 Clock_busy_msc2 (Divider_msc2, 1, 28), 112 Clock_busy_pcm (Divider_pcm, 1, 27), 113 Clock_busy_ssi (Divider_ssi, 1, 28), 114 Clock_busy_uhc (Divider_uhc, 1, 28), 115 Clock_busy_vpu (Divider_vpu, 1, 28), 116 117 Clock_change_enable_cpu (Clock_control, 1, 22), 118 Clock_change_enable_ahb0 (Clock_control, 1, 21), 119 Clock_change_enable_ahb2 (Clock_control, 1, 20), 120 Clock_change_enable_bch (Divider_bch, 1, 29), 121 Clock_change_enable_cim (Divider_cim, 1, 30), 122 Clock_change_enable_ddr (Divider_ddr, 1, 29), 123 Clock_change_enable_gpu (Divider_gpu, 1, 29), 124 Clock_change_enable_hdmi (Divider_hdmi, 1, 29), 125 Clock_change_enable_i2s0 (Divider_i2s0, 1, 29), 126 Clock_change_enable_i2s1 (Divider_i2s1, 1, 29), 127 Clock_change_enable_lcd0 (Divider_lcd0, 1, 28), 128 Clock_change_enable_lcd1 (Divider_lcd1, 1, 28), 129 Clock_change_enable_msc0 (Divider_msc0, 1, 29), 130 Clock_change_enable_msc1 (Divider_msc1, 1, 29), 131 Clock_change_enable_msc2 (Divider_msc2, 1, 29), 132 Clock_change_enable_pcm (Divider_pcm, 1, 28), 133 Clock_change_enable_ssi (Divider_ssi, 1, 29), 134 Clock_change_enable_uhc (Divider_uhc, 1, 29), 135 Clock_change_enable_vpu (Divider_vpu, 1, 29), 136 137 Clock_divider_cpu (Clock_control, 0x0f, 0), // CDIV 138 Clock_divider_hclock0 (Clock_control, 0x0f, 8), // H0DIV (fast AHB peripherals) 139 Clock_divider_hclock2 (Clock_control, 0x0f, 12), // H2DIV (fast AHB peripherals) 140 Clock_divider_l2cache (Clock_control, 0x0f, 4), // L2CDIV 141 Clock_divider_pclock (Clock_control, 0x0f, 16), // PDIV (slow APB peripherals) 142 Clock_divider_bch (Divider_bch, 0x0f, 0), // BCHCDR 143 Clock_divider_cim (Divider_cim, 0xff, 0), // CIMCDR 144 Clock_divider_ddr (Divider_ddr, 0x0f, 0), // DDRCDR 145 Clock_divider_gpu (Divider_gpu, 0x0f, 0), // GPUCDR 146 Clock_divider_hdmi (Divider_hdmi, 0xff, 0), // HDMICDR 147 Clock_divider_i2s0 (Divider_i2s0, 0xff, 0), // I2SCDR 148 Clock_divider_i2s1 (Divider_i2s1, 0xff, 0), // I2SCDR 149 Clock_divider_lcd0 (Divider_lcd0, 0xff, 0), // LPCDR 150 Clock_divider_lcd1 (Divider_lcd1, 0xff, 0), // LPCDR 151 Clock_divider_msc0 (Divider_msc0, 0xff, 0), // MSC0CDR 152 Clock_divider_msc1 (Divider_msc1, 0xff, 0), // MSC1CDR 153 Clock_divider_msc2 (Divider_msc2, 0xff, 0), // MSC2CDR 154 Clock_divider_pcm (Divider_pcm, 0xff, 0), // PCMCDR 155 Clock_divider_ssi (Divider_ssi, 0xff, 0), // SSICDR 156 Clock_divider_uhc (Divider_uhc, 0xff, 0), // UHCCDR 157 Clock_divider_vpu (Divider_vpu, 0x0f, 0), // VPUCDR 158 159 Clock_gate_main (Clock_control, 1, 23, true), // GATE_SCLKA 160 Clock_gate_ddr (Clock_gate0, 3, 30, true), // DDR1, DDR0 161 Clock_gate_ipu (Clock_gate0, 1, 29, true), // IPU 162 Clock_gate_lcd (Clock_gate0, 3, 27, true), // LCD, TVE 163 Clock_gate_cim (Clock_gate0, 1, 26, true), // CIM 164 Clock_gate_i2c2 (Clock_gate0, 1, 25, true), // SMB2 165 Clock_gate_uhc (Clock_gate0, 1, 24, true), // UHC 166 Clock_gate_mac (Clock_gate0, 1, 23, true), // MAC 167 Clock_gate_gps (Clock_gate0, 1, 22, true), // GPS 168 Clock_gate_dma (Clock_gate0, 1, 21, true), // PDMA 169 //Clock_gate_ssi2 (Clock_gate0, 1, 20, true), // SSI2 170 Clock_gate_ssi1 (Clock_gate0, 1, 19, true), // SSI1 171 Clock_gate_uart3 (Clock_gate0, 1, 18, true), // UART3 172 Clock_gate_uart2 (Clock_gate0, 1, 17, true), // UART2 173 Clock_gate_uart1 (Clock_gate0, 1, 16, true), // UART1 174 Clock_gate_uart0 (Clock_gate0, 1, 15, true), // UART0 175 Clock_gate_sadc (Clock_gate0, 1, 14, true), // SADC 176 Clock_gate_kbc (Clock_gate0, 1, 13, true), // KBC 177 Clock_gate_msc2 (Clock_gate0, 1, 12, true), // MSC2 178 Clock_gate_msc1 (Clock_gate0, 1, 11, true), // MSC1 179 Clock_gate_owi (Clock_gate0, 1, 10, true), // OWI 180 Clock_gate_tssi0 (Clock_gate0, 1, 9, true), // TSSI0 181 Clock_gate_aic0 (Clock_gate0, 1, 8, true), // AIC0 182 Clock_gate_scc (Clock_gate0, 1, 7, true), // SCC 183 Clock_gate_i2c1 (Clock_gate0, 1, 6, true), // SMB1 184 Clock_gate_i2c0 (Clock_gate0, 1, 5, true), // SMB0 185 Clock_gate_ssi0 (Clock_gate0, 1, 4, true), // SSI0 186 Clock_gate_msc0 (Clock_gate0, 1, 3, true), // MSC0 187 Clock_gate_otg0 (Clock_gate0, 1, 2, true), // OTG0 188 Clock_gate_bch (Clock_gate0, 1, 1, true), // BCH 189 Clock_gate_nemc (Clock_gate0, 1, 0, true), // NEMC 190 Clock_gate_p1 (Clock_gate1, 1, 15, true), // P1 191 Clock_gate_x2d (Clock_gate1, 1, 14, true), // X2D 192 Clock_gate_des (Clock_gate1, 1, 13, true), // DES 193 Clock_gate_i2c4 (Clock_gate1, 1, 12, true), // SMB4 194 Clock_gate_ahb_mon (Clock_gate1, 1, 11, true), // AHB_MON 195 Clock_gate_uart4 (Clock_gate1, 1, 10, true), // UART4 196 Clock_gate_hdmi (Clock_gate1, 1, 9, true), // HDMI 197 Clock_gate_otg1 (Clock_gate1, 1, 8, true), // OTG1 198 Clock_gate_gpvlc (Clock_gate1, 1, 7, true), // GPVLC 199 Clock_gate_aic1 (Clock_gate1, 1, 6, true), // AIC1 200 Clock_gate_compress (Clock_gate1, 1, 5, true), // COMPRESS 201 Clock_gate_gpu (Clock_gate1, 1, 4, true), // GPU 202 Clock_gate_pcm (Clock_gate1, 1, 3, true), // PCM 203 Clock_gate_vpu (Clock_gate1, 1, 2, true), // VPU 204 Clock_gate_tssi1 (Clock_gate1, 1, 1, true), // TSSI1 205 Clock_gate_i2c3 (Clock_gate1, 1, 0, true), // I2C3 206 207 Pll_enable_A (Pll_control_A, 1, 0), // APLLEN 208 Pll_enable_E (Pll_control_E, 1, 0), // EPLLEN 209 Pll_enable_M (Pll_control_M, 1, 0), // MPLLEN 210 Pll_enable_V (Pll_control_V, 1, 0), // VPLLEN 211 212 Pll_stable_A (Pll_control_A, 1, 4), // APLL_ON 213 Pll_stable_E (Pll_control_E, 1, 4), // EPLL_ON 214 Pll_stable_M (Pll_control_M, 1, 4), // MPLL_ON 215 Pll_stable_V (Pll_control_V, 1, 4), // VPLL_ON 216 217 Pll_bypass_A (Pll_control_A, 1, 1), // APLL_BP 218 Pll_bypass_E (Pll_control_E, 1, 1), // EPLL_BP 219 Pll_bypass_M (Pll_control_M, 1, 1), // MPLL_BP 220 Pll_bypass_V (Pll_control_V, 1, 1), // VPLL_BP 221 222 Pll_multiplier_A (Pll_control_A, 0x1fff, 19), // APLLM 223 Pll_multiplier_E (Pll_control_E, 0x1fff, 19), // EPLLM 224 Pll_multiplier_M (Pll_control_M, 0x1fff, 19), // MPLLM 225 Pll_multiplier_V (Pll_control_V, 0x1fff, 19), // VPLLM 226 227 Pll_input_division_A (Pll_control_A, 0x3f, 13), // APLLN 228 Pll_input_division_E (Pll_control_E, 0x3f, 13), // EPLLN 229 Pll_input_division_M (Pll_control_M, 0x3f, 13), // MPLLN 230 Pll_input_division_V (Pll_control_V, 0x3f, 13), // VPLLN 231 232 Pll_output_division_A (Pll_control_A, 0x0f, 9), // APLLOD 233 Pll_output_division_E (Pll_control_E, 0x0f, 9), // EPLLOD 234 Pll_output_division_M (Pll_control_M, 0x0f, 9), // MPLLOD 235 Pll_output_division_V (Pll_control_V, 0x0f, 9); // VPLLOD 236 237 238 239 // Multiplexer instances. 240 241 #define Clocks(...) ((enum Clock_identifiers []) {__VA_ARGS__}) 242 243 static Mux mux_external (Clock_external), 244 245 // Clocks being propagated to others. 246 247 mux_clock_ssi (Clock_ssi), 248 mux_clock_msc (Clock_msc), 249 mux_hclock2 (Clock_hclock2), 250 mux_hclock2_pclock (Clock_hclock2_pclock), 251 mux_pclock (Clock_pclock), 252 253 // Main bus and peripheral clock sources. 254 255 mux_ahb2 (4, Clocks(Clock_none, Clock_main, Clock_pll_M, Clock_rtc)), 256 mux_core (4, Clocks(Clock_none, Clock_main, Clock_pll_M, Clock_pll_E)), 257 mux_main (4, Clocks(Clock_none, Clock_pll_A, Clock_external, Clock_rtc)), 258 259 // Memory and device clock sources. 260 261 mux_cim (2, Clocks(Clock_main, Clock_pll_M)), 262 mux_dev (3, Clocks(Clock_none, Clock_main, Clock_pll_M)), 263 mux_lcd (3, Clocks(Clock_main, Clock_pll_M, Clock_pll_V)), 264 mux_usb (3, Clocks(Clock_main, Clock_pll_M, Clock_pll_E /* , OTG PHY */)), 265 266 // Clock selectors involving the external clock. 267 268 mux_i2s (4, Clocks(Clock_external, Clock_external, Clock_main, Clock_pll_E)), 269 mux_pcm (8, Clocks(Clock_external, Clock_external, Clock_external, Clock_external, 270 Clock_main, Clock_pll_M, Clock_pll_E, Clock_pll_V)), 271 mux_ssi (4, Clocks(Clock_external, Clock_external, Clock_main, Clock_pll_M)); 272 273 274 275 // Clock instances. 276 277 static Clock_null clock_none; 278 279 static Clock_passive clock_external(48000000), clock_rtc(32768); 280 281 282 283 // Note the use of extra parentheses due to the annoying C++ "most vexing parse" 284 // problem. See: https://en.wikipedia.org/wiki/Most_vexing_parse 285 286 static Clock clock_ahb_mon((Source(mux_external)), (Control(Clock_gate_ahb_mon))), 287 288 clock_compress((Source(mux_external)), (Control(Clock_gate_compress))), 289 290 clock_des((Source(mux_external)), (Control(Clock_gate_des))), 291 292 clock_dma((Source(mux_external)), (Control(Clock_gate_dma))), 293 294 clock_gps((Source(mux_external)), (Control(Clock_gate_gps))), 295 296 clock_gpvlc((Source(mux_external)), (Control(Clock_gate_gpvlc))), 297 298 clock_i2c0((Source(mux_pclock)), (Control(Clock_gate_i2c0))), 299 300 clock_i2c1((Source(mux_pclock)), (Control(Clock_gate_i2c1))), 301 302 clock_i2c2((Source(mux_pclock)), (Control(Clock_gate_i2c2))), 303 304 clock_i2c3((Source(mux_pclock)), (Control(Clock_gate_i2c3))), 305 306 clock_i2c4((Source(mux_pclock)), (Control(Clock_gate_i2c4))), 307 308 clock_i2s0(Source(mux_i2s, Clock_source_i2s0), Control(Clock_gate_aic0)), 309 310 clock_i2s1(Source(mux_i2s, Clock_source_i2s1), Control(Clock_gate_aic1)), 311 312 clock_ipu((Source(mux_external)), (Control(Clock_gate_ipu))), 313 314 clock_kbc((Source(mux_external)), (Control(Clock_gate_kbc))), 315 316 clock_lcd((Source(mux_external)), (Control(Clock_gate_lcd))), 317 318 clock_main(Source(mux_main, Clock_source_main), Control(Clock_gate_main)), 319 320 clock_mac((Source(mux_external)), (Control(Clock_gate_mac))), 321 322 clock_msc((Source(mux_dev, Clock_source_msc))), 323 324 clock_nemc((Source(mux_hclock2)), (Control(Clock_gate_nemc))), 325 326 clock_otg0((Source(mux_external)), (Control(Clock_gate_otg0))), 327 328 clock_otg1((Source(mux_external)), (Control(Clock_gate_otg1))), 329 330 clock_owi((Source(mux_external)), (Control(Clock_gate_owi))), 331 332 clock_sadc((Source(mux_external)), (Control(Clock_gate_sadc))), 333 334 clock_scc((Source(mux_external)), (Control(Clock_gate_scc))), 335 336 clock_tssi0((Source(mux_external)), (Control(Clock_gate_tssi0))), 337 338 clock_tssi1((Source(mux_external)), (Control(Clock_gate_tssi1))), 339 340 clock_uart0((Source(mux_external)), (Control(Clock_gate_uart0))), 341 342 clock_uart1((Source(mux_external)), (Control(Clock_gate_uart1))), 343 344 clock_uart2((Source(mux_external)), (Control(Clock_gate_uart2))), 345 346 clock_uart3((Source(mux_external)), (Control(Clock_gate_uart3))), 347 348 clock_uart4((Source(mux_external)), (Control(Clock_gate_uart4))), 349 350 clock_x2d((Source(mux_external)), (Control(Clock_gate_x2d))), 351 352 // Special parent clock for hclock2 and pclock. 353 354 clock_hclock2_pclock(Source(mux_ahb2, Clock_source_hclock2)), 355 356 // SSI channel clocks depending on a common parent divider. 357 358 clock_ssi0((Source(mux_clock_ssi)), Control(Clock_gate_ssi0)), 359 360 clock_ssi1((Source(mux_clock_ssi)), Control(Clock_gate_ssi1)); 361 362 static Clock_divided 363 clock_bch(Source(mux_core, Clock_source_bch), 364 Control(Clock_gate_bch, Clock_change_enable_bch, Clock_busy_bch), 365 Divider(Clock_divider_bch)), 366 367 clock_cim(Source(mux_cim, Clock_source_cim), 368 Control(Clock_gate_cim, Clock_change_enable_cim, Clock_busy_cim), 369 Divider(Clock_divider_cim)), 370 371 clock_cpu(Source(mux_core, Clock_source_cpu), 372 Control(Field::undefined, Clock_change_enable_cpu, Clock_busy_cpu), 373 Divider(Clock_divider_cpu)), 374 375 clock_ddr(Source(mux_dev, Clock_source_ddr), 376 Control(Clock_gate_ddr, Clock_change_enable_ddr, Clock_busy_ddr), 377 Divider(Clock_divider_ddr)), 378 379 clock_gpu(Source(mux_core, Clock_source_gpu), 380 Control(Clock_gate_gpu, Clock_change_enable_gpu, Clock_busy_gpu), 381 Divider(Clock_divider_gpu)), 382 383 clock_hclock0(Source(mux_core, Clock_source_hclock0), 384 Control(Field::undefined, Clock_change_enable_ahb0), 385 Divider(Clock_divider_hclock0)), 386 387 clock_hclock2(Source(mux_hclock2_pclock), 388 Control(Field::undefined, Clock_change_enable_ahb2), 389 Divider(Clock_divider_hclock2)), 390 391 clock_hdmi(Source(mux_lcd, Clock_source_hdmi), 392 Control(Clock_gate_hdmi, Clock_change_enable_hdmi, Clock_busy_hdmi), 393 Divider(Clock_divider_hdmi)), 394 395 clock_lcd_pixel0(Source(mux_lcd, Clock_source_lcd0), 396 Control(Clock_gate_lcd, Clock_change_enable_lcd0, Clock_busy_lcd0), 397 Divider(Clock_divider_lcd0)), 398 399 clock_lcd_pixel1(Source(mux_lcd, Clock_source_lcd1), 400 Control(Clock_gate_lcd, Clock_change_enable_lcd1, Clock_busy_lcd1), 401 Divider(Clock_divider_lcd1)), 402 403 clock_msc0(Source(mux_clock_msc), 404 Control(Clock_gate_msc0, Clock_change_enable_msc0, Clock_busy_msc0), 405 Divider(Clock_divider_msc0)), 406 407 clock_msc1(Source(mux_clock_msc), 408 Control(Clock_gate_msc1, Clock_change_enable_msc1, Clock_busy_msc1), 409 Divider(Clock_divider_msc1)), 410 411 clock_msc2(Source(mux_clock_msc), 412 Control(Clock_gate_msc2, Clock_change_enable_msc2, Clock_busy_msc2), 413 Divider(Clock_divider_msc2)), 414 415 clock_pcm(Source(mux_pcm, Clock_source_pcm), 416 Control(Clock_gate_pcm, Clock_change_enable_pcm, Clock_busy_pcm), 417 Divider(Clock_divider_pcm)), 418 419 clock_pclock(Source(mux_hclock2_pclock), 420 Control(Field::undefined, Clock_change_enable_ahb2), 421 Divider(Clock_divider_pclock)), 422 423 clock_ssi(Source(mux_ssi, Clock_source_ssi), 424 Control(Field::undefined, Clock_change_enable_ssi, Clock_busy_ssi), 425 Divider(Clock_divider_ssi)), 426 427 clock_uhc(Source(mux_usb, Clock_source_uhc), 428 Control(Clock_gate_uhc, Clock_change_enable_uhc, Clock_busy_uhc), 429 Divider(Clock_divider_uhc)), 430 431 clock_vpu(Source(mux_core, Clock_source_vpu), 432 Control(Clock_gate_vpu, Clock_change_enable_vpu, Clock_busy_vpu), 433 Divider(Clock_divider_vpu)); 434 435 const double jz4780_pll_intermediate_min = 300000000, 436 jz4780_pll_intermediate_max = 1500000000; 437 438 static Pll clock_pll_A(Source(mux_external), 439 Control_pll(Pll_enable_A, Pll_stable_A, Pll_bypass_A), 440 Divider_pll(Pll_multiplier_A, Pll_input_division_A, 441 Pll_output_division_A, 442 jz4780_pll_intermediate_min, jz4780_pll_intermediate_max, 443 true)), 444 445 clock_pll_E(Source(mux_external), 446 Control_pll(Pll_enable_E, Pll_stable_E, Pll_bypass_E), 447 Divider_pll(Pll_multiplier_E, Pll_input_division_E, 448 Pll_output_division_E, 449 jz4780_pll_intermediate_min, jz4780_pll_intermediate_max, 450 true)), 451 452 clock_pll_M(Source(mux_external), 453 Control_pll(Pll_enable_M, Pll_stable_M, Pll_bypass_M), 454 Divider_pll(Pll_multiplier_M, Pll_input_division_M, 455 Pll_output_division_M, 456 jz4780_pll_intermediate_min, jz4780_pll_intermediate_max, 457 true)), 458 459 clock_pll_V(Source(mux_external), 460 Control_pll(Pll_enable_V, Pll_stable_V, Pll_bypass_V), 461 Divider_pll(Pll_multiplier_V, Pll_input_division_V, 462 Pll_output_division_V, 463 jz4780_pll_intermediate_min, jz4780_pll_intermediate_max, 464 true)); 465 466 467 468 // Clock register. 469 470 static Clock_base *clocks[Clock_identifier_count] = { 471 &clock_none, // Clock_aic 472 &clock_none, // Clock_aic_bitclk 473 &clock_none, // Clock_aic_pclk 474 &clock_none, // Clock_can0 475 &clock_none, // Clock_can1 476 &clock_none, // Clock_cdbus 477 &clock_cim, 478 &clock_cpu, 479 &clock_ddr, 480 &clock_dma, 481 &clock_none, // Clock_emac 482 &clock_external, 483 &clock_hclock0, 484 &clock_hclock2, 485 &clock_hclock2_pclock, 486 &clock_hdmi, 487 &clock_i2c0, 488 &clock_i2c1, 489 &clock_i2c2, 490 &clock_i2c3, 491 &clock_i2c4, 492 &clock_i2s0, 493 &clock_none, // Clock_i2s0_rx 494 &clock_none, // Clock_i2s0_tx 495 &clock_i2s1, 496 &clock_none, // Clock_i2s1_rx 497 &clock_none, // Clock_i2s1_tx 498 &clock_none, // Clock_kbc 499 &clock_lcd, 500 &clock_lcd_pixel0, 501 &clock_lcd_pixel1, 502 &clock_mac, 503 &clock_main, 504 &clock_none, // Clock_mipi_csi 505 &clock_msc, 506 &clock_msc0, 507 &clock_msc1, 508 &clock_msc2, 509 &clock_none, // Clock_none 510 &clock_otg0, 511 &clock_otg1, 512 &clock_pclock, 513 &clock_pcm, 514 &clock_pll_A, 515 &clock_pll_E, 516 &clock_pll_M, 517 &clock_pll_V, 518 &clock_none, // Clock_pwm0 519 &clock_none, // Clock_pwm1 520 &clock_rtc, 521 &clock_scc, 522 &clock_none, // Clock_sfc 523 &clock_ssi, 524 &clock_ssi0, 525 &clock_ssi1, 526 &clock_none, // Clock_ssi2 527 &clock_none, // Clock_timer 528 &clock_uart0, 529 &clock_uart1, 530 &clock_uart2, 531 &clock_uart3, 532 &clock_uart4, 533 &clock_none, // Clock_udc 534 &clock_uhc, 535 &clock_none, // Clock_uprt 536 &clock_vpu, 537 }; 538 539 540 541 // Peripheral abstraction. 542 543 Cpm_jz4780_chip::Cpm_jz4780_chip(l4_addr_t addr) 544 : Cpm_chip(addr, clocks) 545 { 546 } 547 548 549 550 // C language interface functions. 551 552 void 553 *jz4780_cpm_init(l4_addr_t cpm_base) 554 { 555 return (void *) new Cpm_jz4780_chip(cpm_base); 556 } 557 558 const char * 559 jz4780_cpm_clock_type(void *cpm, enum Clock_identifiers clock) 560 { 561 return static_cast<Cpm_jz4780_chip *>(cpm)->clock_type(clock); 562 } 563 564 int 565 jz4780_cpm_have_clock(void *cpm, enum Clock_identifiers clock) 566 { 567 return static_cast<Cpm_jz4780_chip *>(cpm)->have_clock(clock); 568 } 569 570 void 571 jz4780_cpm_start_clock(void *cpm, enum Clock_identifiers clock) 572 { 573 static_cast<Cpm_jz4780_chip *>(cpm)->start_clock(clock); 574 } 575 576 void 577 jz4780_cpm_stop_clock(void *cpm, enum Clock_identifiers clock) 578 { 579 static_cast<Cpm_jz4780_chip *>(cpm)->stop_clock(clock); 580 } 581 582 int 583 jz4780_cpm_get_parameters(void *cpm, enum Clock_identifiers clock, uint32_t parameters[]) 584 { 585 return static_cast<Cpm_jz4780_chip *>(cpm)->get_parameters(clock, parameters); 586 } 587 588 int 589 jz4780_cpm_set_parameters(void *cpm, enum Clock_identifiers clock, int num_parameters, uint32_t parameters[]) 590 { 591 return static_cast<Cpm_jz4780_chip *>(cpm)->set_parameters(clock, num_parameters, parameters); 592 } 593 594 uint8_t 595 jz4780_cpm_get_source(void *cpm, enum Clock_identifiers clock) 596 { 597 return static_cast<Cpm_jz4780_chip *>(cpm)->get_source(clock); 598 } 599 600 void 601 jz4780_cpm_set_source(void *cpm, enum Clock_identifiers clock, uint8_t source) 602 { 603 static_cast<Cpm_jz4780_chip *>(cpm)->set_source(clock, source); 604 } 605 606 enum Clock_identifiers 607 jz4780_cpm_get_source_clock(void *cpm, enum Clock_identifiers clock) 608 { 609 return static_cast<Cpm_jz4780_chip *>(cpm)->get_source_clock(clock); 610 } 611 612 void 613 jz4780_cpm_set_source_clock(void *cpm, enum Clock_identifiers clock, enum Clock_identifiers source) 614 { 615 static_cast<Cpm_jz4780_chip *>(cpm)->set_source_clock(clock, source); 616 } 617 618 uint64_t 619 jz4780_cpm_get_source_frequency(void *cpm, enum Clock_identifiers clock) 620 { 621 return static_cast<Cpm_jz4780_chip *>(cpm)->get_source_frequency(clock); 622 } 623 624 uint64_t 625 jz4780_cpm_get_frequency(void *cpm, enum Clock_identifiers clock) 626 { 627 return static_cast<Cpm_jz4780_chip *>(cpm)->get_frequency(clock); 628 } 629 630 int 631 jz4780_cpm_set_frequency(void *cpm, enum Clock_identifiers clock, uint64_t frequency) 632 { 633 return static_cast<Cpm_jz4780_chip *>(cpm)->set_frequency(clock, frequency); 634 }