1 /* 2 * CPM (clock and power management) support for the JZ4740. 3 * 4 * Copyright (C) 2017, 2018, 2020, 2021, 2023 Paul Boddie <paul@boddie.org.uk> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 19 * Boston, MA 02110-1301, USA 20 */ 21 22 #pragma once 23 24 #include <l4/devices/cpm.h> 25 26 #include <l4/sys/types.h> 27 #include <stdint.h> 28 29 30 31 #ifdef __cplusplus 32 33 #include <l4/devices/hw_register_block.h> 34 35 /* A simple abstraction for accessing the CPM registers. 36 * A proper device could inherit from Hw::Device and use an 37 * Int_property for _exclk_freq. */ 38 39 class Cpm_jz4740_chip : public Cpm_chip 40 { 41 private: 42 Hw::Register_block<32> _regs; 43 uint32_t _exclk_freq; 44 45 // Utility methods. 46 47 uint8_t _get_divider(uint32_t reg, uint32_t mask, uint8_t shift); 48 49 // PLL status. 50 51 int have_pll(); 52 int pll_enabled(); 53 int pll_bypassed(); 54 55 // Clock control. 56 57 uint32_t get_clock_gate_value(enum Clock_identifiers clock); 58 59 public: 60 Cpm_jz4740_chip(l4_addr_t addr, uint32_t exclk_freq); 61 62 // PLL configuration. 63 64 uint16_t get_multiplier(); 65 uint8_t get_input_division(); 66 uint8_t get_output_division(); 67 68 // Divider configuration. 69 70 uint8_t get_cpu_divider(); 71 uint8_t get_hclock_divider(); 72 uint8_t get_pclock_divider(); 73 uint8_t get_memory_divider(); 74 uint8_t get_source_divider(); 75 uint16_t get_lcd_pixel_divider(); 76 77 void set_lcd_device_divider(uint8_t division); 78 void set_lcd_pixel_divider(uint16_t division); 79 80 // PLL frequency status. 81 82 uint32_t get_pll_frequency(); 83 uint32_t get_source_frequency(); 84 85 // Clock frequency status. 86 87 uint32_t get_cpu_frequency(); 88 uint32_t get_hclock_frequency(); 89 uint32_t get_pclock_frequency(); 90 uint32_t get_memory_frequency(); 91 92 // Clock configuration. 93 94 uint32_t get_frequency(enum Clock_identifiers clock); 95 void set_frequency(enum Clock_identifiers clock, uint32_t frequency); 96 97 int have_clock(enum Clock_identifiers clock); 98 void start_clock(enum Clock_identifiers clock); 99 void stop_clock(enum Clock_identifiers clock); 100 101 }; 102 103 #endif /* __cplusplus */ 104 105 106 107 /* C language interface. */ 108 109 EXTERN_C_BEGIN 110 111 void *jz4740_cpm_init(l4_addr_t cpm_base); 112 113 int jz4740_cpm_have_pll(void *cpm); 114 115 int jz4740_cpm_have_clock(void *cpm, enum Clock_identifiers clock); 116 void jz4740_cpm_start_clock(void *cpm, enum Clock_identifiers clock); 117 void jz4740_cpm_stop_clock(void *cpm, enum Clock_identifiers clock); 118 119 uint16_t jz4740_cpm_get_lcd_pixel_divider(void *cpm); 120 121 uint32_t jz4740_cpm_get_frequency(void *cpm, enum Clock_identifiers clock); 122 void jz4740_cpm_set_frequency(void *cpm, enum Clock_identifiers clock, uint32_t frequency); 123 124 uint32_t jz4740_cpm_get_cpu_frequency(void *cpm); 125 uint32_t jz4740_cpm_get_hclock_frequency(void *cpm); 126 uint32_t jz4740_cpm_get_source_frequency(void *cpm); 127 uint32_t jz4740_cpm_get_pclock_frequency(void *cpm); 128 uint32_t jz4740_cpm_get_memory_frequency(void *cpm); 129 130 EXTERN_C_END