/*  * Clock and power management. This exposes the combined functionality  * provided by the jz4740 and related SoCs. The power management  * functionality could be exposed using a separate driver.  *  * Copyright (C) 2017, 2018, 2021, 2023 Paul Boddie <paul@boddie.org.uk>  *  * This program is free software; you can redistribute it and/or  * modify it under the terms of the GNU General Public License as  * published by the Free Software Foundation; either version 2 of  * the License, or (at your option) any later version.  *  * This program is distributed in the hope that it will be useful,  * but WITHOUT ANY WARRANTY; without even the implied warranty of  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the  * GNU General Public License for more details.  *  * You should have received a copy of the GNU General Public License  * along with this program; if not, write to the Free Software  * Foundation, Inc., 51 Franklin Street, Fifth Floor,  * Boston, MA  02110-1301, USA  */  #include <l4/devices/hw_mmio_register_block.h> #include "cpm-jz4740.h"    enum Regs : unsigned {   Clock_control       = 0x000,  // CPCCR   Low_power_control   = 0x004,  // LCR   Pll_control         = 0x010,  // CPPCR   Clock_gate          = 0x020,  // CLKGR   Sleep_control       = 0x024,  // SCR   I2s_divider         = 0x060,  // I2SCDR   Lcd_divider         = 0x064,  // LPCDR   Msc_divider         = 0x068,  // MSCCDR   Uhc_divider         = 0x06c,  // UHCCDR   Ssi_divider         = 0x074,  // SSICDR };  enum Clock_bits : unsigned {   Clock_change_enable   = 22, // CE   Clock_pllout_source   = 21, // PCS   Clock_lcd_divider     = 16, // LCD   Clock_memory_divider  = 12, // MDIV   Clock_pclock_divider  = 8,  // PDIV (slow APB peripherals)   Clock_hclock_divider  = 4,  // HDIV (fast AHB peripherals)   Clock_cpu_divider     = 0,  // CDIV };  enum Pll_bits : unsigned {   Pll_multiplier        = 23, // PLLM   Pll_input_division    = 18, // PLLN   Pll_output_division   = 16, // PLLOD   Pll_stable            = 10, // PLLS   Pll_bypassed          = 9,  // PLLBP   Pll_enabled           = 8,  // PLLEN };  enum Clock_gate_bits : unsigned {   Clock_gate_lcd        = 10, // LCD   Clock_gate_timer      = 1,  // TCU };  enum Lcd_divider_bits : unsigned {   Lcd_divider_value     = 0, };    // If implemented as a Hw::Device, various properties would be // initialised in the constructor and obtained from the device tree // definitions.  Cpm_jz4740_chip::Cpm_jz4740_chip(l4_addr_t addr, uint32_t exclk_freq) : _exclk_freq(exclk_freq) {   _regs = new Hw::Mmio_register_block<32>(addr);    // add_cid("cpm");   // add_cid("cpm-jz4740");   // register_property("exclk_freq", &_exclk_freq); }  // Clock/timer control.  uint32_t Cpm_jz4740_chip::get_clock_gate_value(enum Clock_identifiers clock) {   switch (clock)   {      case Clock_lcd: return (1 << Clock_gate_lcd);     case Clock_timer: return (1 << Clock_gate_timer);     default: return 0;   } }  int Cpm_jz4740_chip::have_clock(enum Clock_identifiers clock) {   return !(_regs[Clock_gate] & get_clock_gate_value(clock)); }  void Cpm_jz4740_chip::start_clock(enum Clock_identifiers clock) {   _regs[Clock_gate] = _regs[Clock_gate] & ~get_clock_gate_value(clock); }  void Cpm_jz4740_chip::stop_clock(enum Clock_identifiers clock) {   _regs[Clock_gate] = _regs[Clock_gate] | get_clock_gate_value(clock); }  // PLL control.  // Return whether the PLL is stable.  int Cpm_jz4740_chip::have_pll() {   return _regs[Pll_control] & (1 << Pll_stable); }  int Cpm_jz4740_chip::pll_enabled() {   return _regs[Pll_control] & (1 << Pll_enabled); }  int Cpm_jz4740_chip::pll_bypassed() {   return _regs[Pll_control] & (1 << Pll_bypassed); }  // Feedback (9-bit) multiplier.  uint16_t Cpm_jz4740_chip::get_multiplier() {   return ((_regs[Pll_control] & (0x1ff << Pll_multiplier)) >> Pll_multiplier) + 2; }  // Input (5-bit) divider.  uint8_t Cpm_jz4740_chip::get_input_division() {   return ((_regs[Pll_control] & (0x1f << Pll_input_division)) >> Pll_input_division) + 2; }  // Output divider.  uint8_t Cpm_jz4740_chip::get_output_division() {   uint8_t od[4] = {1, 2, 2, 4};   return od[(_regs[Pll_control] & (0x03 << Pll_output_division)) >> Pll_output_division]; }  // General clock divider.  uint8_t Cpm_jz4740_chip::_get_divider(uint32_t reg, uint32_t mask, uint8_t shift) {   uint8_t cd[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};   uint8_t d = (_regs[reg] & mask) >> shift;   return (d < 10) ? cd[d] : 1; }  // CPU clock (CCLK) divider.  uint8_t Cpm_jz4740_chip::get_cpu_divider() {   return _get_divider(Clock_control, 0xf << Clock_cpu_divider, Clock_cpu_divider); }  // Fast peripheral clock (HCLK) divider.  uint8_t Cpm_jz4740_chip::get_hclock_divider() {   return _get_divider(Clock_control, 0xf << Clock_hclock_divider, Clock_hclock_divider); }  // Slow peripheral clock (PCLK) divider.  uint8_t Cpm_jz4740_chip::get_pclock_divider() {   return _get_divider(Clock_control, 0xf << Clock_pclock_divider, Clock_pclock_divider); }  // Memory clock (MCLK) divider.  uint8_t Cpm_jz4740_chip::get_memory_divider() {   return _get_divider(Clock_control, 0xf << Clock_memory_divider, Clock_memory_divider); }  // Clock source divider for MSC, I2S, LCD and USB.  uint8_t Cpm_jz4740_chip::get_source_divider() {   return _regs[Clock_control] & (1 << Clock_pllout_source) ? 1 : 2; }  // LCD device clock divider.  void Cpm_jz4740_chip::set_lcd_device_divider(uint8_t division) {   if (division == 0)     division = 1;   else if (division > 32)     division = 32;    _regs[Clock_control] = _regs[Clock_control] | (1 << Clock_change_enable);    _regs[Clock_control] = (_regs[Clock_control] & ~(0x1f << Clock_lcd_divider)) |                          ((division - 1) << Clock_lcd_divider);    _regs[Clock_control] = _regs[Clock_control] & ~(1 << Clock_change_enable); }  // LCD pixel clock divider.  uint16_t Cpm_jz4740_chip::get_lcd_pixel_divider() {   return (_regs[Lcd_divider] >> Lcd_divider_value) + 1; }  void Cpm_jz4740_chip::set_lcd_pixel_divider(uint16_t division) {   if (division == 0)     division = 1;   else if (division > 2048)     division = 2048;    _regs[Clock_control] = _regs[Clock_control] | (1 << Clock_change_enable);    _regs[Lcd_divider] = (_regs[Lcd_divider] & ~(0x7ff << Lcd_divider_value)) |                        ((division - 1) << Lcd_divider_value);    _regs[Clock_control] = _regs[Clock_control] & ~(1 << Clock_change_enable); }    uint32_t Cpm_jz4740_chip::get_frequency(enum Clock_identifiers clock) {   if (clock == Clock_lcd_pixel)     return get_source_frequency() / get_lcd_pixel_divider();    // NOTE: Consider a better error result.   return 0; }  void Cpm_jz4740_chip::set_frequency(enum Clock_identifiers clock, uint32_t frequency) {   uint32_t out = get_source_frequency();    switch (clock)   {     // Limit the device frequency to 150MHz.      case Clock_lcd:       if (frequency > 150000000)         frequency = 150000000;       set_lcd_device_divider(out / frequency);       break;      case Clock_lcd_pixel:       set_lcd_pixel_divider(out / frequency);       break;      default:       break;   } }    uint32_t Cpm_jz4740_chip::get_pll_frequency() {   // Test for PLL enable and not PLL bypass.    if (pll_enabled() && !pll_bypassed())     return (_exclk_freq * get_multiplier()) /            (get_input_division() * get_output_division());   else     return _exclk_freq; }  // Clock frequency for MSC, I2S, LCD and USB.  uint32_t Cpm_jz4740_chip::get_source_frequency() {   return get_pll_frequency() / get_source_divider(); }  // Clock frequency for the CPU.  uint32_t Cpm_jz4740_chip::get_cpu_frequency() {          return get_pll_frequency() / get_cpu_divider(); }  // Clock frequency for fast peripherals.  uint32_t Cpm_jz4740_chip::get_hclock_frequency() {   return get_pll_frequency() / get_hclock_divider(); }  // Clock frequency for slow peripherals.  uint32_t Cpm_jz4740_chip::get_pclock_frequency() {   return get_pll_frequency() / get_pclock_divider(); }  // Clock frequency for the memory.  uint32_t Cpm_jz4740_chip::get_memory_frequency() {   return get_pll_frequency() / get_memory_divider(); }    // C language interface functions.  void *jz4740_cpm_init(l4_addr_t cpm_base) {   /* Initialise the clock and power management peripheral with the      register memory region and a 12MHz EXCLK frequency. */    return (void *) new Cpm_jz4740_chip(cpm_base, 12000000); }  int jz4740_cpm_have_clock(void *cpm, enum Clock_identifiers clock) {   return static_cast<Cpm_jz4740_chip *>(cpm)->have_clock(clock); }  void jz4740_cpm_start_clock(void *cpm, enum Clock_identifiers clock) {   static_cast<Cpm_jz4740_chip *>(cpm)->start_clock(clock); }  void jz4740_cpm_stop_clock(void *cpm, enum Clock_identifiers clock) {   static_cast<Cpm_jz4740_chip *>(cpm)->stop_clock(clock); }  uint32_t jz4740_cpm_get_cpu_frequency(void *cpm) {          return static_cast<Cpm_jz4740_chip *>(cpm)->get_cpu_frequency(); }  uint32_t jz4740_cpm_get_hclock_frequency(void *cpm) {   return static_cast<Cpm_jz4740_chip *>(cpm)->get_hclock_frequency(); }  uint32_t jz4740_cpm_get_source_frequency(void *cpm) {   return static_cast<Cpm_jz4740_chip *>(cpm)->get_source_frequency(); }  uint32_t jz4740_cpm_get_pclock_frequency(void *cpm) {   return static_cast<Cpm_jz4740_chip *>(cpm)->get_pclock_frequency(); }  uint32_t jz4740_cpm_get_memory_frequency(void *cpm) {   return static_cast<Cpm_jz4740_chip *>(cpm)->get_memory_frequency(); }  uint16_t jz4740_cpm_get_lcd_pixel_divider(void *cpm) {   return static_cast<Cpm_jz4740_chip *>(cpm)->get_lcd_pixel_divider(); }  uint32_t jz4740_cpm_get_frequency(void *cpm, enum Clock_identifiers clock) {   return static_cast<Cpm_jz4740_chip *>(cpm)->get_frequency(clock); }  void jz4740_cpm_set_frequency(void *cpm, enum Clock_identifiers clock, uint32_t frequency) {   static_cast<Cpm_jz4740_chip *>(cpm)->set_frequency(clock, frequency); }