1 /* 2 * LCD configuration value definitions for the JZ4740 and related SoCs. 3 * 4 * Copyright (C) 2018, 2020 Paul Boddie <paul@boddie.org.uk> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 19 * Boston, MA 02110-1301, USA 20 */ 21 22 #pragma once 23 24 enum Jz4740_lcd_config_bits 25 { 26 Jz4740_lcd_config_lcd_pin = 31, /* LCDPIN (SLCD pin functions) */ 27 Jz4740_lcd_config_tv_pal_halfline = 30, /* JZ4780: TVEPEH */ 28 Jz4740_lcd_config_desc_8_word = 28, /* JZ4780: NEWDES */ 29 Jz4740_lcd_config_tv_enable = 26, /* JZ4780: TVEN */ 30 Jz4740_lcd_config_underrun_recover = 25, /* JZ4780: RECOVER */ 31 Jz4740_lcd_config_ps_disable = 23, /* PSM */ 32 Jz4740_lcd_config_cls_disable = 22, /* CLSM */ 33 Jz4740_lcd_config_spl_disable = 21, /* SPLM */ 34 Jz4740_lcd_config_rev_disable = 20, /* REVM */ 35 Jz4740_lcd_config_hsync_mod_disable = 19, /* HSYNM (hsync polarity choice) */ 36 Jz4740_lcd_config_pclock_mod_disable = 18, /* PCLKM (dot/pixel clock polarity choice) */ 37 Jz4740_lcd_config_data_inverse = 17, /* INVDAT (inverse output data) */ 38 Jz4740_lcd_config_sync_input = 16, /* SYNDIR (hsync/vsync direction) */ 39 Jz4740_lcd_config_ps_reset = 15, /* PSP */ 40 Jz4740_lcd_config_cls_reset = 14, /* CLSP */ 41 Jz4740_lcd_config_spl_reset = 13, /* SPLP */ 42 Jz4740_lcd_config_rev_reset = 12, /* REVP */ 43 Jz4740_lcd_config_hsync_active_low = 11, /* HSP (hsync polarity) */ 44 Jz4740_lcd_config_pclock_fall_edge = 10, /* PCP (dot/pixel clock polarity) */ 45 Jz4740_lcd_config_de_active_low = 9, /* DEP (data enable polarity) */ 46 Jz4740_lcd_config_vsync_fall_edge = 8, /* VSP (vsync polarity) */ 47 Jz4740_lcd_config_bpp = 6, /* 16/18/24bpp selection for generic TFT */ 48 Jz4740_lcd_config_stn_pins = 4, /* PDW (STN pins utilisation) */ 49 Jz4740_lcd_config_mode = 0, 50 }; 51 52 enum Jz4740_lcd_bpp_values 53 { 54 Jz4740_lcd_bpp_16 = 0 << Jz4740_lcd_config_bpp, 55 Jz4740_lcd_bpp_24 = 1 << Jz4740_lcd_config_bpp, /* JZ4780 */ 56 Jz4740_lcd_bpp_18 = 2 << Jz4740_lcd_config_bpp, 57 }; 58 59 enum Jz4740_lcd_modes 60 { 61 Jz4740_lcd_mode_tft_generic = 0, /* parallel 16/18/24-bit panel */ 62 Jz4740_lcd_mode_tft_sharp = 1, 63 Jz4740_lcd_mode_tft_casio = 2, 64 Jz4740_lcd_mode_tft_samsung = 3, 65 Jz4740_lcd_mode_ccir656_nonint = 4, /* non-interlaced (TV out) */ 66 Jz4740_lcd_mode_ccir656_int = 6, /* interlaced (TV out) */ 67 Jz4740_lcd_mode_stn_single_colour = 8, /* single == one panel */ 68 Jz4740_lcd_mode_stn_single_mono = 9, 69 Jz4740_lcd_mode_stn_dual_colour = 10, /* dual == two panels */ 70 Jz4740_lcd_mode_stn_dual_mono = 11, 71 Jz4740_lcd_mode_tft_serial = 12, /* serial 8-bit panel */ 72 Jz4740_lcd_mode_lcm = 13, /* JZ4780 */ 73 }; 74 75 enum Jz4740_lcd_config_values 76 { 77 Jz4740_lcd_desc_8_word = 1 << Jz4740_lcd_config_desc_8_word, 78 Jz4740_lcd_underrun_recover = 1 << Jz4740_lcd_config_underrun_recover, 79 Jz4740_lcd_de_positive = 0 << Jz4740_lcd_config_de_active_low, 80 Jz4740_lcd_de_negative = 1 << Jz4740_lcd_config_de_active_low, 81 Jz4740_lcd_pclock_positive = 0 << Jz4740_lcd_config_pclock_fall_edge, 82 Jz4740_lcd_pclock_negative = 1 << Jz4740_lcd_config_pclock_fall_edge, 83 Jz4740_lcd_hsync_positive = 0 << Jz4740_lcd_config_hsync_active_low, 84 Jz4740_lcd_hsync_negative = 1 << Jz4740_lcd_config_hsync_active_low, 85 Jz4740_lcd_vsync_positive = 0 << Jz4740_lcd_config_vsync_fall_edge, 86 Jz4740_lcd_vsync_negative = 1 << Jz4740_lcd_config_vsync_fall_edge, 87 Jz4740_lcd_ps_disabled = 1 << Jz4740_lcd_config_ps_disable, 88 Jz4740_lcd_cls_disabled = 1 << Jz4740_lcd_config_cls_disable, 89 Jz4740_lcd_spl_disabled = 1 << Jz4740_lcd_config_spl_disable, 90 Jz4740_lcd_rev_disabled = 1 << Jz4740_lcd_config_rev_disable, 91 };