1 /* 2 * Clock and power management. This exposes the combined functionality 3 * provided by the X1600 and related SoCs. The power management 4 * functionality could be exposed using a separate driver. 5 * 6 * Copyright (C) 2017, 2018, 2020, 2021, 2023 Paul Boddie <paul@boddie.org.uk> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 21 * Boston, MA 02110-1301, USA 22 */ 23 24 #include <l4/devices/hw_mmio_register_block.h> 25 #include "cpm-x1600.h" 26 27 28 29 // Register locations. 30 31 enum Regs : unsigned 32 { 33 Clock_control = 0x000, // CPCCR 34 Low_power_control = 0x004, // LCR 35 Clock_gate0 = 0x020, // CLKGR0 36 Clock_gate1 = 0x028, // CLKGR1 37 Sleep_control = 0x024, // OPCR (oscillator and power control) 38 Clock_status = 0x0d4, // CPCSR 39 40 Divider_can0 = 0x0a0, // CAN0CDR 41 Divider_can1 = 0x0a8, // CAN1CDR 42 Divider_cdbus = 0x0ac, // CDBUSCDR 43 Divider_cim = 0x078, // CIMCDR 44 Divider_ddr = 0x02c, // DDRCDR 45 Divider_mac = 0x054, // MACCDR 46 Divider0_i2s0 = 0x060, // I2S0CDR 47 Divider1_i2s0 = 0x070, // I2S0CDR1 48 Divider0_i2s1 = 0x07c, // I2S1CDR (from X2000 manual) 49 Divider1_i2s1 = 0x080, // I2S1CDR1 (from X2000 manual) 50 Divider_lcd = 0x064, // LPCDR 51 Divider_macphy0 = 0x0e4, // MPHY0C 52 Divider_msc0 = 0x068, // MSC0CDR 53 Divider_msc1 = 0x0a4, // MSC1CDR 54 Divider_pwm = 0x06c, // PWMCDR 55 Divider_sfc = 0x074, // SFCCDR 56 Divider_ssi = 0x05c, // SSICDR 57 58 Cpm_interrupt = 0x0b0, // CPM_INTR 59 Cpm_interrupt_en = 0x0b4, // CPM_INTRE 60 Cpm_swi = 0x0bc, // CPM_SFTINT 61 Cpm_scratch = 0x034, // CPSPR 62 Cpm_scratch_prot = 0x038, // CPSPPR 63 64 Gate_ddr = 0x0d0, // DRCG 65 66 Usb_param_control0 = 0x03c, // USBPCR 67 Usb_reset_detect = 0x040, // USBRDT 68 Usb_vbus_jitter = 0x044, // USBVBFIL 69 Usb_param_control1 = 0x048, // USBPCR1 70 71 Pll_control = 0x00c, // CPPCR 72 Pll_control_A = 0x010, // CPAPCR 73 Pll_control_M = 0x014, // CPMPCR 74 Pll_control_E = 0x018, // CPEPCR 75 Pll_fraction_A = 0x084, // CPAPACR 76 Pll_fraction_M = 0x088, // CPMPACR 77 Pll_fraction_E = 0x08c, // CPEPACR 78 }; 79 80 81 82 // Register field definitions. 83 84 static Field Clock_source_main (Clock_control, 3, 30), // SEL_SRC (output to SCLK_A) 85 Clock_source_cpu (Clock_control, 3, 28), // SEL_CPLL (output to CCLK) 86 Clock_source_hclock0 (Clock_control, 3, 26), // SEL_H0PLL (output to AHB0) 87 Clock_source_hclock2 (Clock_control, 3, 24), // SEL_H2PLL (output to AHB2) 88 Clock_source_can0 (Divider_can0, 3, 30), // CA0CS 89 Clock_source_can1 (Divider_can1, 3, 30), // CA1CS 90 Clock_source_cdbus (Divider_cdbus, 3, 30), // CDCS 91 Clock_source_cim (Divider_cim, 3, 30), // CIMPCS 92 Clock_source_ddr (Divider_ddr, 3, 30), // DCS 93 Clock_source_i2s0 (Divider0_i2s0, 1, 30), // I2PCS 94 Clock_source_i2s1 (Divider0_i2s1, 1, 30), // I2PCS 95 Clock_source_lcd (Divider_lcd, 3, 30), // LPCS 96 Clock_source_mac (Divider_mac, 3, 30), // MACPCS 97 Clock_source_msc0 (Divider_msc0, 3, 30), // MPCS 98 Clock_source_msc1 (Divider_msc1, 3, 30), // MPCS 99 Clock_source_pwm (Divider_pwm, 3, 30), // PWMPCS 100 Clock_source_sfc (Divider_sfc, 3, 30), // SFCS 101 Clock_source_ssi (Divider_ssi, 3, 30), // SPCS 102 103 Clock_busy_cpu (Clock_status, 1, 0), 104 Clock_busy_hclock0 (Clock_status, 1, 1), 105 Clock_busy_hclock2 (Clock_status, 1, 2), 106 Clock_busy_ddr (Divider_ddr, 1, 28), 107 Clock_busy_mac (Divider_mac, 1, 28), 108 Clock_busy_lcd (Divider_lcd, 1, 28), 109 Clock_busy_msc0 (Divider_msc0, 1, 28), 110 Clock_busy_msc1 (Divider_msc1, 1, 28), 111 Clock_busy_sfc (Divider_sfc, 1, 28), 112 Clock_busy_ssi (Divider_ssi, 1, 28), 113 Clock_busy_cim (Divider_cim, 1, 28), 114 Clock_busy_pwm (Divider_pwm, 1, 28), 115 Clock_busy_can0 (Divider_can0, 1, 28), 116 Clock_busy_can1 (Divider_can1, 1, 28), 117 Clock_busy_cdbus (Divider_cdbus, 1, 28), 118 119 Clock_change_enable_cpu (Clock_control, 1, 22), 120 Clock_change_enable_ahb0 (Clock_control, 1, 21), 121 Clock_change_enable_ahb2 (Clock_control, 1, 20), 122 Clock_change_enable_ddr (Divider_ddr, 1, 29), 123 Clock_change_enable_mac (Divider_mac, 1, 29), 124 Clock_gate_i2s0 (Divider0_i2s0, 1, 29), // CE_I2S is gate, not change enable 125 Clock_gate_i2s1 (Divider0_i2s1, 1, 29), // CE_I2S is gate, not change enable 126 Clock_change_enable_lcd (Divider_lcd, 1, 29), 127 Clock_change_enable_msc0 (Divider_msc0, 1, 29), 128 Clock_change_enable_msc1 (Divider_msc1, 1, 29), 129 Clock_change_enable_sfc (Divider_sfc, 1, 29), 130 Clock_change_enable_ssi (Divider_ssi, 1, 29), 131 Clock_change_enable_cim (Divider_cim, 1, 29), 132 Clock_change_enable_pwm (Divider_pwm, 1, 29), 133 Clock_change_enable_can0 (Divider_can0, 1, 29), 134 Clock_change_enable_can1 (Divider_can1, 1, 29), 135 Clock_change_enable_cdbus (Divider_cdbus, 1, 29), 136 137 Clock_divider_cpu (Clock_control, 0x0f, 0), // CDIV 138 Clock_divider_hclock0 (Clock_control, 0x0f, 8), // H0DIV (fast AHB peripherals) 139 Clock_divider_hclock2 (Clock_control, 0x0f, 12), // H2DIV (fast AHB peripherals) 140 Clock_divider_l2cache (Clock_control, 0x0f, 4), // L2CDIV 141 Clock_divider_pclock (Clock_control, 0x0f, 16), // PDIV (slow APB peripherals) 142 Clock_divider_can0 (Divider_can0, 0xff, 0), // CAN0CDR 143 Clock_divider_can1 (Divider_can1, 0xff, 0), // CAN1CDR 144 Clock_divider_cdbus (Divider_cdbus, 0xff, 0), // CDBUSCDR 145 Clock_divider_cim (Divider_cim, 0xff, 0), // CIMCDR 146 Clock_divider_ddr (Divider_ddr, 0x0f, 0), // DDRCDR 147 Clock_divider_i2s0_m (Divider0_i2s0, 0x1ff, 20), // I2SDIV_M 148 Clock_divider_i2s0_n (Divider0_i2s0, 0xfffff, 0), // I2SDIV_N 149 Clock_divider_i2s0_d (Divider1_i2s0, 0xfffff, 0), // I2SDIV_D 150 Clock_divider_i2s1_m (Divider0_i2s1, 0x1ff, 20), // I2SDIV_M 151 Clock_divider_i2s1_n (Divider0_i2s1, 0xfffff, 0), // I2SDIV_N 152 Clock_divider_i2s1_d (Divider1_i2s1, 0xfffff, 0), // I2SDIV_D 153 Clock_divider_lcd (Divider_lcd, 0xff, 0), // LPCDR 154 Clock_divider_mac (Divider_mac, 0xff, 0), // MACCDR 155 Clock_divider_msc0 (Divider_msc0, 0xff, 0), // MSC0CDR 156 Clock_divider_msc1 (Divider_msc1, 0xff, 0), // MSC1CDR 157 Clock_divider_pwm (Divider_pwm, 0x0f, 0), // PWMCDR 158 Clock_divider_sfc (Divider_sfc, 0xff, 0), // SFCCDR 159 Clock_divider_ssi (Divider_ssi, 0xff, 0), // SSICDR 160 161 Clock_divider_i2s0_n_auto (Divider1_i2s0, 1, 31), // I2S_NEN 162 Clock_divider_i2s0_d_auto (Divider1_i2s0, 1, 30), // I2S_DEN 163 Clock_divider_i2s1_n_auto (Divider1_i2s1, 1, 31), // I2S_NEN 164 Clock_divider_i2s1_d_auto (Divider1_i2s1, 1, 30), // I2S_DEN 165 166 Clock_gate_main (Clock_control, 1, 23, true), // GATE_SCLKA 167 Clock_gate_ddr (Clock_gate0, 1, 31, true), // DDR 168 Clock_gate_ahb0 (Clock_gate0, 1, 29, true), // AHB0 169 Clock_gate_apb0 (Clock_gate0, 1, 28, true), // APB0 170 Clock_gate_rtc (Clock_gate0, 1, 27, true), // RTC 171 Clock_gate_aes (Clock_gate0, 1, 24, true), // AES 172 Clock_gate_lcd_pixel (Clock_gate0, 1, 23, true), // LCD 173 Clock_gate_cim (Clock_gate0, 1, 22, true), // CIM 174 Clock_gate_dma (Clock_gate0, 1, 21, true), // PDMA 175 Clock_gate_ost (Clock_gate0, 1, 20, true), // OST 176 Clock_gate_ssi0 (Clock_gate0, 1, 19, true), // SSI0 177 Clock_gate_timer (Clock_gate0, 1, 18, true), // TCU 178 Clock_gate_dtrng (Clock_gate0, 1, 17, true), // DTRNG 179 Clock_gate_uart2 (Clock_gate0, 1, 16, true), // UART2 180 Clock_gate_uart1 (Clock_gate0, 1, 15, true), // UART1 181 Clock_gate_uart0 (Clock_gate0, 1, 14, true), // UART0 182 Clock_gate_sadc (Clock_gate0, 1, 13, true), // SADC 183 Clock_gate_aic (Clock_gate0, 1, 11, true), // AUDIO 184 Clock_gate_ssi_slv (Clock_gate0, 1, 10, true), // SSI_SLV 185 Clock_gate_i2c1 (Clock_gate0, 1, 8, true), // I2C1 186 Clock_gate_i2c0 (Clock_gate0, 1, 7, true), // I2C0 187 Clock_gate_msc1 (Clock_gate0, 1, 5, true), // MSC1 188 Clock_gate_msc0 (Clock_gate0, 1, 4, true), // MSC0 189 Clock_gate_otg (Clock_gate0, 1, 3, true), // OTG 190 Clock_gate_sfc (Clock_gate0, 1, 2, true), // SFC 191 Clock_gate_efuse (Clock_gate0, 1, 1, true), // EFUSE 192 Clock_gate_nemc (Clock_gate0, 1, 0, true), // NEMC 193 Clock_gate_arb (Clock_gate1, 1, 30, true), // ARB 194 Clock_gate_mipi_csi (Clock_gate1, 1, 28, true), // MIPI_CSI 195 Clock_gate_intc (Clock_gate1, 1, 26, true), // INTC 196 Clock_gate_gmac0 (Clock_gate1, 1, 23, true), // GMAC0 197 Clock_gate_uart3 (Clock_gate1, 1, 16, true), // UART3 198 Clock_gate_i2s0_tx (Clock_gate1, 1, 9, true), // I2S0_dev_tclk 199 Clock_gate_i2s0_rx (Clock_gate1, 1, 8, true), // I2S0_dev_rclk 200 Clock_gate_hash (Clock_gate1, 1, 6, true), // HASH 201 Clock_gate_pwm (Clock_gate1, 1, 5, true), // PWM 202 Clock_gate_cdbus (Clock_gate1, 1, 2, true), // CDBUS 203 Clock_gate_can1 (Clock_gate1, 1, 1, true), // CAN1 204 Clock_gate_can0 (Clock_gate1, 1, 0, true), // CAN0 205 206 Pll_enable_A (Pll_control_A, 1, 0), // APLLEN 207 Pll_enable_E (Pll_control_E, 1, 0), // EPLLEN 208 Pll_enable_M (Pll_control_M, 1, 0), // MPLLEN 209 210 Pll_stable_A (Pll_control_A, 1, 3), // APLL_ON 211 Pll_stable_E (Pll_control_E, 1, 3), // EPLL_ON 212 Pll_stable_M (Pll_control_M, 1, 3), // MPLL_ON 213 214 Pll_bypass_A (Pll_control_A, 1, 30), // APLL_BP 215 Pll_bypass_E (Pll_control_E, 1, 26), // EPLL_BP 216 Pll_bypass_M (Pll_control_M, 1, 28), // MPLL_BP 217 218 Pll_multiplier_A (Pll_control_A, 0xfff, 20), // APLLM 219 Pll_multiplier_E (Pll_control_E, 0x3f, 20), // EPLLM (observed) 220 Pll_multiplier_M (Pll_control_M, 0xfff, 20), // MPLLM 221 222 Pll_input_division_A (Pll_control_A, 0x3f, 14), // APLLN 223 Pll_input_division_E (Pll_control_E, 0x3f, 14), // EPLLN 224 Pll_input_division_M (Pll_control_M, 0x3f, 14), // MPLLN 225 226 Pll_output_division1_A (Pll_control_A, 0x07, 11), // APLLOD1 227 Pll_output_division1_E (Pll_control_E, 0x07, 11), // EPLLOD1 228 Pll_output_division1_M (Pll_control_M, 0x07, 11), // MPLLOD1 229 230 Pll_output_division0_A (Pll_control_A, 0x07, 8), // APLLOD0 231 Pll_output_division0_E (Pll_control_E, 0x07, 8), // EPLLOD0 232 Pll_output_division0_M (Pll_control_M, 0x07, 8); // MPLLOD0 233 234 235 236 // Multiplexer instances. 237 238 #define Clocks(...) ((enum Clock_identifiers []) {__VA_ARGS__}) 239 240 static Mux mux_external (Clock_external), 241 242 // Clocks being propagated to others. 243 244 mux_hclock0 (Clock_hclock0), 245 mux_hclock2 (Clock_hclock2), 246 mux_pclock (Clock_pclock), 247 mux_hclock2_pclock (Clock_hclock2_pclock), 248 mux_i2s0_rx (Clock_i2s0), 249 mux_i2s0_tx (Clock_i2s1), 250 251 // Main peripheral and bus clock sources. 252 253 mux_bus (4, Clocks(Clock_main, Clock_pll_M, Clock_pll_E, Clock_external)), 254 mux_core (3, Clocks(Clock_none, Clock_main, Clock_pll_M)), 255 mux_dev (3, Clocks(Clock_main, Clock_pll_M, Clock_pll_E)), 256 mux_main (3, Clocks(Clock_none, Clock_external, Clock_pll_A)), 257 mux_i2s (2, Clocks(Clock_main, Clock_pll_E)); 258 259 260 261 // Clock instances. 262 263 static Clock_null clock_none; 264 265 static Clock_passive clock_external(24000000); 266 267 // Note the use of extra parentheses due to the annoying C++ "most vexing parse" 268 // problem. See: https://en.wikipedia.org/wiki/Most_vexing_parse 269 270 static Clock clock_aic((Source(mux_hclock2)), (Control(Clock_gate_aic))), 271 272 clock_dma((Source(mux_hclock2)), (Control(Clock_gate_dma))), 273 274 clock_i2c0((Source(mux_pclock)), (Control(Clock_gate_i2c0))), 275 276 clock_i2c1((Source(mux_pclock)), (Control(Clock_gate_i2c1))), 277 278 clock_i2s0(Source(mux_i2s, Clock_source_i2s0), Control(Clock_gate_i2s0)), 279 280 clock_i2s1(Source(mux_i2s, Clock_source_i2s1), Control(Clock_gate_i2s1)), 281 282 clock_main(Source(mux_main, Clock_source_main), Control(Clock_gate_main)), 283 284 clock_mipi_csi((Source(mux_hclock0)), Control(Clock_gate_mipi_csi)), 285 286 clock_otg0((Source(mux_hclock2)), (Control(Clock_gate_otg))), 287 288 clock_timer((Source(mux_pclock)), (Control(Clock_gate_timer))), 289 290 clock_uart0((Source(mux_external)), (Control(Clock_gate_uart0))), 291 292 clock_uart1((Source(mux_external)), (Control(Clock_gate_uart1))), 293 294 clock_uart2((Source(mux_external)), (Control(Clock_gate_uart2))), 295 296 clock_uart3((Source(mux_external)), (Control(Clock_gate_uart3))), 297 298 // Special parent clock for hclock2 and pclock. 299 300 clock_hclock2_pclock(Source(mux_core, Clock_source_hclock2), 301 Control(Clock_gate_apb0, Clock_change_enable_ahb2)); 302 303 static Clock_divided 304 clock_can0(Source(mux_bus, Clock_source_can0), 305 Control(Clock_gate_can0, Clock_change_enable_can0, Clock_busy_can0), 306 Divider(Clock_divider_can0)), 307 308 clock_can1(Source(mux_bus, Clock_source_can1), 309 Control(Clock_gate_can1, Clock_change_enable_can1, Clock_busy_can1), 310 Divider(Clock_divider_can1)), 311 312 clock_cdbus(Source(mux_dev, Clock_source_cdbus), 313 Control(Clock_gate_cdbus, Clock_change_enable_cdbus, Clock_busy_cdbus), 314 Divider(Clock_divider_cdbus)), 315 316 clock_cim(Source(mux_dev, Clock_source_cim), 317 Control(Clock_gate_cim, Clock_change_enable_cim, Clock_busy_cim), 318 Divider(Clock_divider_cim)), 319 320 clock_cpu(Source(mux_core, Clock_source_cpu), 321 Control(Field::undefined, Clock_change_enable_cpu, Clock_busy_cpu), 322 Divider(Clock_divider_cpu)), 323 324 clock_ddr(Source(mux_core, Clock_source_ddr), 325 Control(Clock_gate_ddr, Clock_change_enable_ddr, Clock_busy_ddr), 326 Divider(Clock_divider_ddr)), 327 328 clock_hclock0(Source(mux_core, Clock_source_hclock0), 329 Control(Clock_gate_ahb0, Clock_change_enable_ahb0), 330 Divider(Clock_divider_hclock0)), 331 332 clock_hclock2((Source(mux_hclock2_pclock)), (Divider(Clock_divider_hclock2))), 333 334 clock_lcd_pixel(Source(mux_dev, Clock_source_lcd), 335 Control(Clock_gate_lcd_pixel, Clock_change_enable_lcd, Clock_busy_lcd), 336 Divider(Clock_divider_lcd)), 337 338 clock_mac(Source(mux_dev, Clock_source_mac), 339 Control(Clock_gate_gmac0, Clock_change_enable_mac, Clock_busy_mac), 340 Divider(Clock_divider_mac)), 341 342 clock_msc0(Source(mux_dev, Clock_source_msc0), 343 Control(Clock_gate_msc0, Clock_change_enable_msc0, Clock_busy_msc0), 344 Divider(Clock_divider_msc0)), 345 346 clock_msc1(Source(mux_dev, Clock_source_msc1), 347 Control(Clock_gate_msc1, Clock_change_enable_msc1, Clock_busy_msc1), 348 Divider(Clock_divider_msc1)), 349 350 clock_pclock((Source(mux_hclock2_pclock)), (Divider(Clock_divider_pclock))), 351 352 clock_pwm0(Source(mux_dev, Clock_source_pwm), 353 Control(Clock_gate_pwm, Clock_change_enable_pwm, Clock_busy_pwm), 354 Divider(Clock_divider_pwm)), 355 356 clock_sfc(Source(mux_dev, Clock_source_sfc), 357 Control(Clock_gate_sfc, Clock_change_enable_sfc, Clock_busy_sfc), 358 Divider(Clock_divider_sfc)), 359 360 clock_ssi0(Source(mux_dev, Clock_source_ssi), 361 Control(Clock_gate_ssi0, Clock_change_enable_ssi, Clock_busy_ssi), 362 Divider(Clock_divider_ssi)); 363 364 static Clock_divided_i2s 365 clock_i2s0_rx(Source(mux_i2s0_rx), 366 Control(Clock_gate_i2s0_rx), 367 Divider_i2s(Clock_divider_i2s0_m, Clock_divider_i2s0_n, 368 Clock_divider_i2s0_d, Clock_divider_i2s0_n_auto, 369 Clock_divider_i2s0_d_auto)), 370 371 clock_i2s0_tx(Source(mux_i2s0_tx), 372 Control(Clock_gate_i2s0_tx), 373 Divider_i2s(Clock_divider_i2s1_m, Clock_divider_i2s1_n, 374 Clock_divider_i2s1_d, Clock_divider_i2s1_n_auto, 375 Clock_divider_i2s1_d_auto)); 376 377 const double x1600_pll_intermediate_min = 600000000, 378 x1600_pll_intermediate_max = 2400000000; 379 380 static Pll clock_pll_A(Source(mux_external), 381 Control_pll(Pll_enable_A, Pll_stable_A, Pll_bypass_A), 382 Divider_pll(Pll_multiplier_A, Pll_input_division_A, 383 Pll_output_division0_A, Pll_output_division1_A, 384 x1600_pll_intermediate_min, x1600_pll_intermediate_max)), 385 386 clock_pll_E(Source(mux_external), 387 Control_pll(Pll_enable_E, Pll_stable_E, Pll_bypass_E), 388 Divider_pll(Pll_multiplier_E, Pll_input_division_E, 389 Pll_output_division0_E, Pll_output_division1_E, 390 x1600_pll_intermediate_min, x1600_pll_intermediate_max)), 391 392 clock_pll_M(Source(mux_external), 393 Control_pll(Pll_enable_M, Pll_stable_M, Pll_bypass_M), 394 Divider_pll(Pll_multiplier_M, Pll_input_division_M, 395 Pll_output_division0_M, Pll_output_division1_M, 396 x1600_pll_intermediate_min, x1600_pll_intermediate_max)); 397 398 399 400 // Clock register. 401 402 static Clock_base *clocks[Clock_identifier_count] = { 403 &clock_aic, 404 &clock_none, // Clock_aic_bitclk 405 &clock_none, // Clock_aic_pclk 406 &clock_can0, 407 &clock_can1, 408 &clock_cdbus, 409 &clock_cim, 410 &clock_cpu, 411 &clock_ddr, 412 &clock_dma, 413 &clock_none, // Clock_emac 414 &clock_external, 415 &clock_hclock0, 416 &clock_hclock2, 417 &clock_hclock2_pclock, 418 &clock_none, // Clock_hdmi 419 &clock_i2c0, 420 &clock_i2c1, 421 &clock_none, // Clock_i2c2 422 &clock_none, // Clock_i2c3 423 &clock_none, // Clock_i2c4 424 &clock_i2s0, // supplies i2s0_rx 425 &clock_i2s0_rx, 426 &clock_i2s0_tx, 427 &clock_i2s1, // supplies i2s0_tx 428 &clock_none, // Clock_i2s1_rx 429 &clock_none, // Clock_i2s1_tx 430 &clock_none, // Clock_kbc 431 &clock_none, // Clock_lcd 432 &clock_lcd_pixel, 433 &clock_none, // Clock_lcd_pixel1 434 &clock_mac, 435 &clock_main, 436 &clock_mipi_csi, 437 &clock_none, // Clock_msc 438 &clock_msc0, 439 &clock_msc1, 440 &clock_none, // Clock_msc2 441 &clock_none, // Clock_none 442 &clock_otg0, 443 &clock_none, // Clock_otg1 444 &clock_pclock, 445 &clock_pll_A, 446 &clock_pll_E, 447 &clock_pll_M, 448 &clock_none, // Clock_pll_V 449 &clock_pwm0, 450 &clock_none, // Clock_pwm1 451 &clock_none, // Clock_rtc 452 &clock_none, // Clock_scc 453 &clock_sfc, 454 &clock_none, // Clock_ssi 455 &clock_ssi0, 456 &clock_none, // Clock_ssi1 457 &clock_none, // Clock_ssi2 458 &clock_timer, 459 &clock_uart0, 460 &clock_uart1, 461 &clock_uart2, 462 &clock_uart3, 463 &clock_none, // Clock_udc 464 &clock_none, // Clock_uhc 465 &clock_none, // Clock_uprt 466 &clock_none, // Clock_vpu 467 }; 468 469 470 471 // Peripheral abstraction. 472 473 Cpm_x1600_chip::Cpm_x1600_chip(l4_addr_t addr) 474 : Cpm_chip(addr, clocks) 475 { 476 } 477 478 479 480 // C language interface functions. 481 482 void 483 *x1600_cpm_init(l4_addr_t cpm_base) 484 { 485 return (void *) new Cpm_x1600_chip(cpm_base); 486 } 487 488 const char * 489 x1600_cpm_clock_type(void *cpm, enum Clock_identifiers clock) 490 { 491 return static_cast<Cpm_x1600_chip *>(cpm)->clock_type(clock); 492 } 493 494 int 495 x1600_cpm_have_clock(void *cpm, enum Clock_identifiers clock) 496 { 497 return static_cast<Cpm_x1600_chip *>(cpm)->have_clock(clock); 498 } 499 500 void 501 x1600_cpm_start_clock(void *cpm, enum Clock_identifiers clock) 502 { 503 static_cast<Cpm_x1600_chip *>(cpm)->start_clock(clock); 504 } 505 506 void 507 x1600_cpm_stop_clock(void *cpm, enum Clock_identifiers clock) 508 { 509 static_cast<Cpm_x1600_chip *>(cpm)->stop_clock(clock); 510 } 511 512 int 513 x1600_cpm_get_parameters(void *cpm, enum Clock_identifiers clock, uint32_t parameters[]) 514 { 515 return static_cast<Cpm_x1600_chip *>(cpm)->get_parameters(clock, parameters); 516 } 517 518 int 519 x1600_cpm_set_parameters(void *cpm, enum Clock_identifiers clock, int num_parameters, uint32_t parameters[]) 520 { 521 return static_cast<Cpm_x1600_chip *>(cpm)->set_parameters(clock, num_parameters, parameters); 522 } 523 524 uint8_t 525 x1600_cpm_get_source(void *cpm, enum Clock_identifiers clock) 526 { 527 return static_cast<Cpm_x1600_chip *>(cpm)->get_source(clock); 528 } 529 530 void 531 x1600_cpm_set_source(void *cpm, enum Clock_identifiers clock, uint8_t source) 532 { 533 static_cast<Cpm_x1600_chip *>(cpm)->set_source(clock, source); 534 } 535 536 enum Clock_identifiers 537 x1600_cpm_get_source_clock(void *cpm, enum Clock_identifiers clock) 538 { 539 return static_cast<Cpm_x1600_chip *>(cpm)->get_source_clock(clock); 540 } 541 542 void 543 x1600_cpm_set_source_clock(void *cpm, enum Clock_identifiers clock, enum Clock_identifiers source) 544 { 545 static_cast<Cpm_x1600_chip *>(cpm)->set_source_clock(clock, source); 546 } 547 548 uint64_t 549 x1600_cpm_get_source_frequency(void *cpm, enum Clock_identifiers clock) 550 { 551 return static_cast<Cpm_x1600_chip *>(cpm)->get_source_frequency(clock); 552 } 553 554 uint64_t 555 x1600_cpm_get_frequency(void *cpm, enum Clock_identifiers clock) 556 { 557 return static_cast<Cpm_x1600_chip *>(cpm)->get_frequency(clock); 558 } 559 560 int 561 x1600_cpm_set_frequency(void *cpm, enum Clock_identifiers clock, uint64_t frequency) 562 { 563 return static_cast<Cpm_x1600_chip *>(cpm)->set_frequency(clock, frequency); 564 }