1 /* 2 * JZ4780 HDMI peripheral support. 3 * 4 * Copyright (C) 2020 Paul Boddie <paul@boddie.org.uk> 5 * 6 * Techniques and operations introduced from the Linux DRM bridge driver for 7 * Synopsys DW-HDMI whose authors are as follows: 8 * 9 * Copyright (C) 2013-2015 Mentor Graphics Inc. 10 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. 11 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de> 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of 16 * the License, or (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 26 * Boston, MA 02110-1301, USA 27 * 28 * ---- 29 * 30 * Some acronyms: 31 * 32 * CEC (Consumer Electronics Control) is a HDMI device control interface for up 33 * to 15 devices. 34 * 35 * CSC (Colour Space Conversion) is the processing needed to convert from one 36 * representation of colours to another. 37 * 38 * HEAC (HDMI Ethernet and Audio Return Channel) is a combination of HEC (HDMI 39 * Ethernet Channel) which provides a 100Mb/s bidirectional link and ARC (Audio 40 * Return Channel) which permits the consumption of audio data from the device. 41 * 42 * MHL (Mobile High-Definition Link) is an adaptation of HDMI for mobile 43 * devices. 44 * 45 * TMDS (Transition-Minimized Differential Signaling) is the method by which 46 * audio, control and video data are all sent to the device. 47 */ 48 49 #include <l4/devices/hdmi-jz4780.h> 50 #include <l4/devices/hw_mmio_register_block.h> 51 #include <l4/devices/lcd-jz4740-config.h> 52 53 #include <l4/sys/irq.h> 54 #include <l4/util/util.h> 55 56 #include <cstdio> 57 58 /* 59 I2C pins: 60 61 HDMI: PF25/SMB4_SDA/DDCSDA, PF24/SMB4_SCK/DDCSCK 62 63 See: http://mipscreator.imgtec.com/CI20/hardware/board/ci20_jz4780_v2.0.pdf 64 */ 65 66 enum Regs 67 { 68 // Identification. 69 70 Design_id = 0x000, // DESIGN_ID 71 Revision_id = 0x001, // REVISION_ID 72 Product_id0 = 0x002, // PRODUCT_ID0 73 Product_id1 = 0x003, // PRODUCT_ID1 74 Config_id0 = 0x004, // CONFIG_ID0 75 Config_id1 = 0x005, // CONFIG_ID1 76 Config_id2 = 0x006, // CONFIG_ID2 77 Config_id3 = 0x007, // CONFIG_ID3 78 79 // Top-level interrupt control. 80 81 Int_mask = 0x1ff, // MUTE 82 83 // Interrupt status and mask for various functions. 84 85 Fc_int_status0 = 0x100, // FC_STAT0 86 Fc_int_status1 = 0x101, // FC_STAT1 87 Fc_int_status2 = 0x102, // FC_STAT2 88 As_int_status = 0x103, // AS_STAT0 89 Phy_int_status = 0x104, // PHY_STAT0 90 Cec_int_status = 0x106, // CEC_STAT0 91 Vp_int_status = 0x107, // VP_STAT0 92 Ahb_dma_audio_int_status = 0x109, // AHBDMAAUD_STAT0 93 94 Fc_int_mask0 = 0x180, // MUTE_FC_STAT0 95 Fc_int_mask1 = 0x181, // MUTE_FC_STAT1 96 Fc_int_mask2 = 0x182, // MUTE_FC_STAT2 97 As_int_mask = 0x183, // MUTE_AS_STAT0 98 Phy_int_mask = 0x184, // MUTE_PHY_STAT0 99 Cec_int_mask = 0x186, // MUTE_CEC_STAT0 100 Vp_int_mask = 0x187, // MUTE_VP_STAT0 101 Ahb_dma_audio_int_mask = 0x189, // MUTE_AHBDMAAUD_STAT0 102 103 // I2C for E-DDC. 104 105 I2c_int_status = 0x105, // I2CM_STAT0 106 I2c_int_mask = 0x185, // MUTE_I2CM_STAT0 107 108 I2c_device_address = 0x7e00, // I2CM_SLAVE 109 I2c_register = 0x7e01, // I2CM_ADDRESS 110 I2c_data_out = 0x7e02, // I2CM_DATAO 111 I2c_data_in = 0x7e03, // I2CM_DATAI 112 I2c_operation = 0x7e04, // I2CM_OPERATION 113 I2c_int_config0 = 0x7e05, // I2CM_INT 114 I2c_int_config1 = 0x7e06, // I2CM_CTLINT 115 I2c_divider = 0x7e07, // I2CM_DIV 116 I2c_segment_address = 0x7e08, // I2CM_SEGADDR 117 I2c_software_reset = 0x7e09, // I2CM_SOFTRSTZ 118 I2c_segment_pointer = 0x7e0a, // I2CM_SEGPTR 119 120 // I2C for PHY. 121 122 I2c_phy_int_status = 0x108, // I2CMPHY_STAT0 123 I2c_phy_int_mask = 0x188, // MUTE_I2CMPHY_STAT0 124 125 I2c_phy_device_address = 0x3020, // PHY_I2CM_SLAVE_ADDR 126 I2c_phy_register = 0x3021, // PHY_I2CM_ADDRESS_ADDR 127 I2c_phy_data_out1 = 0x3022, // PHY_I2CM_DATAO_1_ADDR 128 I2c_phy_data_out0 = 0x3023, // PHY_I2CM_DATAO_0_ADDR 129 I2c_phy_data_in1 = 0x3024, // PHY_I2CM_DATAI_1_ADDR 130 I2c_phy_data_in0 = 0x3025, // PHY_I2CM_DATAI_0_ADDR 131 I2c_phy_operation = 0x3026, // PHY_I2CM_OPERATION_ADDR 132 I2c_phy_int_config0 = 0x3027, // PHY_I2CM_INT_ADDR 133 I2c_phy_int_config1 = 0x3028, // PHY_I2CM_CTLINT_ADDR 134 I2c_phy_divider = 0x3029, // PHY_I2CM_DIV_ADDR 135 I2c_phy_software_reset = 0x302a, // PHY_I2CM_SOFTRSTZ_ADDR 136 137 // PHY registers. 138 139 Phy_config = 0x3000, // PHY_CONF0 140 Phy_test0 = 0x3001, // PHY_TST0 141 Phy_test1 = 0x3002, // PHY_TST1 142 Phy_test2 = 0x3003, // PHY_TST2 143 Phy_status = 0x3004, // PHY_STAT0 144 Phy_int_config = 0x3005, // PHY_INT0 145 Phy_mask = 0x3006, // PHY_MASK0 146 Phy_polarity = 0x3007, // PHY_POL0 147 148 // Main controller registers. 149 150 Main_clock_disable = 0x4001, // MC_CLKDIS 151 Main_software_reset = 0x4002, // MC_SWRSTZ 152 Main_flow_control = 0x4004, // MC_FLOWCTRL 153 Main_reset = 0x4005, // MC_PHYRSTZ 154 Main_heac_phy_reset = 0x4007, // MC_HEACPHY_RST 155 156 // Frame composer registers for input video. 157 158 Fc_video_config = 0x1000, // FC_INVIDCONF 159 Fc_horizontal_active_width0 = 0x1001, // FC_INHACTV0 160 Fc_horizontal_active_width1 = 0x1002, // FC_INHACTV1 161 Fc_horizontal_blank_width0 = 0x1003, // FC_INHBLANK0 162 Fc_horizontal_blank_width1 = 0x1004, // FC_INHBLANK1 163 Fc_vertical_active_height0 = 0x1005, // FC_INVACTV0 164 Fc_vertical_active_height1 = 0x1006, // FC_INVACTV1 165 Fc_vertical_blank_height = 0x1007, // FC_INVBLANK 166 167 // Frame composer registers for sync pulses. 168 169 Fc_hsync_delay0 = 0x1008, // FC_HSYNCINDELAY0 170 Fc_hsync_delay1 = 0x1009, // FC_HSYNCINDELAY1 171 Fc_hsync_width0 = 0x100A, // FC_HSYNCINWIDTH0 172 Fc_hsync_width1 = 0x100B, // FC_HSYNCINWIDTH1 173 Fc_vsync_delay = 0x100C, // FC_VSYNCINDELAY 174 Fc_vsync_height = 0x100D, // FC_VSYNCINWIDTH 175 176 // Frame composer registers for video path configuration. 177 178 Fc_control_duration = 0x1011, // FC_CTRLDUR 179 Fc_ex_control_duration = 0x1012, // FC_EXCTRLDUR 180 Fc_ex_control_space = 0x1013, // FC_EXCTRLSPAC 181 Fc_channel0_preamble = 0x1014, // FC_CH0PREAM 182 Fc_channel1_preamble = 0x1015, // FC_CH1PREAM 183 Fc_channel2_preamble = 0x1016, // FC_CH2PREAM 184 185 // Colour space conversion registers. 186 187 Csc_config = 0x4100, // CSC_CFG 188 Csc_scale = 0x4101, // CSC_SCALE 189 190 // HDCP registers. 191 192 Hdcp_config0 = 0x5000, // A_HDCPCFG0 193 Hdcp_config1 = 0x5001, // A_HDCPCFG1 194 Hdcp_video_polarity = 0x5009, // A_VIDPOLCFG 195 196 // Video sample registers. 197 198 Sample_video_config = 0x0200, // TX_INVID0 199 Sample_video_stuffing = 0x0201, // TX_INSTUFFING 200 Sample_gy_data0 = 0x0202, // TX_GYDATA0 201 Sample_gy_data1 = 0x0203, // TX_GYDATA1 202 Sample_rcr_data0 = 0x0204, // TX_RCRDATA0 203 Sample_rcr_data1 = 0x0205, // TX_RCRDATA1 204 Sample_bcb_data0 = 0x0206, // TX_BCBDATA0 205 Sample_bcb_data1 = 0x0207, // TX_BCBDATA1 206 207 // Video packetizer registers. 208 209 Packet_status = 0x0800, // VP_STATUS 210 Packet_pr_cd = 0x0801, // VP_PR_CD 211 Packet_stuffing = 0x0802, // VP_STUFF 212 Packet_remap = 0x0803, // VP_REMAP 213 Packet_config = 0x0804, // VP_CONF 214 }; 215 216 // Identification values. 217 218 enum Product_id_values : uint8_t 219 { 220 Product_id0_transmitter = 0xa0, // PRODUCT_ID0_HDMI_TX 221 222 Product_id1_hdcp = 0xc0, // PRODUCT_ID1_HDCP 223 Product_id1_receiver = 0x02, // PRODUCT_ID1_HDMI_RX 224 Product_id1_transmitter = 0x01, // PRODUCT_ID1_HDMI_TX 225 }; 226 227 // Configuration values. 228 229 enum Config_id_values : uint8_t 230 { 231 Config_id0_i2s = 0x10, // CONFIG0_I2S 232 Config_id0_cec = 0x02, // CONFIG0_CEC 233 234 Config_id1_ahb = 0x01, // CONFIG1_AHB 235 236 Config2_dwc_hdmi_tx_phy = 0x00, // DWC_HDMI_TX_PHY 237 Config2_dwc_mhl_phy_heac = 0xb2, // DWC_MHL_PHY_HEAC 238 Config2_dwc_mhl_phy = 0xc2, // DWC_MHL_PHY 239 Config2_dwc_hdmi_3d_tx_phy_heac = 0xe2, // DWC_HDMI_3D_TX_PHY_HEAC 240 Config2_dwc_hdmi_3d_tx_phy = 0xf2, // DWC_HDMI_3D_TX_PHY 241 Config2_dwc_hdmi20_tx_phy = 0xf3, // DWC_HDMI20_TX_PHY 242 Config2_vendor_phy = 0xfe, // VENDOR_PHY 243 244 Config_id3_ahb_audio_dma = 0x02, // CONFIG3_AHBAUDDMA 245 Config_id3_gp_audio = 0x01, // CONFIG3_GPAUD 246 }; 247 248 // Status and mask bits. 249 250 enum Int_mask_bits : uint8_t 251 { 252 Int_mask_wakeup = 0x02, 253 Int_mask_all = 0x01, 254 }; 255 256 // I2C status and mask bits, also for PHY I2C. 257 258 enum I2c_int_status_bits : uint8_t 259 { 260 I2c_int_status_done = 0x02, 261 I2c_int_status_error = 0x01, 262 }; 263 264 // I2C operation bits. 265 266 enum I2c_operation_bits : uint8_t 267 { 268 I2c_operation_write = 0x10, 269 I2c_operation_segment_read = 0x02, // not PHY I2C 270 I2c_operation_read = 0x01, 271 }; 272 273 // Device addresses. 274 275 enum I2c_phy_device_addresses : uint8_t 276 { 277 I2c_phy_device_phy_gen2 = 0x69, // PHY_I2CM_SLAVE_ADDR_PHY_GEN2 278 I2c_phy_device_phy_heac = 0x49, // PHY_I2CM_SLAVE_ADDR_HEAC_PHY 279 }; 280 281 // Device registers. 282 283 enum I2c_phy_device_registers : uint8_t 284 { 285 I2c_phy_3d_tx_clock_cal_ctrl = 0x05, // 3D_TX_PHY_CKCALCTRL 286 I2c_phy_3d_tx_cpce_ctrl = 0x06, // 3D_TX_PHY_CPCE_CTRL 287 I2c_phy_3d_tx_clock_symbol_ctrl = 0x09, // 3D_TX_PHY_CKSYMTXCTRL 288 I2c_phy_3d_tx_vlevel_ctrl = 0x0e, // 3D_TX_PHY_VLEVCTRL 289 I2c_phy_3d_tx_curr_ctrl = 0x10, // 3D_TX_PHY_CURRCTRL 290 I2c_phy_3d_tx_pll_phby_ctrl = 0x13, // 3D_TX_PHY_PLLPHBYCTRL 291 I2c_phy_3d_tx_gmp_ctrl = 0x15, // 3D_TX_PHY_GMPCTRL 292 I2c_phy_3d_tx_msm_ctrl = 0x17, // 3D_TX_PHY_MSM_CTRL 293 I2c_phy_3d_tx_term = 0x19, // 3D_TX_PHY_TXTERM 294 }; 295 296 // PHY I2C register values. 297 298 enum Msm_ctrl_bits : uint16_t 299 { 300 Msm_ctrl_clock_output_select_fb = 1 << 3, // 3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK 301 }; 302 303 enum Clock_cal_ctrl_bits : uint16_t 304 { 305 Clock_cal_ctrl_override = 1 << 15, // 3D_TX_PHY_CKCALCTRL_OVERRIDE 306 }; 307 308 // Interrupt configuration bits, also for PHY I2C. 309 310 enum I2c_int_config0_bits : uint8_t 311 { 312 I2c_int_config0_done_polarity = 0x08, 313 I2c_int_config0_done_mask = 0x04, 314 }; 315 316 enum I2c_int_config1_bits : uint8_t 317 { 318 I2c_int_config1_nack_polarity = 0x80, 319 I2c_int_config1_nack_mask = 0x40, 320 I2c_int_config1_arb_polarity = 0x08, 321 I2c_int_config1_arb_mask = 0x04, 322 }; 323 324 // PHY configuration values. 325 326 enum Phy_config_bits : uint8_t 327 { 328 Phy_config_powerdown_disable = 0x80, // PHY_CONF0_PDZ_MASK 329 Phy_config_tmds = 0x40, // PHY_CONF0_ENTMDS_MASK 330 Phy_config_svsret = 0x20, // PHY_CONF0_SVSRET_MASK 331 Phy_config_gen2_powerdown = 0x10, // PHY_CONF0_GEN2_PDDQ_MASK 332 Phy_config_gen2_tx_power = 0x08, // PHY_CONF0_GEN2_TXPWRON_MASK 333 Phy_config_gen2_hotplug_detect_rx_sense = 0x04, // PHY_CONF0_GEN2_ENHPDRXSENSE_MASK 334 Phy_config_select_data_enable_polarity = 0x02, // PHY_CONF0_SELDATAENPOL_MASK 335 Phy_config_select_interface_control = 0x01, // PHY_CONF0_SELDIPIF_MASK 336 }; 337 338 enum Phy_test_bits : uint8_t 339 { 340 Phy_test0_clear_mask = 0x20, // PHY_TST0_TSTCLR_MASK 341 Phy_test0_enable_mask = 0x10, // PHY_TST0_TSTEN_MASK 342 Phy_test0_clock_mask = 0x01, // PHY_TST0_TSTCLK_MASK 343 }; 344 345 // PHY status and mask values. 346 347 enum Phy_status_bits : uint8_t 348 { 349 Phy_status_all = 0xf3, 350 Phy_status_rx_sense_all = 0xf0, 351 Phy_status_rx_sense3 = 0x80, // PHY_RX_SENSE3 352 Phy_status_rx_sense2 = 0x40, // PHY_RX_SENSE2 353 Phy_status_rx_sense1 = 0x20, // PHY_RX_SENSE1 354 Phy_status_rx_sense0 = 0x10, // PHY_RX_SENSE0 355 Phy_status_hotplug_detect = 0x02, // PHY_HPD 356 Phy_status_tx_phy_lock = 0x01, // PHY_TX_PHY_LOCK 357 Phy_status_none = 0, 358 }; 359 360 // PHY interrupt status and mask values. 361 362 enum Phy_int_status_bits : uint8_t 363 { 364 Phy_int_status_all = 0x3f, 365 Phy_int_status_rx_sense_all = 0x3c, 366 Phy_int_status_rx_sense3 = 0x20, // IH_PHY_STAT0_RX_SENSE3 367 Phy_int_status_rx_sense2 = 0x10, // IH_PHY_STAT0_RX_SENSE2 368 Phy_int_status_rx_sense1 = 0x08, // IH_PHY_STAT0_RX_SENSE1 369 Phy_int_status_rx_sense0 = 0x04, // IH_PHY_STAT0_RX_SENSE0 370 Phy_int_status_tx_phy_lock = 0x02, // IH_PHY_STAT0_TX_PHY_LOCK 371 Phy_int_status_hotplug_detect = 0x01, // IH_PHY_STAT0_HPD 372 Phy_int_status_none = 0, 373 }; 374 375 // PHY main register values. 376 377 enum Main_heac_phy_reset_bits : uint8_t 378 { 379 Main_heac_phy_reset_assert = 0x01, // MC_HEACPHY_RST_ASSERT 380 }; 381 382 enum Main_flow_control_bits : uint8_t 383 { 384 Main_flow_control_csc_active = 0x01, // MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH 385 Main_flow_control_csc_inactive = 0x00, // MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS 386 }; 387 388 enum Main_clock_disable_bits : uint8_t 389 { 390 Main_clock_disable_hdcp = 0x40, // MC_CLKDIS_HDCPCLK_DISABLE 391 Main_clock_disable_cec = 0x20, // MC_CLKDIS_CECCLK_DISABLE 392 Main_clock_disable_csc = 0x10, // MC_CLKDIS_CSCCLK_DISABLE 393 Main_clock_disable_audio = 0x08, // MC_CLKDIS_AUDCLK_DISABLE 394 Main_clock_disable_prep = 0x04, // MC_CLKDIS_PREPCLK_DISABLE 395 Main_clock_disable_tmds = 0x02, // MC_CLKDIS_TMDSCLK_DISABLE 396 Main_clock_disable_pixel = 0x01, // MC_CLKDIS_PIXELCLK_DISABLE 397 }; 398 399 enum Main_software_reset_bits : uint8_t 400 { 401 Main_software_reset_tmds = 0x02, // MC_SWRSTZ_TMDSSWRST_REQ 402 }; 403 404 // Frame composer values. 405 406 enum Fc_video_config_bits : uint8_t 407 { 408 Fc_video_config_hdcp_keepout_active = 0x80, // FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE 409 Fc_video_config_hdcp_keepout_inactive = 0x00, // FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE 410 Fc_video_config_vsync_active_high = 0x40, // FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH 411 Fc_video_config_vsync_active_low = 0x00, // FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW 412 Fc_video_config_hsync_active_high = 0x20, // FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH 413 Fc_video_config_hsync_active_low = 0x00, // FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW 414 Fc_video_config_data_enable_active_high = 0x10, // FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH 415 Fc_video_config_data_enable_active_low = 0x00, // FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW 416 Fc_video_config_hdmi_mode = 0x08, // FC_INVIDCONF_DVI_MODEZ_HDMI_MODE 417 Fc_video_config_dvi_mode = 0x00, // FC_INVIDCONF_DVI_MODEZ_DVI_MODE 418 Fc_video_config_osc_active_high = 0x02, // FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH 419 Fc_video_config_osc_active_low = 0x00, // FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW 420 Fc_video_config_interlaced = 0x01, // FC_INVIDCONF_IN_I_P_INTERLACED 421 Fc_video_config_progressive = 0x00, // FC_INVIDCONF_IN_I_P_PROGRESSIVE 422 }; 423 424 enum Fc_int_status2_bits : uint8_t 425 { 426 Fc_int_status2_overflow = 0x03, // FC_STAT2_OVERFLOW_MASK 427 Fc_int_status2_overflow_low = 0x02, // FC_STAT2_LOW_PRIORITY_OVERFLOW 428 Fc_int_status2_overflow_high = 0x01 // FC_STAT2_HIGH_PRIORITY_OVERFLOW, 429 }; 430 431 // Colour space conversion values. 432 433 enum Csc_config_bits : uint8_t 434 { 435 Csc_config_interpolation_mask = 0x30, // CSC_CFG_INTMODE_MASK 436 Csc_config_interpolation_disable = 0x00, // CSC_CFG_INTMODE_DISABLE 437 Csc_config_interpolation_form1 = 0x10, // CSC_CFG_INTMODE_CHROMA_INT_FORMULA1 438 Csc_config_interpolation_form2 = 0x20, // CSC_CFG_INTMODE_CHROMA_INT_FORMULA2 439 Csc_config_decimation_mask = 0x3, // CSC_CFG_DECMODE_MASK 440 Csc_config_decimation_disable = 0x0, // CSC_CFG_DECMODE_DISABLE 441 Csc_config_decimation_form1 = 0x1, // CSC_CFG_DECMODE_CHROMA_INT_FORMULA1 442 Csc_config_decimation_form2 = 0x2, // CSC_CFG_DECMODE_CHROMA_INT_FORMULA2 443 Csc_config_decimation_form3 = 0x3, // CSC_CFG_DECMODE_CHROMA_INT_FORMULA3 444 }; 445 446 enum Csc_scale_bits : uint8_t 447 { 448 Csc_scale_colour_depth_mask = 0xf0, // CSC_SCALE_CSC_COLORDE_PTH_MASK 449 Csc_scale_colour_depth_24bpp = 0x00, // CSC_SCALE_CSC_COLORDE_PTH_24BPP 450 Csc_scale_colour_depth_30bpp = 0x50, // CSC_SCALE_CSC_COLORDE_PTH_30BPP 451 Csc_scale_colour_depth_36bpp = 0x60, // CSC_SCALE_CSC_COLORDE_PTH_36BPP 452 Csc_scale_colour_depth_48bpp = 0x70, // CSC_SCALE_CSC_COLORDE_PTH_48BPP 453 Csc_scale_mask = 0x03, // CSC_SCALE_CSCSCALE_MASK 454 }; 455 456 // HDCP register values. 457 458 enum Hdcp_config0_bits : uint8_t 459 { 460 Hdcp_config0_rxdetect_enable = 0x4, // A_HDCPCFG0_RXDETECT_ENABLE 461 }; 462 463 enum Hdcp_config1_bits : uint8_t 464 { 465 Hdcp_config1_encryption_disable = 0x2, // A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE 466 }; 467 468 enum Hdcp_video_polarity_bits : uint8_t 469 { 470 Hdcp_video_polarity_data_enable_active_high = 0x10, // A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH 471 }; 472 473 // Video sample register values. 474 475 enum Sample_video_config_bits : uint8_t 476 { 477 Sample_video_config_data_enable_active = 0x80, // TX_INVID0_INTERNAL_DE_GENERATOR_ENABLE 478 Sample_video_config_mapping_mask = 0x1f, // TX_INVID0_VIDEO_MAPPING_MASK 479 }; 480 481 enum Sample_video_stuffing_bits : uint8_t 482 { 483 Sample_video_stuffing_bdb_data = 0x04, // TX_INSTUFFING_BDBDATA_STUFFING_ENABLE 484 Sample_video_stuffing_rcr_data = 0x02, // TX_INSTUFFING_RCRDATA_STUFFING_ENABLE 485 Sample_video_stuffing_gy_data = 0x01, // TX_INSTUFFING_GYDATA_STUFFING_ENABLE 486 }; 487 488 // Video packetizer register values. 489 490 enum Packet_stuffing_bits : uint8_t 491 { 492 Packet_stuffing_default_phase = 0x20, // VP_STUFF_IDEFAULT_PHASE_MASK 493 Packet_stuffing_ifix_pp_to_last = 0x10, // VP_STUFF_IFIX_PP_TO_LAST_MASK 494 Packet_stuffing_icx = 0x08, // VP_STUFF_ICX_GOTO_P0_ST_MASK 495 Packet_stuffing_ycc422 = 0x04, // VP_STUFF_YCC422_STUFFING_STUFFING_MODE 496 Packet_stuffing_pp = 0x02, // VP_STUFF_PP_STUFFING_STUFFING_MODE 497 Packet_stuffing_pr = 0x01, // VP_STUFF_PR_STUFFING_STUFFING_MODE 498 }; 499 500 enum Packet_config_bits : uint8_t 501 { 502 Packet_config_bypass_enable = 0x40, // VP_CONF_BYPASS_EN_ENABLE 503 Packet_config_pp_enable = 0x20, // VP_CONF_PP_EN_ENABLE 504 Packet_config_pr_enable = 0x10, // VP_CONF_PR_EN_ENABLE 505 Packet_config_ycc422_enable = 0x8, // VP_CONF_YCC422_EN_ENABLE 506 Packet_config_bypass_select_packetizer = 0x4, // VP_CONF_BYPASS_SELECT_VID_PACKETIZER 507 Packet_config_output_selector_mask = 0x3, // VP_CONF_OUTPUT_SELECTOR_MASK 508 Packet_config_output_selector_bypass = 0x3, // VP_CONF_OUTPUT_SELECTOR_BYPASS 509 Packet_config_output_selector_ycc422 = 0x1, // VP_CONF_OUTPUT_SELECTOR_YCC422 510 Packet_config_output_selector_pp = 0x0, // VP_CONF_OUTPUT_SELECTOR_PP 511 }; 512 513 enum Packet_remap_bits : uint8_t 514 { 515 Packet_remap_mask = 0x3, // VP_REMAP_MASK 516 Packet_remap_ycc422_24bit = 0x2, // VP_REMAP_YCC422_24bit 517 Packet_remap_ycc422_20bit = 0x1, // VP_REMAP_YCC422_20bit 518 Packet_remap_ycc422_16bit = 0x0, // VP_REMAP_YCC422_16bit 519 }; 520 521 enum Packet_pr_cd_bits : uint8_t 522 { 523 Packet_pr_cd_depth_mask = 0xf0, // VP_PR_CD_COLOR_DEPTH_MASK 524 Packet_pr_cd_depth_offset = 4, // VP_PR_CD_COLOR_DEPTH_OFFSET 525 Packet_pr_cd_factor_mask = 0x0f, // VP_PR_CD_DESIRED_PR_FACTOR_MASK 526 Packet_pr_cd_factor_offset = 0, // VP_PR_CD_DESIRED_PR_FACTOR_OFFSET 527 }; 528 529 530 531 // PHY capabilities. 532 533 static const Phy_capabilities phy_capabilities[] = { 534 // name gen svsret configure 535 {Config2_dwc_hdmi_tx_phy, "DWC_HDMI_TX_PHY", 1, false, false}, 536 {Config2_dwc_mhl_phy_heac, "DWC_MHL_PHY_HEAC", 2, true, true}, 537 {Config2_dwc_mhl_phy, "DWC_MHL_PHY", 2, true, true}, 538 {Config2_dwc_hdmi_3d_tx_phy_heac, "DWC_HDMI_3D_TX_PHY_HEAC", 2, false, true}, 539 {Config2_dwc_hdmi_3d_tx_phy, "DWC_HDMI_3D_TX_PHY", 2, false, true}, 540 {Config2_dwc_hdmi20_tx_phy, "DWC_HDMI20_TX_PHY", 2, true, true}, 541 {0, "Vendor PHY", 0, false, false}, 542 }; 543 544 545 546 // PHY configuration, adopting the Linux driver's tables of values. 547 548 static const struct Phy_mpll_config phy_mpll_config[] = { 549 // 8bpc 10bpc 12bpc 550 // pixelclock cpce gmp cpce gmp cpce gmp 551 { 45250000, { {0x01e0, 0x0000}, {0x21e1, 0x0000}, {0x41e2, 0x0000} } }, 552 { 92500000, { {0x0140, 0x0005}, {0x2141, 0x0005}, {0x4142, 0x0005} } }, 553 { 148500000, { {0x00a0, 0x000a}, {0x20a1, 0x000a}, {0x40a2, 0x000a} } }, 554 { 216000000, { {0x00a0, 0x000a}, {0x2001, 0x000f}, {0x4002, 0x000f} } }, 555 { ~0UL, { {0x0000, 0x0000}, {0x0000, 0x0000}, {0x0000, 0x0000} } } 556 }; 557 558 static const struct Phy_curr_ctrl phy_curr_ctrl[] = { 559 // pixelclock 8bpc 10bpc 12bpc 560 { 54000000, {0x091c, 0x091c, 0x06dc} }, 561 { 58400000, {0x091c, 0x06dc, 0x06dc} }, 562 { 72000000, {0x06dc, 0x06dc, 0x091c} }, 563 { 74250000, {0x06dc, 0x0b5c, 0x091c} }, 564 { 118800000, {0x091c, 0x091c, 0x06dc} }, 565 { 216000000, {0x06dc, 0x0b5c, 0x091c} }, 566 { ~0UL, {0x0000, 0x0000, 0x0000} } 567 }; 568 569 static const struct Phy_config phy_config[] = { 570 // pixelclock symbol term vlevel 571 { 216000000, 0x800d, 0x0005, 0x01ad}, 572 { ~0UL, 0x0000, 0x0000, 0x0000} 573 }; 574 575 576 577 // Initialise the HDMI peripheral. 578 579 Hdmi_jz4780_chip::Hdmi_jz4780_chip(l4_addr_t start, l4_addr_t end, 580 l4_cap_idx_t irq, 581 struct Jz4740_lcd_panel *panel) 582 : _start(start), _end(end), _irq(irq), _panel(panel) 583 { 584 // 8-bit registers with 2-bit address shifting. 585 586 _regs = new Hw::Mmio_register_block<8>(start, 2); 587 588 // Initialise I2C state for DDC. 589 590 _segment_read = false; 591 _device_register = 0; 592 593 // Initialise I2C state for PHY initialisation. 594 595 _phy_device_register = 0; 596 597 // Initialise identifying details and capabilities of the hardware. 598 599 get_identification(); 600 601 // Reset interrupts to a minimal, enabled state. 602 603 irq_init(); 604 605 // Set up DDC and PHY communication. 606 607 i2c_init(I2c_software_reset, I2c_divider, I2c_int_config0, I2c_int_config1, 608 I2c_int_status, I2c_int_mask); 609 i2c_init(I2c_phy_software_reset, I2c_phy_divider, I2c_phy_int_config0, I2c_phy_int_config1, 610 I2c_phy_int_status, I2c_phy_int_mask); 611 612 // Enable PHY interrupts. 613 614 phy_irq_init(); 615 } 616 617 // Pixel clock frequency calculation. 618 619 unsigned long Hdmi_jz4780_chip::get_pixelclock() 620 { 621 return _pixelclock; 622 623 /* Calculated frequency, which may not be the actual pixelclock frequency... 624 625 return (_panel->line_start + _panel->width + _panel->line_end + _panel->hsync) * 626 (_panel->frame_start + _panel->height + _panel->frame_end + _panel->vsync) * 627 _panel->frame_rate; 628 */ 629 } 630 631 632 633 // Update a register by enabling/setting or disabling/clearing the given bits. 634 635 void Hdmi_jz4780_chip::reg_update(uint32_t reg, uint32_t bits, bool enable) 636 { 637 if (enable) 638 _regs[reg] = _regs[reg] | bits; 639 else 640 _regs[reg] = _regs[reg] & ~bits; 641 } 642 643 // Update a field. The bits must be shifted to coincide with the mask. 644 645 void Hdmi_jz4780_chip::reg_update_field(uint32_t reg, uint32_t mask, uint32_t bits) 646 { 647 _regs[reg] = (_regs[reg] & ~(mask)) | (bits & mask); 648 } 649 650 void Hdmi_jz4780_chip::reg_fill_field(uint32_t reg, uint32_t mask) 651 { 652 _regs[reg] = _regs[reg] | mask; 653 } 654 655 656 657 // Chipset querying. 658 659 void Hdmi_jz4780_chip::get_identification() 660 { 661 _version = (_regs[Design_id] << 8) | _regs[Revision_id]; 662 _phy_type = _regs[Config_id2]; 663 664 // Initialise a member to any matching capabilities or leave it as the "null" 665 // entry. 666 667 _phy_def = phy_capabilities; 668 669 while (_phy_def->gen && (_phy_def->type != _phy_type)) 670 _phy_def++; 671 } 672 673 void Hdmi_jz4780_chip::get_version(uint8_t *major, uint16_t *minor) 674 { 675 *major = (_version >> 12) & 0xfff; 676 *minor = _version & 0xfff; 677 } 678 679 void Hdmi_jz4780_chip::get_phy_capabilities(const struct Phy_capabilities **phy_def) 680 { 681 *phy_def = _phy_def; 682 } 683 684 685 686 // Initialisation. 687 688 void Hdmi_jz4780_chip::irq_init() 689 { 690 // Disable interrupts. 691 692 _regs[Int_mask] = _regs[Int_mask] | (Int_mask_wakeup | Int_mask_all); 693 694 // Mask all interrupts. 695 696 _regs[Fc_int_mask0] = 0xff; 697 _regs[Fc_int_mask1] = 0xff; 698 _regs[Fc_int_mask2] = 0xff; 699 _regs[As_int_mask] = 0xff; 700 _regs[Phy_int_mask] = 0xff; 701 _regs[I2c_int_mask] = 0xff; 702 _regs[I2c_phy_int_mask] = 0xff; 703 _regs[Cec_int_mask] = 0xff; 704 _regs[Vp_int_mask] = 0xff; 705 _regs[Ahb_dma_audio_int_mask] = 0xff; 706 707 // Enable interrupts. 708 709 _regs[Int_mask] = _regs[Int_mask] & ~(Int_mask_wakeup | Int_mask_all); 710 } 711 712 void Hdmi_jz4780_chip::phy_irq_init() 713 { 714 // Set PHY interrupt polarities. 715 716 _regs[Phy_polarity] = Phy_status_all; 717 718 // Enable/unmask second-level interrupts. 719 720 _regs[Phy_mask] = _regs[Phy_mask] & ~(Phy_status_all); 721 722 // Clear pending interrupts. 723 724 _regs[Phy_int_status] = Phy_int_status_all; 725 726 // Enable/unmask interrupts. 727 728 _regs[Phy_int_mask] = _regs[Phy_int_mask] & ~(Phy_int_status_all); 729 } 730 731 732 733 // I2C support. 734 735 void Hdmi_jz4780_chip::i2c_init(uint32_t reset, uint32_t divider, 736 uint32_t config0, uint32_t config1, 737 uint32_t status, uint32_t mask) 738 { 739 // Software reset. 740 741 _regs[reset] = 0; 742 743 // Standard mode (100kHz). 744 745 _regs[divider] = 0; 746 747 // Set interrupt polarities. 748 749 _regs[config0] = I2c_int_config0_done_polarity; 750 _regs[config1] = I2c_int_config1_nack_polarity | I2c_int_config1_arb_polarity; 751 752 // Clear and mask/mute interrupts. 753 754 _regs[status] = I2c_int_status_done | I2c_int_status_error; 755 _regs[mask] = I2c_int_status_done | I2c_int_status_error; 756 } 757 758 long Hdmi_jz4780_chip::i2c_wait(uint32_t status) 759 { 760 long err; 761 uint8_t int_status; 762 l4_msgtag_t tag; 763 764 do 765 { 766 tag = l4_irq_receive(_irq, L4_IPC_NEVER); 767 768 err = l4_ipc_error(tag, l4_utcb()); 769 if (err) 770 return err; 771 772 int_status = _regs[status]; 773 774 // Test for an error condition. 775 776 if (int_status & I2c_int_status_error) 777 return -L4_EIO; 778 779 // Acknowledge the interrupt. 780 781 _regs[status] = int_status; 782 783 } while (!(int_status & I2c_int_status_done)); 784 785 return L4_EOK; 786 } 787 788 int Hdmi_jz4780_chip::i2c_read(uint8_t *buf, unsigned int length) 789 { 790 unsigned int i; 791 long err; 792 793 // Unmask interrupts. 794 795 _regs[I2c_int_mask] = 0; 796 797 for (i = 0; i < length; i++) 798 { 799 // Increment the device register. 800 801 _regs[I2c_register] = _device_register++; 802 _regs[I2c_operation] = _segment_read ? I2c_operation_segment_read 803 : I2c_operation_read; 804 805 // Wait and then read. 806 807 err = i2c_wait(I2c_int_status); 808 if (err) 809 break; 810 811 buf[i] = _regs[I2c_data_in]; 812 } 813 814 // Mask interrupts again. 815 816 _regs[I2c_int_mask] = I2c_int_status_done | I2c_int_status_error; 817 818 return i; 819 } 820 821 int Hdmi_jz4780_chip::i2c_phy_write(uint8_t address, uint16_t value) 822 { 823 i2c_phy_set_address(address); 824 return i2c_phy_write(&value, 1); 825 } 826 827 int Hdmi_jz4780_chip::i2c_phy_write(uint16_t *buf, unsigned int length) 828 { 829 unsigned int i; 830 long err; 831 832 // Unmask interrupts. 833 834 _regs[I2c_phy_int_mask] = 0; 835 836 for (i = 0; i < length; i++) 837 { 838 // Increment the device register. 839 840 _regs[I2c_phy_register] = _device_register++; 841 _regs[I2c_phy_operation] = I2c_operation_write; 842 843 // Write and then wait. 844 845 _regs[I2c_phy_data_out1] = (buf[i] >> 8) & 0xff; 846 _regs[I2c_phy_data_out0] = buf[i] & 0xff; 847 848 err = i2c_wait(I2c_phy_int_status); 849 if (err) 850 break; 851 } 852 853 // Mask interrupts again. 854 855 _regs[I2c_phy_int_mask] = I2c_int_status_done | I2c_int_status_error; 856 857 return i; 858 } 859 860 void Hdmi_jz4780_chip::i2c_set_address(uint8_t address) 861 { 862 _regs[I2c_device_address] = address; 863 _segment_read = false; 864 i2c_set_register(0); 865 } 866 867 void Hdmi_jz4780_chip::i2c_phy_set_address(uint8_t address) 868 { 869 // The Linux drivers seem to set the clear field when changing the PHY device 870 // address, presumably because some manual says so. 871 872 _regs[Phy_test0] = _regs[Phy_test0] | Phy_test0_clear_mask; 873 _regs[I2c_phy_device_address] = address; 874 _regs[Phy_test0] = _regs[Phy_test0] & ~Phy_test0_clear_mask; 875 876 i2c_phy_set_register(0); 877 } 878 879 void Hdmi_jz4780_chip::i2c_set_segment(uint8_t segment) 880 { 881 _regs[I2c_segment_address] = 0x30; 882 _regs[I2c_segment_pointer] = segment; 883 _segment_read = true; 884 i2c_set_register(0); 885 } 886 887 void Hdmi_jz4780_chip::i2c_set_register(uint8_t device_register) 888 { 889 _device_register = device_register; 890 } 891 892 void Hdmi_jz4780_chip::i2c_phy_set_register(uint8_t device_register) 893 { 894 _phy_device_register = device_register; 895 } 896 897 898 899 // PHY operations. 900 901 void Hdmi_jz4780_chip::phy_enable_powerdown(bool enable) 902 { 903 reg_update(Phy_config, Phy_config_powerdown_disable, !enable); 904 } 905 906 void Hdmi_jz4780_chip::phy_enable_tmds(bool enable) 907 { 908 reg_update(Phy_config, Phy_config_tmds, enable); 909 } 910 911 void Hdmi_jz4780_chip::phy_enable_svsret(bool enable) 912 { 913 reg_update(Phy_config, Phy_config_svsret, enable); 914 } 915 916 void Hdmi_jz4780_chip::phy_enable_gen2_powerdown(bool enable) 917 { 918 reg_update(Phy_config, Phy_config_gen2_powerdown, enable); 919 } 920 921 void Hdmi_jz4780_chip::phy_enable_gen2_tx_power(bool enable) 922 { 923 reg_update(Phy_config, Phy_config_gen2_tx_power, enable); 924 } 925 926 void Hdmi_jz4780_chip::phy_enable_interface(bool enable) 927 { 928 reg_update(Phy_config, Phy_config_select_data_enable_polarity, enable); 929 reg_update(Phy_config, Phy_config_select_interface_control, !enable); 930 } 931 932 // Configure the PHY. Various things not supported by the JZ4780 PHY are ignored 933 // such as the TDMS clock ratio (dependent on HDMI 2 and content scrambling). 934 935 long Hdmi_jz4780_chip::phy_configure() 936 { 937 long err; 938 939 phy_power_off(); 940 941 if (_phy_def->svsret) 942 phy_enable_svsret(true); 943 944 phy_reset(); 945 946 _regs[Main_heac_phy_reset] = Main_heac_phy_reset_assert; 947 948 i2c_phy_set_address(I2c_phy_device_phy_gen2); 949 950 if (_phy_def->configure) 951 { 952 err = phy_configure_specific(); 953 if (err) 954 return err; 955 } 956 957 // NOTE: TMDS clock delay here in Linux driver. 958 959 phy_power_on(); 960 961 return L4_EOK; 962 } 963 964 // Configure for the JZ4780 specifically. 965 966 long Hdmi_jz4780_chip::phy_configure_specific() 967 { 968 const struct Phy_mpll_config *m = phy_mpll_config; 969 const struct Phy_curr_ctrl *c = phy_curr_ctrl; 970 const struct Phy_config *p = phy_config; 971 unsigned long pixelclock = get_pixelclock(); 972 973 // Find MPLL, CURR_CTRL and PHY configuration settings appropriate for the 974 // pixel clock frequency. 975 976 while (m->pixelclock && (pixelclock > m->pixelclock)) 977 m++; 978 979 while (c->pixelclock && (pixelclock > c->pixelclock)) 980 c++; 981 982 while (p->pixelclock && (pixelclock > p->pixelclock)) 983 p++; 984 985 printf("MPLL for %ld; CURR_CTRL for %ld; PHY for %ld\n", m->pixelclock, c->pixelclock, p->pixelclock); 986 987 if (!m->pixelclock || !c->pixelclock || !p->pixelclock) 988 return -L4_EINVAL; 989 990 // Using values for 8bpc from the tables. 991 992 // Initialise MPLL. 993 994 i2c_phy_write(I2c_phy_3d_tx_cpce_ctrl, m->res[Phy_resolution_8bpc].cpce); 995 i2c_phy_write(I2c_phy_3d_tx_gmp_ctrl, m->res[Phy_resolution_8bpc].gmp); 996 997 // Initialise CURRCTRL. 998 999 i2c_phy_write(I2c_phy_3d_tx_cpce_ctrl, c->curr[Phy_resolution_8bpc]); 1000 1001 // Initialise PHY_CONFIG. 1002 1003 i2c_phy_write(I2c_phy_3d_tx_pll_phby_ctrl, 0); 1004 i2c_phy_write(I2c_phy_3d_tx_msm_ctrl, Msm_ctrl_clock_output_select_fb); 1005 1006 i2c_phy_write(I2c_phy_3d_tx_term, p->term); 1007 i2c_phy_write(I2c_phy_3d_tx_clock_symbol_ctrl, p->symbol); 1008 i2c_phy_write(I2c_phy_3d_tx_vlevel_ctrl, p->vlevel); 1009 1010 // Override and disable clock termination. 1011 1012 i2c_phy_write(I2c_phy_3d_tx_clock_cal_ctrl, Clock_cal_ctrl_override); 1013 1014 return L4_EOK; 1015 } 1016 1017 long Hdmi_jz4780_chip::phy_init() 1018 { 1019 printf("phy_init...\n"); 1020 1021 long err; 1022 int i; 1023 1024 // Initialisation repeated for HDMI PHY specification reasons. 1025 1026 for (i = 0; i < 2; i++) 1027 { 1028 phy_enable_interface(true); 1029 err = phy_configure(); 1030 if (err) 1031 return err; 1032 } 1033 1034 return L4_EOK; 1035 } 1036 1037 void Hdmi_jz4780_chip::phy_reset() 1038 { 1039 _regs[Main_reset] = 1; 1040 _regs[Main_reset] = 0; 1041 } 1042 1043 void Hdmi_jz4780_chip::phy_power_off() 1044 { 1045 printf("phy_power_off...\n"); 1046 1047 if (_phy_def && (_phy_def->gen == 1)) 1048 { 1049 phy_enable_tmds(false); 1050 phy_enable_powerdown(true); 1051 return; 1052 } 1053 1054 phy_enable_gen2_tx_power(false); 1055 1056 wait_for_tx_phy_lock(0); 1057 1058 phy_enable_gen2_powerdown(true); 1059 } 1060 1061 void Hdmi_jz4780_chip::phy_power_on() 1062 { 1063 printf("phy_power_on...\n"); 1064 1065 if (_phy_def && (_phy_def->gen == 1)) 1066 { 1067 phy_enable_powerdown(false); 1068 phy_enable_tmds(false); 1069 phy_enable_tmds(true); 1070 return; 1071 } 1072 1073 phy_enable_gen2_tx_power(true); 1074 phy_enable_gen2_powerdown(false); 1075 1076 wait_for_tx_phy_lock(1); 1077 } 1078 1079 1080 1081 // Hotplug detection. 1082 1083 bool Hdmi_jz4780_chip::connected() 1084 { 1085 return (_regs[Phy_status] & Phy_status_hotplug_detect) != 0; 1086 } 1087 1088 long Hdmi_jz4780_chip::wait_for_connection() 1089 { 1090 return wait_for_phy_irq(Phy_int_status_hotplug_detect, Phy_status_hotplug_detect, 1091 Phy_status_hotplug_detect); 1092 } 1093 1094 // General PHY interrupt handling. 1095 1096 long Hdmi_jz4780_chip::wait_for_phy_irq(uint32_t int_status_flags, 1097 uint32_t status_flags, 1098 uint32_t status_values) 1099 { 1100 long err; 1101 uint8_t int_status, status; 1102 uint8_t status_unchanged = ~(status_values) & status_flags; 1103 l4_msgtag_t tag; 1104 1105 do 1106 { 1107 tag = l4_irq_receive(_irq, L4_IPC_NEVER); 1108 1109 err = l4_ipc_error(tag, l4_utcb()); 1110 if (err) 1111 return err; 1112 1113 // Obtain the details. 1114 1115 int_status = _regs[Phy_int_status]; 1116 status = _regs[Phy_status]; 1117 1118 // Acknowledge the interrupt. 1119 1120 _regs[Phy_int_status] = int_status_flags; 1121 1122 // Continue without a handled event. 1123 // An event is handled when detected and when the status differs from 1124 // the unchanged state. 1125 1126 printf("Status: %x versus %x\n", status & status_flags, status_unchanged); 1127 1128 } while (!((int_status & int_status_flags) && 1129 ((status & status_flags) ^ status_unchanged))); 1130 1131 return L4_EOK; 1132 } 1133 1134 // Wait for TX_PHY_LOCK to become high or low. 1135 1136 long Hdmi_jz4780_chip::wait_for_tx_phy_lock(int level) 1137 { 1138 if (!!(_regs[Phy_status] & Phy_status_tx_phy_lock) == level) 1139 return L4_EOK; 1140 1141 return wait_for_phy_irq(Phy_int_status_tx_phy_lock, Phy_status_tx_phy_lock, 1142 level ? Phy_status_tx_phy_lock : Phy_status_none); 1143 } 1144 1145 1146 1147 // Output setup operations. 1148 1149 long Hdmi_jz4780_chip::enable(unsigned long pixelclock) 1150 { 1151 _pixelclock = pixelclock; 1152 1153 // Disable frame composer overflow interrupts. 1154 1155 enable_overflow_irq(false); 1156 1157 // NOTE: Here, CEA modes are normally detected and thus the output encoding. 1158 // NOTE: Instead, a fixed RGB output encoding and format is used. 1159 // NOTE: Meanwhile, the input encoding and format will also be fixed to a RGB 1160 // NOTE: representation. 1161 1162 // _bits_per_channel = 8; 1163 // _data_enable_polarity = true; 1164 1165 // HDMI initialisation "step B.1": video frame initialisation. 1166 1167 frame_init(); 1168 1169 // HDMI initialisation "step B.2": PHY initialisation. 1170 1171 long err = phy_init(); 1172 if (err) 1173 return err; 1174 1175 // HDMI initialisation "step B.3": video signal initialisation. 1176 1177 data_path_init(); 1178 1179 // With audio, various clock updates are needed. 1180 1181 // NOTE: DVI mode is being assumed for now, for simplicity. 1182 1183 // In non-DVI mode, the AVI, vendor-specific infoframe and regular infoframe 1184 // are set up. 1185 1186 packet_init(); 1187 csc_init(); 1188 sample_init(); 1189 hdcp_init(); 1190 1191 // Enable frame composer overflow interrupts. 1192 1193 enable_overflow_irq(true); 1194 1195 return L4_EOK; 1196 } 1197 1198 void Hdmi_jz4780_chip::enable_overflow_irq(bool enable) 1199 { 1200 if (!enable) 1201 reg_update(Fc_int_mask2, Fc_int_status2_overflow, !enable); 1202 1203 // Apparent workaround required. 1204 1205 else 1206 { 1207 uint8_t config = _regs[Fc_video_config]; 1208 1209 _regs[Main_software_reset] = ~(Main_software_reset_tmds); 1210 1211 for (int i = 0; i < 4; i++) 1212 _regs[Fc_video_config] = config; 1213 } 1214 } 1215 1216 void Hdmi_jz4780_chip::frame_init() 1217 { 1218 printf("frame_init...\n"); 1219 1220 // Initialise the video configuration. This is rather like the initialisation 1221 // of the LCD controller. The sync and data enable polarities are set up, plus 1222 // extras like HDCP, DVI mode, progressive/interlace. 1223 // NOTE: Here, the JZ4740-specific configuration is used to store the picture 1224 // NOTE: properties, but a neutral structure should be adopted. 1225 1226 uint8_t config = 0; 1227 1228 config |= (_panel->config & Jz4740_lcd_hsync_negative) 1229 ? Fc_video_config_hsync_active_low 1230 : Fc_video_config_hsync_active_high; 1231 1232 config |= (_panel->config & Jz4740_lcd_vsync_negative) 1233 ? Fc_video_config_vsync_active_low 1234 : Fc_video_config_vsync_active_high; 1235 1236 config |= (_panel->config & Jz4740_lcd_de_negative) 1237 ? Fc_video_config_data_enable_active_low 1238 : Fc_video_config_data_enable_active_high; 1239 1240 // NOTE: Only supporting DVI mode so far. 1241 1242 config |= Fc_video_config_dvi_mode; 1243 1244 // NOTE: Not supporting HDCP. 1245 1246 config |= Fc_video_config_hdcp_keepout_inactive; 1247 1248 // NOTE: Only supporting progressive scan so far. 1249 1250 config |= Fc_video_config_progressive; 1251 config |= Fc_video_config_osc_active_low; 1252 1253 _regs[Fc_video_config] = config; 1254 1255 printf("Fc_video_config (%x) = %x\n", Fc_video_config, (uint8_t) _regs[Fc_video_config]); 1256 1257 // Then, the frame characteristics (visible area, sync pulse) are set. Indeed, 1258 // the frame area details should be practically the same as those used by the 1259 // LCD controller. 1260 1261 uint16_t hblank = _panel->line_start + _panel->line_end + _panel->hsync, 1262 vblank = _panel->frame_start + _panel->frame_end + _panel->vsync, 1263 hsync_delay = _panel->line_end, 1264 vsync_delay = _panel->frame_end, 1265 hsync_width = _panel->hsync, 1266 vsync_height = _panel->vsync; 1267 1268 _regs[Fc_horizontal_active_width1] = (_panel->width >> 8) & 0xff; 1269 _regs[Fc_horizontal_active_width0] = _panel->width & 0xff; 1270 1271 _regs[Fc_horizontal_blank_width1] = (hblank >> 8) & 0xff; 1272 _regs[Fc_horizontal_blank_width0] = hblank & 0xff; 1273 1274 _regs[Fc_vertical_active_height1] = (_panel->height >> 8) & 0xff; 1275 _regs[Fc_vertical_active_height0] = _panel->height & 0xff; 1276 1277 _regs[Fc_vertical_blank_height] = vblank & 0xff; 1278 1279 _regs[Fc_hsync_delay1] = (hsync_delay >> 8) & 0xff; 1280 _regs[Fc_hsync_delay0] = hsync_delay & 0xff; 1281 1282 _regs[Fc_vsync_delay] = vsync_delay & 0xff; 1283 1284 _regs[Fc_hsync_width1] = (hsync_width >> 8) & 0xff; 1285 _regs[Fc_hsync_width0] = hsync_width & 0xff; 1286 1287 _regs[Fc_vsync_height] = vsync_height & 0xff; 1288 } 1289 1290 void Hdmi_jz4780_chip::data_path_init() 1291 { 1292 printf("data_path_init...\n"); 1293 1294 // Initialise the path of the video data. Here, the elements of the data 1295 // stream are defined such as the control period duration, data channel 1296 // characteristics, pixel and TMDS clocks, and the involvement of colour space 1297 // conversion. 1298 1299 // Control period minimum duration. 1300 1301 _regs[Fc_control_duration] = 12; 1302 _regs[Fc_ex_control_duration] = 32; 1303 _regs[Fc_ex_control_space] = 1; 1304 1305 // Set to fill TMDS data channels. 1306 1307 _regs[Fc_channel0_preamble] = 0x0b; 1308 _regs[Fc_channel1_preamble] = 0x16; 1309 _regs[Fc_channel2_preamble] = 0x21; 1310 1311 // Apparent two-stage clock activation. 1312 1313 uint8_t clock_disable = Main_clock_disable_hdcp | 1314 Main_clock_disable_csc | 1315 Main_clock_disable_audio | 1316 Main_clock_disable_prep | 1317 Main_clock_disable_tmds; 1318 1319 // Activate the pixel clock. 1320 1321 _regs[Main_clock_disable] = clock_disable; 1322 1323 // Then activate the TMDS clock. 1324 1325 clock_disable &= ~(Main_clock_disable_tmds); 1326 _regs[Main_clock_disable] = clock_disable; 1327 1328 // NOTE: Bypass colour space conversion for now. 1329 1330 _regs[Main_flow_control] = Main_flow_control_csc_inactive; 1331 } 1332 1333 void Hdmi_jz4780_chip::packet_init() 1334 { 1335 printf("packet_init...\n"); 1336 1337 // Initialise the video packet details. 1338 // NOTE: With 24bpp RGB output only for now, no pixel repetition. 1339 1340 int colour_depth = 4; 1341 1342 _regs[Packet_pr_cd] = 1343 ((colour_depth << Packet_pr_cd_depth_offset) & 1344 Packet_pr_cd_depth_mask); 1345 1346 _regs[Packet_remap] = Packet_remap_ycc422_16bit; 1347 1348 reg_fill_field(Packet_stuffing, Packet_stuffing_pr | 1349 Packet_stuffing_default_phase | 1350 Packet_stuffing_pp | 1351 Packet_stuffing_ycc422); 1352 1353 // Disable pixel repeater. 1354 1355 reg_update_field(Packet_config, Packet_config_bypass_enable | 1356 Packet_config_pr_enable | 1357 Packet_config_pp_enable | 1358 Packet_config_ycc422_enable | 1359 Packet_config_bypass_select_packetizer | 1360 Packet_config_output_selector_mask, 1361 Packet_config_bypass_enable | 1362 Packet_config_bypass_select_packetizer | 1363 Packet_config_output_selector_bypass); 1364 } 1365 1366 void Hdmi_jz4780_chip::csc_init() 1367 { 1368 printf("csc_init...\n"); 1369 1370 // Initialise the colour space conversion details. 1371 // NOTE: No conversion will be done yet (see data_path_init). 1372 1373 _regs[Csc_config] = Csc_config_interpolation_disable | 1374 Csc_config_decimation_disable; 1375 1376 // NOTE: Use 8bpc (24bpp) for now. 1377 1378 reg_update_field(Csc_scale, Csc_scale_colour_depth_mask, Csc_scale_colour_depth_24bpp); 1379 1380 // NOTE: Coefficients should be set here. 1381 } 1382 1383 void Hdmi_jz4780_chip::sample_init() 1384 { 1385 printf("sample_init...\n"); 1386 1387 // Initialise the mapping of video input data. 1388 // NOTE: With 24bpp RGB input only for now. 1389 1390 int colour_format = 0x01; 1391 1392 // Data enable inactive. 1393 1394 _regs[Sample_video_config] = (colour_format & Sample_video_config_mapping_mask); 1395 1396 // Transmission stuffing when data enable is inactive. 1397 1398 _regs[Sample_video_stuffing] = Sample_video_stuffing_bdb_data | 1399 Sample_video_stuffing_rcr_data | 1400 Sample_video_stuffing_gy_data; 1401 1402 _regs[Sample_gy_data0] = 0; 1403 _regs[Sample_gy_data1] = 0; 1404 _regs[Sample_rcr_data0] = 0; 1405 _regs[Sample_rcr_data1] = 0; 1406 _regs[Sample_bcb_data0] = 0; 1407 _regs[Sample_bcb_data1] = 0; 1408 } 1409 1410 void Hdmi_jz4780_chip::hdcp_init() 1411 { 1412 printf("hdcp_init...\n"); 1413 1414 // Initialise HDCP registers, mostly turning things off. 1415 1416 reg_update(Hdcp_config0, Hdcp_config0_rxdetect_enable, false); 1417 1418 reg_update(Hdcp_video_polarity, 1419 Hdcp_video_polarity_data_enable_active_high, 1420 !(_panel->config & Jz4740_lcd_de_negative)); 1421 1422 reg_update(Hdcp_config1, Hdcp_config1_encryption_disable, true); 1423 } 1424 1425 1426 1427 // C language interface functions. 1428 1429 void *jz4780_hdmi_init(l4_addr_t start, l4_addr_t end, l4_cap_idx_t irq, 1430 struct Jz4740_lcd_panel *panel) 1431 { 1432 return (void *) new Hdmi_jz4780_chip(start, end, irq, panel); 1433 } 1434 1435 void jz4780_hdmi_get_version(void *hdmi, uint8_t *major, uint16_t *minor) 1436 { 1437 static_cast<Hdmi_jz4780_chip *>(hdmi)->get_version(major, minor); 1438 } 1439 1440 void jz4780_hdmi_get_phy_capabilities(void *hdmi, const struct Phy_capabilities **phy_def) 1441 { 1442 static_cast<Hdmi_jz4780_chip *>(hdmi)->get_phy_capabilities(phy_def); 1443 } 1444 1445 int jz4780_hdmi_i2c_read(void *hdmi, uint8_t *buf, unsigned int length) 1446 { 1447 return static_cast<Hdmi_jz4780_chip *>(hdmi)->i2c_read(buf, length); 1448 } 1449 1450 void jz4780_hdmi_i2c_set_address(void *hdmi, uint8_t address) 1451 { 1452 static_cast<Hdmi_jz4780_chip *>(hdmi)->i2c_set_address(address); 1453 } 1454 1455 void jz4780_hdmi_i2c_set_segment(void *hdmi, uint8_t segment) 1456 { 1457 static_cast<Hdmi_jz4780_chip *>(hdmi)->i2c_set_segment(segment); 1458 } 1459 1460 void jz4780_hdmi_i2c_set_register(void *hdmi, uint8_t device_register) 1461 { 1462 static_cast<Hdmi_jz4780_chip *>(hdmi)->i2c_set_register(device_register); 1463 } 1464 1465 int jz4780_hdmi_connected(void *hdmi) 1466 { 1467 return (int) static_cast<Hdmi_jz4780_chip *>(hdmi)->connected(); 1468 } 1469 1470 long jz4780_hdmi_wait_for_connection(void *hdmi) 1471 { 1472 return static_cast<Hdmi_jz4780_chip *>(hdmi)->wait_for_connection(); 1473 } 1474 1475 long jz4780_hdmi_enable(void *hdmi, unsigned long pixelclock) 1476 { 1477 return static_cast<Hdmi_jz4780_chip *>(hdmi)->enable(pixelclock); 1478 }