1 /* 2 * CPM (clock and power management) support for the JZ4730. 3 * 4 * Copyright (C) 2017, 2018, 2020, 2021 Paul Boddie <paul@boddie.org.uk> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 19 * Boston, MA 02110-1301, USA 20 */ 21 22 #pragma once 23 24 #include "cpm.h" 25 26 #include <l4/sys/types.h> 27 #include <stdint.h> 28 29 30 31 #ifdef __cplusplus 32 33 #include <l4/devices/hw_register_block.h> 34 35 /* A simple abstraction for accessing the CPM registers. 36 * A proper device could inherit from Hw::Device and use an 37 * Int_property for _exclk_freq. */ 38 39 class Cpm_jz4730_chip : public Cpm_chip 40 { 41 private: 42 Hw::Register_block<32> _regs; 43 uint32_t _exclk_freq; 44 45 int pll_enabled(); 46 int pll_bypassed(); 47 48 // Clock control. 49 50 uint32_t get_clock_gate_value(enum Clock_identifiers clock); 51 52 public: 53 Cpm_jz4730_chip(l4_addr_t addr, uint32_t exclk_freq); 54 55 int have_pll(); 56 57 uint16_t get_multiplier(); 58 uint8_t get_input_division(); 59 uint8_t get_output_division(); 60 61 uint8_t _get_divider(uint32_t reg, uint32_t mask, uint8_t shift); 62 uint8_t get_cpu_divider(); 63 uint8_t get_hclock_divider(); 64 uint8_t get_pclock_divider(); 65 uint8_t get_memory_divider(); 66 uint8_t get_source_divider(); 67 68 uint16_t get_lcd_pixel_divider(); 69 uint32_t get_lcd_pixel_frequency(); 70 71 void set_lcd_device_divider(uint8_t division); 72 void set_lcd_pixel_divider(uint16_t division); 73 void set_lcd_frequencies(uint32_t pclk, uint8_t ratio); 74 75 int have_clock(enum Clock_identifiers clock); 76 void start_clock(enum Clock_identifiers clock); 77 void stop_clock(enum Clock_identifiers clock); 78 79 uint32_t get_pll_frequency(); 80 uint32_t get_output_frequency(); 81 void update_output_frequency(); 82 83 uint32_t get_cpu_frequency(); 84 uint32_t get_hclock_frequency(); 85 uint32_t get_pclock_frequency(); 86 uint32_t get_memory_frequency(); 87 }; 88 89 #endif /* __cplusplus */ 90 91 92 93 /* C language interface. */ 94 95 EXTERN_C_BEGIN 96 97 void *jz4730_cpm_init(l4_addr_t cpm_base); 98 99 int jz4730_cpm_have_pll(void *cpm); 100 101 int jz4730_cpm_have_clock(void *cpm, enum Clock_identifiers clock); 102 void jz4730_cpm_start_clock(void *cpm, enum Clock_identifiers clock); 103 void jz4730_cpm_stop_clock(void *cpm, enum Clock_identifiers clock); 104 105 uint16_t jz4730_cpm_get_lcd_pixel_divider(void *cpm); 106 uint32_t jz4730_cpm_get_lcd_pixel_frequency(void *cpm); 107 108 void jz4730_cpm_set_lcd_frequencies(void *cpm, uint32_t pclk, uint8_t ratio); 109 void jz4730_cpm_update_output_frequency(void *cpm); 110 111 uint32_t jz4730_cpm_get_cpu_frequency(void *cpm); 112 uint32_t jz4730_cpm_get_hclock_frequency(void *cpm); 113 uint32_t jz4730_cpm_get_output_frequency(void *cpm); 114 uint32_t jz4730_cpm_get_pclock_frequency(void *cpm); 115 uint32_t jz4730_cpm_get_memory_frequency(void *cpm); 116 117 EXTERN_C_END