1 /* 2 * I2C support for the JZ4780. 3 * 4 * Copyright (C) 2017, 2018, 2021 Paul Boddie <paul@boddie.org.uk> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 19 * Boston, MA 02110-1301, USA 20 */ 21 22 #include <l4/devices/i2c-jz4780.h> 23 #include <l4/devices/hw_mmio_register_block.h> 24 25 #include <l4/sys/icu.h> 26 #include <l4/util/util.h> 27 #include <sys/time.h> 28 29 #include <cstdio> 30 31 /* 32 I2C pins: 33 34 I2C0: PD30/SMB0_SDA, PD31/SMB0_SCK 35 I2C1: PD30/SMB1_SDA, PD31/SMB1_SCK (pulled up on CI20) 36 I2C2: PF16/SMB2_SDA, PF17/SMB2_SCK 37 PWM: PD10/SMB3_SDA, PD11/SMB3_SCK 38 PWM: PE3/SMB4_SDA, PE4/SMB4_SCK 39 I2C4: PE12/SMB4_SDA, PE13/SMB4_SCK 40 HDMI: PF25/SMB4_SDA/DDCSDA, PF24/SMB4_SCK/DDCSCK 41 42 See: http://mipscreator.imgtec.com/CI20/hardware/board/ci20_jz4780_v2.0.pdf 43 */ 44 45 enum Regs 46 { 47 Smb_control = 0x000, // SMBCON 48 Smb_target_address = 0x004, // SMBTAR 49 Smb_slave_address = 0x008, // SMBSAR 50 Smb_data_command = 0x010, // SMBDC 51 Std_high_count = 0x014, // SMBSHCNT 52 Std_low_count = 0x018, // SMBSLCNT 53 Fast_high_count = 0x01c, // SMBFHCNT 54 Fast_low_count = 0x020, // SMBFLCNT 55 Int_status = 0x02c, // SMBINTST (read-only) 56 Int_mask = 0x030, // SMBINTM 57 58 Rx_fifo_thold = 0x038, // SMBRXTL 59 Tx_fifo_thold = 0x03c, // SMBTXTL 60 Int_combined_clear = 0x040, // SMBCINT (read-only) 61 Int_rx_uf_clear = 0x044, // SMBCRXUF (read-only) 62 Int_rx_of_clear = 0x048, // SMBCRXOF (read-only) 63 Int_tx_of_clear = 0x04c, // SMBCTXOF (read-only) 64 Int_rd_req_clear = 0x050, // SMBCRXREQ (read-only) 65 Int_tx_abort_clear = 0x054, // SMBCTXABT (read-only) 66 Int_rx_done_clear = 0x058, // SMBCRXDN (read-only) 67 Int_activity_clear = 0x05c, // SMBCACT (read-only) 68 Int_stop_clear = 0x060, // SMBCSTP (read-only) 69 Int_start_clear = 0x064, // SMBCSTT (read-only) 70 Int_call_clear = 0x068, // SMBCGC (read-only) 71 Smb_enable = 0x06c, // SMBENB 72 Smb_status = 0x070, // SMBST (read-only) 73 74 Tx_fifo_count = 0x074, // SMBTXFLR (read-only) 75 Rx_fifo_count = 0x078, // SMBRXFLR (read-only) 76 77 Trans_abort_status0 = 0x080, // SMBABTSRC (read-only) 78 Trans_abort_status1 = 0x084, // ... (read-only) 79 80 Smb_dma_ctrl = 0x088, // SMBDMACR 81 Smb_trans_data_lvl = 0x08c, // SMBDMATDLR 82 Smb_recv_data_lvl = 0x090, // SMBDMARDLR 83 Smb_sda_setup_time = 0x094, // SMBSDASU 84 Smb_ack_call = 0x098, // SMBACKGC 85 86 Smb_enable_status = 0x09c, // SMBENBST (read-only) 87 Smb_sda_hold_time = 0x0d0, // SMBSDAHD 88 89 Smb_block_offset = 0x1000 90 }; 91 92 enum Smb_control_bits : unsigned 93 { 94 Smb_no_stop_empty = 0x80, // STPHLD (no STP condition when queue empty) 95 Smb_disable_slave = 0x40, // SLVDIS (slave disabled) 96 Smb_enable_restart = 0x20, // REST 97 Smb_enable_master = 0x01, // MD (master enabled) 98 Smb_speed_bit = 1, // SPD 99 }; 100 101 enum Smb_enable_bits : unsigned 102 { 103 Smb_enable_enabled = 0x01, // SMBEN 104 }; 105 106 enum Smb_status_bits : unsigned 107 { 108 Smb_status_master_act = 0x20, // MSTACT (master active) 109 Smb_status_rx_nempty = 0x08, // RFNE (read queue not empty) 110 Smb_status_tx_empty = 0x04, // TFE (write queue empty) 111 Smb_status_tx_nfull = 0x02, // TFNF (write queue not full) 112 Smb_status_active = 0x01, // ACT (device active as master or slave) 113 }; 114 115 enum Smb_target_bits : unsigned 116 { 117 Smb_target_7bits = 0x7f, 118 }; 119 120 enum Smb_hold_control_bits : unsigned 121 { 122 Smb_hold_enable = 0x100, // HDENB 123 Smb_hold_disable = 0x000, // HDENB 124 Smb_hold_mask = 0x1ff, 125 }; 126 127 enum Smb_setup_control_bits : unsigned 128 { 129 Smb_setup_mask = 0x0ff, 130 }; 131 132 enum Smb_command_bits : unsigned 133 { 134 Smb_command_read = 0x100, // CMD 135 Smb_command_write = 0x000, // CMD 136 }; 137 138 enum Smb_fifo_bits : unsigned 139 { 140 Smb_fifo_limit = 16, 141 }; 142 143 enum Int_bits : unsigned 144 { 145 Int_call = 0x800, // IGC (general call received) 146 Int_start = 0x400, // ISTT (start/restart condition occurred) 147 Int_stop = 0x200, // ISTP (stop condition occurred) 148 Int_activity = 0x100, // IACT (bus activity interrupt) 149 Int_rx_done = 0x080, // RXDN (read from master device done) 150 Int_tx_abort = 0x040, // TXABT (transmit abort) 151 Int_rd_req = 0x020, // RDREQ (read request from master device) 152 Int_tx_empty = 0x010, // TXEMP (threshold reached or passed) 153 Int_tx_of = 0x008, // TXOF (overflow when writing to queue) 154 Int_rx_full = 0x004, // RXFL (threshold reached or exceeded) 155 Int_rx_of = 0x002, // RXOF (overflow from device) 156 Int_rx_uf = 0x001, // RXUF (underflow when reading from queue) 157 }; 158 159 160 161 // Initialise a channel. 162 163 I2c_jz4780_channel::I2c_jz4780_channel(l4_addr_t start, 164 Cpm_jz4780_chip *cpm, 165 uint32_t frequency) 166 : _cpm(cpm), _frequency(frequency) 167 { 168 _regs = new Hw::Mmio_register_block<32>(start); 169 } 170 171 // Enable the channel. 172 173 void 174 I2c_jz4780_channel::enable() 175 { 176 _regs[Smb_enable] = Smb_enable_enabled; 177 while (!(_regs[Smb_enable_status] & Smb_enable_enabled)); 178 } 179 180 // Disable the channel. 181 182 void 183 I2c_jz4780_channel::disable() 184 { 185 _regs[Smb_enable] = 0; 186 while (_regs[Smb_enable_status] & Smb_enable_enabled); 187 } 188 189 // Set the frequency-related peripheral parameters. 190 191 void 192 I2c_jz4780_channel::set_frequency() 193 { 194 // The APB clock (PCLK) is used to drive I2C transfers. Its value must be 195 // obtained from the CPM unit. It is known as SMB_CLK here and is scaled to 196 // kHz in order to keep the numbers easily representable, as is the bus 197 // frequency. 198 199 uint32_t smb_clk = _cpm->get_pclock_frequency() / 1000; 200 uint32_t i2c_clk = _frequency / 1000; 201 unsigned int speed = (i2c_clk <= 100) ? 1 : 2; 202 203 _regs[Smb_control] = _regs[Smb_control] | (speed << Smb_speed_bit) | 204 Smb_disable_slave | 205 Smb_enable_restart | 206 Smb_enable_master; 207 208 // According to the programming manual, if the PCLK period is T{SMB_CLK} 209 // then the I2C clock period is... 210 211 // T{SCL} = T{SCL_high} + T{SCL_low} 212 213 // Where... 214 215 // T{SCL_low} = T{SMB_CLK} * (#cycles for low signal) 216 // T{SCL_high} = T{SMB_CLK} * (#cycles for high signal) 217 218 // Since, with minimum periods being defined... 219 220 // T{SCL} >= T{min_SCL} 221 // T{SCL_low} >= T{min_SCL_low} 222 // T{SCL_high} >= T{min_SCL_high} 223 // T{min_SCL} = T{min_SCL_low} + T{min_SCL_high} 224 225 // Then the following applies... 226 227 // T{SMB_CLK} * (#cycles for low signal)) >= T{min_SCL_low} 228 // T{SMB_CLK} * (#cycles for high signal) >= T{min_SCL_high} 229 230 // To work with different clock speeds while maintaining the low-to-high 231 // ratios: 232 233 // T{min_SCL_low} = T{min_SCL} * T{min_SCL_low} / T{min_SCL} 234 // = T{min_SCL} * (T{min_SCL_low} / (T{min_SCL_low} + T{min_SCL_high})) 235 236 // T{min_SCL_high} = T{min_SCL} * T{min_SCL_high} / T{min_SCL} 237 // = T{min_SCL} * (T{min_SCL_high} / (T{min_SCL_low} + T{min_SCL_high})) 238 239 // Constraints are given with respect to the high and low count registers. 240 241 // #cycles for high signal = SMBxHCNT + 8 242 // #cycles for low signal = SMBxLCNT + 1 243 244 // From earlier, this yields... 245 246 // T{SMB_CLK} * (SMBxLCNT + 1) >= T{min_SCL_low} 247 // T{SMB_CLK} * (SMBxHCNT + 8) >= T{min_SCL_high} 248 249 // Rearranging... 250 251 // SMBxLCNT >= (T{min_SCL_low} / T{SMB_CLK}) - 1 252 // >= T{min_SCL_low} * SMB_CLK - 1 253 254 // SMBxHCNT >= (T{min_SCL_high} / T{SMB_CLK}) - 8 255 // >= T{min_SCL_high} * SMB_CLK - 8 256 257 // Introducing the definitions for the high and low periods... 258 259 // SMBxLCNT >= T{min_SCL} * (T{min_SCL_low} / (T{min_SCL_low} + T{min_SCL_high})) * SMB_CLK - 1 260 // >= (T{min_SCL_low} / T{min_SCL}) * SMB_CLK / I2C_CLK - 1 261 262 // SMBxHCNT >= T{min_SCL} * (T{min_SCL_high} / (T{min_SCL_low} + T{min_SCL_high})) * SMB_CLK - 8 263 // >= (T{min_SCL_high} / T{min_SCL}) * SMB_CLK / I2C_CLK - 8 264 265 uint32_t high_reg, low_reg; 266 uint32_t high_count, low_count; 267 int32_t hold_count; 268 uint32_t setup_count; 269 270 // Level hold times: 271 272 // Standard Fast 273 // SCL low 4.7us 1.3us 274 // SCL high 4.0us 0.6us + 275 // SCL period 8.7us 1.9us = 276 277 if (i2c_clk <= 100) // 100 kHz 278 { 279 low_count = (smb_clk * 47) / (i2c_clk * 87) - 1; 280 high_count = (smb_clk * 40) / (i2c_clk * 87) - 8; 281 low_reg = Std_low_count; 282 high_reg = Std_high_count; 283 } 284 else 285 { 286 low_count = (smb_clk * 13) / (i2c_clk * 19) - 1; 287 high_count = (smb_clk * 6) / (i2c_clk * 19) - 8; 288 low_reg = Fast_low_count; 289 high_reg = Fast_high_count; 290 } 291 292 // Minimum counts are 8 and 6 for low and high respectively. 293 294 _regs[low_reg] = low_count < 8 ? 8 : low_count; 295 _regs[high_reg] = high_count < 6 ? 6 : high_count; 296 297 // Data hold and setup times: 298 299 // Standard Fast 300 // t{HD;DAT} 300ns 300ns 301 // t{SU;DAT} 250ns 100ns 302 303 // T{delay} = (SMBSDAHD + 1) * T{SMB_CLK} 304 // SMBSDAHD = T{delay} / T{SMB_CLK} - 1 305 // SMBSDAHD = SMB_CLK * T{delay} - 1 306 307 hold_count = (smb_clk * 300) / 1000000 - 1; 308 309 _regs[Smb_sda_hold_time] = (_regs[Smb_sda_hold_time] & ~Smb_hold_mask) | 310 (hold_count >= 0 ? Smb_hold_enable : Smb_hold_disable) | 311 (hold_count < 0 ? 0 : hold_count < 255 ? hold_count : 255); 312 313 // T{delay} = (SMBSDASU - 1) * T{SMB_CLK} 314 // SMBSDASU = T{delay} / T{SMB_CLK} + 1 315 // SMBSDASU = SMB_CLK * T{delay} + 1 316 317 if (i2c_clk <= 100) 318 setup_count = (smb_clk * 250) / 1000000 + 1; 319 else 320 setup_count = (smb_clk * 100) / 1000000 + 1; 321 322 _regs[Smb_sda_setup_time] = (_regs[Smb_sda_setup_time] & ~Smb_setup_mask) | 323 (setup_count < 255 ? setup_count : 255); 324 } 325 326 // Set the target address and enable transfer. 327 // NOTE: Only supporting 7-bit addresses currently. 328 329 void 330 I2c_jz4780_channel::set_target(uint8_t address) 331 { 332 disable(); 333 set_frequency(); 334 _regs[Smb_target_address] = address & Smb_target_7bits; 335 enable(); 336 init_parameters(); 337 } 338 339 340 341 // Reset interrupt flags upon certain conditions. 342 343 void 344 I2c_jz4780_channel::reset_flags() 345 { 346 volatile uint32_t r; 347 348 _regs[Int_mask] = 0; 349 350 // Read from the register to clear interrupts. 351 352 r = _regs[Int_combined_clear]; 353 (void) r; 354 } 355 356 // Initialise interrupt flags and queue thresholds for reading and writing. 357 358 void 359 I2c_jz4780_channel::init_parameters() 360 { 361 // Handle read queue conditions for data, write queue conditions for commands. 362 363 reset_flags(); 364 365 _regs[Int_mask] = Int_rx_full | // read condition (reading needed) 366 Int_rx_of | // abort condition 367 Int_tx_empty | // write condition (writing needed) 368 Int_tx_abort; // abort condition 369 370 _regs[Tx_fifo_thold] = 0; // write when 0 in queue 371 372 // Make sure that the stop condition does not occur automatically. 373 374 _regs[Smb_control] = _regs[Smb_control] | Smb_no_stop_empty; 375 } 376 377 378 379 // Return whether the device is active. 380 381 int 382 I2c_jz4780_channel::active() 383 { 384 return _regs[Smb_status] & Smb_status_master_act; 385 } 386 387 // Return whether data is available to receive. 388 389 int 390 I2c_jz4780_channel::have_input() 391 { 392 return _regs[Smb_status] & Smb_status_rx_nempty; 393 } 394 395 // Return whether data is queued for sending. 396 397 int 398 I2c_jz4780_channel::have_output() 399 { 400 return !(_regs[Smb_status] & Smb_status_tx_empty); 401 } 402 403 // Return whether data can be queued for sending. 404 405 int 406 I2c_jz4780_channel::can_send() 407 { 408 return _regs[Smb_status] & Smb_status_tx_nfull; 409 } 410 411 // Return whether a receive operation has failed. 412 413 int 414 I2c_jz4780_channel::read_failed() 415 { 416 return _regs[Int_status] & Int_rx_of; 417 } 418 419 // Return whether a send operation has failed. 420 421 int 422 I2c_jz4780_channel::write_failed() 423 { 424 return _regs[Int_status] & Int_tx_abort; 425 } 426 427 int 428 I2c_jz4780_channel::read_done() 429 { 430 return _pos == _total; 431 } 432 433 int 434 I2c_jz4780_channel::write_done() 435 { 436 return _reqpos == _total; 437 } 438 439 unsigned 440 I2c_jz4780_channel::have_read() 441 { 442 return _pos; 443 } 444 445 unsigned 446 I2c_jz4780_channel::have_written() 447 { 448 return _reqpos; 449 } 450 451 int 452 I2c_jz4780_channel::failed() 453 { 454 return _fail; 455 } 456 457 458 459 // Send read commands for empty queue entries. 460 461 void 462 I2c_jz4780_channel::queue_reads() 463 { 464 unsigned int remaining = _total - _reqpos; 465 unsigned int queued = _reqpos - _pos; 466 467 // Permit one more issued read request due to the behaviour of the peripheral 468 // to withhold a request unless the stop condition has been issued. 469 470 unsigned int can_queue = Smb_fifo_limit - queued + 1; 471 472 // Keep the number of reads in progress below the length of the read queue. 473 474 if (!can_queue) 475 return; 476 477 // At most, only queue as many reads as are remaining. 478 479 if (remaining < can_queue) 480 can_queue = remaining; 481 482 // Queue read requests for any remaining queue entries. 483 484 while (can_queue && can_send()) 485 { 486 _regs[Smb_data_command] = Smb_command_read; 487 _reqpos++; 488 can_queue--; 489 } 490 491 // Issue the stop condition after the final read request. 492 // In practice, an extra read request works better since it does not risk a 493 // transmission abort condition and would permit following transactions. 494 // However, it does risk causing an address autoincrement with some devices. 495 496 if (_total == _reqpos) 497 _regs[Smb_data_command] = Smb_command_read; 498 //stop(); 499 500 // Update the threshold to be notified of any reduced remaining amount. 501 502 set_read_threshold(); 503 } 504 505 // Send write commands for empty queue entries. 506 507 void 508 I2c_jz4780_channel::queue_writes() 509 { 510 unsigned int remaining = _total - _reqpos; 511 unsigned int can_queue = Smb_fifo_limit; 512 513 if (remaining < can_queue) 514 can_queue = remaining; 515 516 // Queue write requests for any remaining queue entries. 517 518 while (can_queue && can_send()) 519 { 520 _regs[Smb_data_command] = Smb_command_write | _buf[_reqpos]; 521 _reqpos++; 522 can_queue--; 523 } 524 } 525 526 // Store read command results from the queue. 527 528 void 529 I2c_jz4780_channel::store_reads() 530 { 531 // Read any input and store it in the buffer. 532 533 while (have_input() && (_pos < _reqpos)) 534 { 535 _buf[_pos] = _regs[Smb_data_command] & 0xff; 536 _pos++; 537 } 538 } 539 540 void 541 I2c_jz4780_channel::set_read_threshold() 542 { 543 unsigned int queued = _reqpos - _pos; 544 545 if (!queued) 546 return; 547 548 // Read all expected. 549 550 _regs[Rx_fifo_thold] = queued - 1; 551 } 552 553 // Read from the target device. 554 555 void 556 I2c_jz4780_channel::start_read(uint8_t buf[], unsigned int total) 557 { 558 _buf = buf; 559 _total = total; 560 _pos = 0; 561 _reqpos = 0; 562 _fail = 0; 563 564 set_read_threshold(); 565 } 566 567 void 568 I2c_jz4780_channel::read() 569 { 570 if (read_failed() || write_failed()) 571 { 572 _fail = 1; 573 return; 574 } 575 576 if (_regs[Int_status] & Int_rx_full) 577 store_reads(); 578 if (_regs[Int_status] & Int_tx_empty) 579 queue_reads(); 580 } 581 582 // Write to the target device. 583 584 void 585 I2c_jz4780_channel::start_write(uint8_t buf[], unsigned int total) 586 { 587 _buf = buf; 588 _total = total; 589 _reqpos = 0; 590 _fail = 0; 591 } 592 593 void 594 I2c_jz4780_channel::write() 595 { 596 if (write_failed()) 597 { 598 _fail = 1; 599 return; 600 } 601 602 if (_regs[Int_status] & Int_tx_empty) 603 queue_writes(); 604 } 605 606 // Explicitly stop communication. 607 608 void 609 I2c_jz4780_channel::stop() 610 { 611 _regs[Smb_control] = _regs[Smb_control] & ~Smb_no_stop_empty; 612 } 613 614 615 616 // Initialise the I2C controller. 617 618 I2c_jz4780_chip::I2c_jz4780_chip(l4_addr_t start, l4_addr_t end, 619 Cpm_jz4780_chip *cpm, 620 uint32_t frequency) 621 : _start(start), _end(end), _cpm(cpm), _frequency(frequency) 622 { 623 } 624 625 // Obtain a channel object. 626 627 I2c_jz4780_channel * 628 I2c_jz4780_chip::get_channel(uint8_t channel) 629 { 630 l4_addr_t block = _start + channel * Smb_block_offset; 631 enum Clock_identifiers bits[] = {Clock_smb0, Clock_smb1, Clock_smb2, Clock_smb3, Clock_smb4}; 632 633 if (channel < 5) 634 { 635 _cpm->start_clock(bits[channel]); 636 return new I2c_jz4780_channel(block, _cpm, _frequency); 637 } 638 else 639 throw -L4_EINVAL; 640 } 641 642 643 644 // C language interface functions. 645 646 void *jz4780_i2c_init(l4_addr_t start, l4_addr_t end, void *cpm, uint32_t frequency) 647 { 648 return (void *) new I2c_jz4780_chip(start, end, static_cast<Cpm_jz4780_chip *>(cpm), frequency); 649 } 650 651 void jz4780_i2c_disable(void *i2c_channel) 652 { 653 static_cast<I2c_jz4780_channel *>(i2c_channel)->disable(); 654 } 655 656 void *jz4780_i2c_get_channel(void *i2c, uint8_t channel) 657 { 658 return static_cast<I2c_jz4780_chip *>(i2c)->get_channel(channel); 659 } 660 661 void jz4780_i2c_set_target(void *i2c_channel, uint8_t addr) 662 { 663 static_cast<I2c_jz4780_channel *>(i2c_channel)->set_target(addr); 664 } 665 666 void jz4780_i2c_start_read(void *i2c_channel, uint8_t buf[], unsigned int total) 667 { 668 static_cast<I2c_jz4780_channel *>(i2c_channel)->start_read(buf, total); 669 } 670 671 void jz4780_i2c_read(void *i2c_channel) 672 { 673 static_cast<I2c_jz4780_channel *>(i2c_channel)->read(); 674 } 675 676 void jz4780_i2c_start_write(void *i2c_channel, uint8_t buf[], unsigned int total) 677 { 678 static_cast<I2c_jz4780_channel *>(i2c_channel)->start_write(buf, total); 679 } 680 681 void jz4780_i2c_write(void *i2c_channel) 682 { 683 static_cast<I2c_jz4780_channel *>(i2c_channel)->write(); 684 } 685 686 int jz4780_i2c_read_done(void *i2c_channel) 687 { 688 return static_cast<I2c_jz4780_channel *>(i2c_channel)->read_done(); 689 } 690 691 int jz4780_i2c_write_done(void *i2c_channel) 692 { 693 return static_cast<I2c_jz4780_channel *>(i2c_channel)->write_done(); 694 } 695 696 unsigned int jz4780_i2c_have_read(void *i2c_channel) 697 { 698 return static_cast<I2c_jz4780_channel *>(i2c_channel)->have_read(); 699 } 700 701 unsigned int jz4780_i2c_have_written(void *i2c_channel) 702 { 703 return static_cast<I2c_jz4780_channel *>(i2c_channel)->have_written(); 704 } 705 706 int jz4780_i2c_failed(void *i2c_channel) 707 { 708 return static_cast<I2c_jz4780_channel *>(i2c_channel)->failed(); 709 } 710 711 void jz4780_i2c_stop(void *i2c_channel) 712 { 713 static_cast<I2c_jz4780_channel *>(i2c_channel)->stop(); 714 }