1 /* 2 * DMA support for the X1600. 3 * 4 * Copyright (C) 2021, 2023, 2024 Paul Boddie <paul@boddie.org.uk> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 19 * Boston, MA 02110-1301, USA 20 */ 21 22 #include <l4/devices/dma-x1600.h> 23 #include <l4/devices/hw_mmio_register_block.h> 24 25 #include <l4/sys/icu.h> 26 #include <l4/sys/ipc.h> 27 #include <l4/sys/irq.h> 28 #include <l4/util/util.h> 29 30 #include <stdio.h> 31 32 33 34 enum Global_regs 35 { 36 Dma_control = 0x1000, // DMAC 37 Dma_irq_pending = 0x1004, // DIRQP 38 }; 39 40 enum Channel_regs 41 { 42 Dma_source = 0x00, // DSA 43 Dma_destination = 0x04, // DTA 44 Dma_transfer_count = 0x08, // DTC 45 Dma_request_source = 0x0c, // DRT 46 Dma_control_status = 0x10, // DCS 47 Dma_command = 0x14, // DCM 48 Dma_descriptor_address = 0x18, // DDA 49 Dma_stride = 0x1c, // DSD 50 }; 51 52 enum Dma_control_bits : unsigned 53 { 54 Dma_fast_msc_transfer = 0x80000000, // FMSC 55 Dma_fast_ssi_transfer = 0x40000000, // FSSI 56 Dma_fast_tssi_transfer = 0x20000000, // FTSSI 57 Dma_fast_uart_transfer = 0x10000000, // FUART 58 Dma_fast_aic_transfer = 0x08000000, // FAIC 59 Dma_control_trans_halted = 0x00000008, // HLT 60 Dma_control_address_error = 0x00000004, // AR 61 Dma_control_enable = 0x00000001, // DMAE 62 }; 63 64 enum Dma_transfer_count_bits : unsigned 65 { 66 Dma_transfer_count_mask = 0x00ffffff, 67 }; 68 69 enum Dma_request_source_bits : unsigned 70 { 71 Dma_request_type_mask = 0x0000003f, 72 }; 73 74 enum Dma_control_status_bits : unsigned 75 { 76 Dma_no_descriptor_transfer = 0x80000000, 77 Dma_8word_descriptor = 0x40000000, 78 Dma_copy_offset_mask = 0x0000ff00, 79 Dma_address_error = 0x00000010, 80 Dma_trans_completed = 0x00000008, 81 Dma_trans_halted = 0x00000004, 82 Dma_channel_enable = 0x00000001, 83 84 Dma_copy_offset_shift = 8, 85 }; 86 87 enum Dma_command_bits : unsigned 88 { 89 Dma_source_address_increment = 0x800000, 90 Dma_source_address_no_increment = 0x000000, 91 Dma_destination_address_increment = 0x400000, 92 Dma_destination_address_no_increment = 0x000000, 93 94 Dma_source_address_increment_wrap = 0x200000, 95 Dma_destination_address_increment_wrap = 0x100000, 96 Dma_recommended_data_unit_size_mask = 0x0f0000, 97 Dma_source_port_width_mask = 0x00c000, 98 Dma_destination_port_width_mask = 0x003000, 99 Dma_transfer_unit_size_mask = 0x000f00, 100 101 Dma_trans_unit_size_32_bit = 0x000000, 102 Dma_trans_unit_size_8_bit = 0x000100, 103 Dma_trans_unit_size_16_bit = 0x000200, 104 Dma_trans_unit_size_16_byte = 0x000300, 105 Dma_trans_unit_size_32_byte = 0x000400, 106 Dma_trans_unit_size_64_byte = 0x000500, 107 Dma_trans_unit_size_128_byte = 0x000600, 108 Dma_trans_unit_size_autonomous = 0x000700, 109 Dma_trans_unit_size_external = 0x000800, 110 111 Dma_source_address_compare_index = 0x000080, 112 Dma_destination_address_compare_index = 0x000040, 113 Dma_stride_enable = 0x000004, 114 Dma_transfer_irq_enable = 0x000002, 115 Dma_descriptor_link_enable = 0x000001, 116 117 Dma_recommended_data_unit_size_shift = 16, 118 Dma_source_port_width_shift = 14, 119 Dma_destination_port_width_shift = 12, 120 Dma_transfer_unit_size_shift = 8, 121 }; 122 123 enum Dma_port_width_values : unsigned 124 { 125 Dma_port_width_32_bit = 0, 126 Dma_port_width_8_bit = 1, 127 Dma_port_width_16_bit = 2, 128 }; 129 130 131 132 // Initialise a channel. 133 134 Dma_x1600_channel::Dma_x1600_channel(Dma_x1600_chip *chip, uint8_t channel, 135 l4_addr_t start, l4_cap_idx_t irq) 136 : _chip(chip), _channel(channel), _irq(irq) 137 { 138 _regs = new Hw::Mmio_register_block<32>(start); 139 140 // Initialise the transfer count. 141 142 _regs[Dma_transfer_count] = 0; 143 } 144 145 // Return the closest interval length greater than or equal to the number of 146 // units given encoded in the request detection interval length field of the 147 // control/status register. 148 149 uint32_t 150 Dma_x1600_channel::encode_req_detect_int_length(uint8_t units) 151 { 152 static uint8_t lengths[] = {0, 1, 2, 3, 4, 8, 16, 32, 64, 128}; 153 int i; 154 155 if (!units) 156 return 0; 157 158 for (i = 0; i <= 9; i++) 159 { 160 if (lengths[i] >= units) 161 break; 162 } 163 164 return i << Dma_recommended_data_unit_size_shift; 165 } 166 167 // Encode the appropriate source port width for the given request type. 168 169 uint32_t 170 Dma_x1600_channel::encode_source_port_width(uint8_t width) 171 { 172 switch (width) 173 { 174 case 1: 175 return Dma_port_width_8_bit << Dma_source_port_width_shift; 176 177 case 2: 178 return Dma_port_width_16_bit << Dma_source_port_width_shift; 179 180 default: 181 return Dma_port_width_32_bit << Dma_source_port_width_shift; 182 } 183 } 184 185 // Encode the appropriate destination port width for the given request type. 186 187 uint32_t 188 Dma_x1600_channel::encode_destination_port_width(uint8_t width) 189 { 190 switch (width) 191 { 192 case 1: 193 return Dma_port_width_8_bit << Dma_destination_port_width_shift; 194 195 case 2: 196 return Dma_port_width_16_bit << Dma_destination_port_width_shift; 197 198 default: 199 return Dma_port_width_32_bit << Dma_destination_port_width_shift; 200 } 201 } 202 203 // Encode the transfer unit size. 204 // NOTE: This does not handle the external case. 205 206 uint32_t 207 Dma_x1600_channel::encode_transfer_unit_size(uint8_t size) 208 { 209 switch (size) 210 { 211 case 0: 212 return Dma_trans_unit_size_autonomous; 213 214 case 1: 215 return Dma_trans_unit_size_8_bit; 216 217 case 2: 218 return Dma_trans_unit_size_16_bit; 219 220 case 16: 221 return Dma_trans_unit_size_16_byte; 222 223 case 32: 224 return Dma_trans_unit_size_32_byte; 225 226 case 64: 227 return Dma_trans_unit_size_64_byte; 228 229 case 128: 230 return Dma_trans_unit_size_128_byte; 231 232 default: 233 return Dma_trans_unit_size_32_bit; 234 } 235 } 236 237 // Transfer data between memory locations, returning the number of units that 238 // should have been transferred. 239 240 unsigned int 241 Dma_x1600_channel::transfer(uint32_t source, uint32_t destination, 242 unsigned int count, 243 bool source_increment, bool destination_increment, 244 uint8_t source_width, uint8_t destination_width, 245 uint8_t transfer_unit_size, 246 enum Dma_x1600_request_type type) 247 { 248 printf("transfer:%s%s%s%s\n", error() ? " error" : "", 249 halted() ? " halted" : "", 250 completed() ? " completed" : "", 251 _regs[Dma_transfer_count] ? " count" : ""); 252 253 // Ensure an absence of address error and halt conditions globally and in this channel. 254 255 if (error() || halted()) 256 return 0; 257 258 // Ensure a zero transfer count for this channel. 259 260 if (_regs[Dma_transfer_count]) 261 return 0; 262 263 // Disable the channel. 264 265 _regs[Dma_control_status] = _regs[Dma_control_status] & ~Dma_channel_enable; 266 267 // Set addresses. 268 269 _regs[Dma_source] = source; 270 _regs[Dma_destination] = destination; 271 272 // Set transfer count to the number of units. 273 274 unsigned int units = count < Dma_transfer_count_mask ? count : Dma_transfer_count_mask; 275 276 _regs[Dma_transfer_count] = units; 277 278 // Set auto-request for memory-to-memory transfers. Otherwise, set the 279 // indicated request type. 280 281 _regs[Dma_request_source] = type; 282 283 // For a descriptor, the actual fields would be populated instead of the 284 // command register, descriptor transfer would be indicated in the control/ 285 // status register along with the appropriate descriptor size indicator. 286 287 /* NOTE: To be considered... 288 * request detection interval length (for autonomous mode) 289 */ 290 291 _regs[Dma_command] = (source_increment ? Dma_source_address_increment : Dma_source_address_no_increment) | 292 (destination_increment ? Dma_destination_address_increment : Dma_destination_address_no_increment) | 293 encode_source_port_width(source_width) | 294 encode_destination_port_width(destination_width) | 295 encode_transfer_unit_size(transfer_unit_size) | 296 Dma_transfer_irq_enable; 297 298 // For a descriptor, the descriptor address would be set and the doorbell 299 // register field for the channel set. 300 301 // Enable the channel (and peripheral). 302 303 _regs[Dma_control_status] = Dma_no_descriptor_transfer | 304 Dma_channel_enable; 305 306 // Return the number of units to transfer. 307 308 return units; 309 } 310 311 // Wait for a transfer to end, returning the number of units remaining to be 312 // transferred. 313 314 unsigned int 315 Dma_x1600_channel::wait() 316 { 317 // An interrupt will occur upon completion, the completion flag will be set 318 // and the transfer count will be zero. 319 320 unsigned int remaining = 0; 321 322 do 323 { 324 if (!wait_for_irq(1000000)) 325 printf("status = %x\n", (uint32_t) _regs[Dma_control_status]); 326 else 327 { 328 printf("status = %x\n", (uint32_t) _regs[Dma_control_status]); 329 remaining = _regs[Dma_transfer_count]; 330 ack_irq(); 331 break; 332 } 333 } 334 while (!error() && !halted() && !completed()); 335 336 // Reset the channel status. 337 338 _regs[Dma_control_status] = _regs[Dma_control_status] & ~(Dma_channel_enable | 339 Dma_trans_completed | Dma_address_error | 340 Dma_trans_halted); 341 _regs[Dma_transfer_count] = 0; 342 343 return remaining; 344 } 345 346 // Wait indefinitely for an interrupt request, returning true if one was delivered. 347 348 bool 349 Dma_x1600_channel::wait_for_irq() 350 { 351 return !l4_error(l4_irq_receive(_irq, L4_IPC_NEVER)) && _chip->have_interrupt(_channel); 352 } 353 354 // Wait up to the given timeout (in microseconds) for an interrupt request, 355 // returning true if one was delivered. 356 357 bool 358 Dma_x1600_channel::wait_for_irq(unsigned int timeout) 359 { 360 return !l4_error(l4_irq_receive(_irq, l4_timeout(L4_IPC_TIMEOUT_NEVER, l4util_micros2l4to(timeout)))) && _chip->have_interrupt(_channel); 361 } 362 363 // Acknowledge an interrupt condition. 364 365 void 366 Dma_x1600_channel::ack_irq() 367 { 368 _chip->ack_irq(_channel); 369 } 370 371 // Return whether a transfer has completed. 372 373 bool 374 Dma_x1600_channel::completed() 375 { 376 return _regs[Dma_control_status] & Dma_trans_completed ? true : false; 377 } 378 379 // Return whether an address error condition has arisen. 380 381 bool 382 Dma_x1600_channel::error() 383 { 384 return _chip->error() || (_regs[Dma_control_status] & Dma_address_error ? true : false); 385 } 386 387 // Return whether a transfer has halted. 388 389 bool 390 Dma_x1600_channel::halted() 391 { 392 return _chip->halted() || (_regs[Dma_control_status] & Dma_trans_halted ? true : false); 393 } 394 395 396 397 // Initialise the I2C controller. 398 399 Dma_x1600_chip::Dma_x1600_chip(l4_addr_t start, l4_addr_t end, 400 Cpm_x1600_chip *cpm) 401 : _start(start), _end(end), _cpm(cpm) 402 { 403 _regs = new Hw::Mmio_register_block<32>(start); 404 } 405 406 // Enable the peripheral. 407 408 void 409 Dma_x1600_chip::enable() 410 { 411 // Make sure that the DMA clock is available. 412 413 _cpm->start_clock(Clock_dma); 414 415 _regs[Dma_control] = Dma_control_enable; 416 while (!(_regs[Dma_control] & Dma_control_enable)); 417 } 418 419 // Disable the channel. 420 421 void 422 Dma_x1600_chip::disable() 423 { 424 _regs[Dma_control] = 0; 425 while (_regs[Dma_control] & Dma_control_enable); 426 } 427 428 // Obtain a channel object. 429 430 Dma_x1600_channel * 431 Dma_x1600_chip::get_channel(uint8_t channel, l4_cap_idx_t irq) 432 { 433 if (channel < 32) 434 return new Dma_x1600_channel(this, channel, _start + 0x20 * channel, irq); 435 else 436 throw -L4_EINVAL; 437 } 438 439 // Return whether an interrupt is pending on the given channel. 440 441 bool 442 Dma_x1600_chip::have_interrupt(uint8_t channel) 443 { 444 return _regs[Dma_irq_pending] & (1UL << channel) ? true : false; 445 } 446 447 // Acknowledge an interrupt condition on the given channel. 448 449 void 450 Dma_x1600_chip::ack_irq(uint8_t channel) 451 { 452 _regs[Dma_irq_pending] = _regs[Dma_irq_pending] & ~(1UL << channel); 453 } 454 455 // Return whether an address error condition has arisen. 456 457 bool 458 Dma_x1600_chip::error() 459 { 460 return _regs[Dma_control] & Dma_control_address_error ? true : false; 461 } 462 463 // Return whether a transfer has halted. 464 465 bool 466 Dma_x1600_chip::halted() 467 { 468 return _regs[Dma_control] & Dma_control_trans_halted ? true : false; 469 } 470 471 472 473 // C language interface functions. 474 475 void *x1600_dma_init(l4_addr_t start, l4_addr_t end, void *cpm) 476 { 477 return (void *) new Dma_x1600_chip(start, end, static_cast<Cpm_x1600_chip *>(cpm)); 478 } 479 480 void x1600_dma_disable(void *dma_chip) 481 { 482 static_cast<Dma_x1600_chip *>(dma_chip)->disable(); 483 } 484 485 void x1600_dma_enable(void *dma_chip) 486 { 487 static_cast<Dma_x1600_chip *>(dma_chip)->enable(); 488 } 489 490 void *x1600_dma_get_channel(void *dma, uint8_t channel, l4_cap_idx_t irq) 491 { 492 return static_cast<Dma_x1600_chip *>(dma)->get_channel(channel, irq); 493 } 494 495 unsigned int x1600_dma_transfer(void *dma_channel, 496 uint32_t source, uint32_t destination, 497 unsigned int count, 498 int source_increment, int destination_increment, 499 uint8_t source_width, uint8_t destination_width, 500 uint8_t transfer_unit_size, 501 enum Dma_x1600_request_type type) 502 { 503 return static_cast<Dma_x1600_channel *>(dma_channel)->transfer(source, 504 destination, count, source_increment, destination_increment, source_width, 505 destination_width, transfer_unit_size, type); 506 } 507 508 unsigned int x1600_dma_wait(void *dma_channel) 509 { 510 return static_cast<Dma_x1600_channel *>(dma_channel)->wait(); 511 }