1 /* 2 * Clock and power management. This exposes the combined functionality 3 * provided by the jz4780 and related SoCs. The power management 4 * functionality could be exposed using a separate driver. 5 * 6 * Copyright (C) 2017, 2018, 2020, 2021, 2023, 7 * 2024 Paul Boddie <paul@boddie.org.uk> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 22 * Boston, MA 02110-1301, USA 23 */ 24 25 #include <l4/devices/hw_mmio_register_block.h> 26 #include "cpm-jz4780.h" 27 28 29 30 // Register locations. 31 32 enum Regs : unsigned 33 { 34 Clock_control = 0x000, // CPCCR 35 Low_power_control = 0x004, // LCR 36 Clock_gate0 = 0x020, // CLKGR0 37 Clock_gate1 = 0x028, // CLKGR1 38 Sleep_control = 0x024, // OPCR (oscillator and power control) 39 Clock_status = 0x0d4, // CPCSR 40 41 Divider_bch = 0x0ac, // BCHCDR 42 Divider_cim = 0x07c, // CIMCDR 43 Divider_ddr = 0x02c, // DDRCDR 44 Divider_gpu = 0x088, // GPUCDR 45 Divider_hdmi = 0x08c, // HDMICDR 46 Divider_i2s0 = 0x060, // I2SCDR 47 Divider_i2s1 = 0x0a0, // I2S1CDR 48 Divider_lcd0 = 0x054, // LP0CDR 49 Divider_lcd1 = 0x064, // LP1CDR 50 Divider_msc0 = 0x068, // MSC0CDR 51 Divider_msc1 = 0x0a4, // MSC1CDR 52 Divider_msc2 = 0x0a8, // MSC2CDR 53 Divider_pcm = 0x084, // PCMCDR 54 Divider_ssi = 0x074, // SSICDR 55 Divider_uhc = 0x06c, // UHCCDR 56 Divider_vpu = 0x030, // VPUCDR 57 58 Cpm_interrupt = 0x0b0, // CPM_INTR 59 Cpm_interrupt_en = 0x0b4, // CPM_INTRE 60 Cpm_scratch = 0x034, // CPSPR 61 Cpm_scratch_prot = 0x038, // CPSPPR 62 63 Usb_param_control0 = 0x03c, // USBPCR 64 Usb_reset_detect = 0x040, // USBRDT 65 Usb_vbus_jitter = 0x044, // USBVBFIL 66 Usb_param_control1 = 0x048, // USBPCR1 67 68 Pll_control = 0x00c, // CPPCR 69 Pll_control_A = 0x010, // CPAPCR 70 Pll_control_M = 0x014, // CPMPCR 71 Pll_control_E = 0x018, // CPEPCR 72 Pll_control_V = 0x01c, // CPVPCR 73 }; 74 75 76 77 // Register field definitions. 78 79 static Field Clock_source_main (Clock_control, 3, 30), // SEL_SRC (output to SCLK_A) 80 Clock_source_cpu (Clock_control, 3, 28), // SEL_CPLL (output to CCLK) 81 Clock_source_hclock0 (Clock_control, 3, 26), // SEL_H0PLL (output to AHB0) 82 Clock_source_hclock2 (Clock_control, 3, 24), // SEL_H2PLL (output to AHB2) 83 Clock_source_bch (Divider_bch, 3, 30), // BPCS 84 Clock_source_cim (Divider_cim, 1, 31), // CIMPCS 85 Clock_source_ddr (Divider_ddr, 3, 30), // DCS 86 Clock_source_gpu (Divider_gpu, 3, 30), // GPCS 87 Clock_source_hdmi (Divider_hdmi, 3, 30), // HPCS 88 Clock_source_i2s0 (Divider_i2s0, 3, 30), // I2CS, I2PCS 89 Clock_source_i2s1 (Divider_i2s1, 3, 30), // I2CS, I2PCS 90 Clock_source_lcd0 (Divider_lcd0, 3, 30), // LPCS 91 Clock_source_lcd1 (Divider_lcd1, 3, 30), // LPCS 92 Clock_source_msc (Divider_msc0, 3, 30), // MPCS 93 Clock_source_pcm (Divider_pcm, 7, 29), // PCMS, PCMPCS 94 Clock_source_ssi (Divider_ssi, 3, 30), // SCS, SPCS 95 Clock_source_uhc (Divider_uhc, 3, 30), // UHCS 96 Clock_source_usb_phy (Usb_param_control1, 3, 24), // REFCLKDIV 97 Clock_source_vpu (Divider_vpu, 3, 30), // VCS 98 99 Clock_busy_cpu (Clock_status, 1, 0), 100 Clock_busy_hclock0 (Clock_status, 1, 1), 101 Clock_busy_hclock2 (Clock_status, 1, 2), 102 Clock_busy_bch (Divider_bch, 1, 28), 103 Clock_busy_cim (Divider_cim, 1, 29), 104 Clock_busy_ddr (Divider_ddr, 1, 28), 105 Clock_busy_gpu (Divider_gpu, 1, 28), 106 Clock_busy_hdmi (Divider_hdmi, 1, 28), 107 Clock_busy_i2s0 (Divider_i2s0, 1, 28), 108 Clock_busy_i2s1 (Divider_i2s1, 1, 28), 109 Clock_busy_lcd0 (Divider_lcd0, 1, 27), 110 Clock_busy_lcd1 (Divider_lcd1, 1, 27), 111 Clock_busy_msc0 (Divider_msc0, 1, 28), 112 Clock_busy_msc1 (Divider_msc1, 1, 28), 113 Clock_busy_msc2 (Divider_msc2, 1, 28), 114 Clock_busy_pcm (Divider_pcm, 1, 27), 115 Clock_busy_ssi (Divider_ssi, 1, 28), 116 Clock_busy_uhc (Divider_uhc, 1, 28), 117 Clock_busy_vpu (Divider_vpu, 1, 28), 118 119 Clock_change_enable_cpu (Clock_control, 1, 22), 120 Clock_change_enable_ahb0 (Clock_control, 1, 21), 121 Clock_change_enable_ahb2 (Clock_control, 1, 20), 122 Clock_change_enable_bch (Divider_bch, 1, 29), 123 Clock_change_enable_cim (Divider_cim, 1, 30), 124 Clock_change_enable_ddr (Divider_ddr, 1, 29), 125 Clock_change_enable_gpu (Divider_gpu, 1, 29), 126 Clock_change_enable_hdmi (Divider_hdmi, 1, 29), 127 Clock_change_enable_i2s0 (Divider_i2s0, 1, 29), 128 Clock_change_enable_i2s1 (Divider_i2s1, 1, 29), 129 Clock_change_enable_lcd0 (Divider_lcd0, 1, 28), 130 Clock_change_enable_lcd1 (Divider_lcd1, 1, 28), 131 Clock_change_enable_msc0 (Divider_msc0, 1, 29), 132 Clock_change_enable_msc1 (Divider_msc1, 1, 29), 133 Clock_change_enable_msc2 (Divider_msc2, 1, 29), 134 Clock_change_enable_pcm (Divider_pcm, 1, 28), 135 Clock_change_enable_ssi (Divider_ssi, 1, 29), 136 Clock_change_enable_uhc (Divider_uhc, 1, 29), 137 Clock_change_enable_vpu (Divider_vpu, 1, 29), 138 139 Clock_divider_cpu (Clock_control, 0x0f, 0), // CDIV 140 Clock_divider_hclock0 (Clock_control, 0x0f, 8), // H0DIV (fast AHB peripherals) 141 Clock_divider_hclock2 (Clock_control, 0x0f, 12), // H2DIV (fast AHB peripherals) 142 Clock_divider_l2cache (Clock_control, 0x0f, 4), // L2CDIV 143 Clock_divider_pclock (Clock_control, 0x0f, 16), // PDIV (slow APB peripherals) 144 Clock_divider_bch (Divider_bch, 0x0f, 0), // BCHCDR 145 Clock_divider_cim (Divider_cim, 0xff, 0), // CIMCDR 146 Clock_divider_ddr (Divider_ddr, 0x0f, 0), // DDRCDR 147 Clock_divider_gpu (Divider_gpu, 0x0f, 0), // GPUCDR 148 Clock_divider_hdmi (Divider_hdmi, 0xff, 0), // HDMICDR 149 Clock_divider_i2s0 (Divider_i2s0, 0xff, 0), // I2SCDR 150 Clock_divider_i2s1 (Divider_i2s1, 0xff, 0), // I2SCDR 151 Clock_divider_lcd0 (Divider_lcd0, 0xff, 0), // LPCDR 152 Clock_divider_lcd1 (Divider_lcd1, 0xff, 0), // LPCDR 153 Clock_divider_msc0 (Divider_msc0, 0xff, 0), // MSC0CDR 154 Clock_divider_msc1 (Divider_msc1, 0xff, 0), // MSC1CDR 155 Clock_divider_msc2 (Divider_msc2, 0xff, 0), // MSC2CDR 156 Clock_divider_pcm (Divider_pcm, 0xff, 0), // PCMCDR 157 Clock_divider_ssi (Divider_ssi, 0xff, 0), // SSICDR 158 Clock_divider_uhc (Divider_uhc, 0xff, 0), // UHCCDR 159 Clock_divider_vpu (Divider_vpu, 0x0f, 0), // VPUCDR 160 161 Clock_gate_main (Clock_control, 1, 23, true), // GATE_SCLKA 162 Clock_gate_ddr (Clock_gate0, 3, 30, true), // DDR1, DDR0 163 Clock_gate_ipu (Clock_gate0, 1, 29, true), // IPU 164 Clock_gate_lcd (Clock_gate0, 3, 27, true), // LCD, TVE 165 Clock_gate_cim (Clock_gate0, 1, 26, true), // CIM 166 Clock_gate_i2c2 (Clock_gate0, 1, 25, true), // SMB2 167 Clock_gate_uhc (Clock_gate0, 1, 24, true), // UHC 168 Clock_gate_mac (Clock_gate0, 1, 23, true), // MAC 169 Clock_gate_gps (Clock_gate0, 1, 22, true), // GPS 170 Clock_gate_dma (Clock_gate0, 1, 21, true), // PDMA 171 //Clock_gate_ssi2 (Clock_gate0, 1, 20, true), // SSI2 172 Clock_gate_ssi1 (Clock_gate0, 1, 19, true), // SSI1 173 Clock_gate_uart3 (Clock_gate0, 1, 18, true), // UART3 174 Clock_gate_uart2 (Clock_gate0, 1, 17, true), // UART2 175 Clock_gate_uart1 (Clock_gate0, 1, 16, true), // UART1 176 Clock_gate_uart0 (Clock_gate0, 1, 15, true), // UART0 177 Clock_gate_sadc (Clock_gate0, 1, 14, true), // SADC 178 Clock_gate_kbc (Clock_gate0, 1, 13, true), // KBC 179 Clock_gate_msc2 (Clock_gate0, 1, 12, true), // MSC2 180 Clock_gate_msc1 (Clock_gate0, 1, 11, true), // MSC1 181 Clock_gate_owi (Clock_gate0, 1, 10, true), // OWI 182 Clock_gate_tssi0 (Clock_gate0, 1, 9, true), // TSSI0 183 Clock_gate_aic0 (Clock_gate0, 1, 8, true), // AIC0 184 Clock_gate_scc (Clock_gate0, 1, 7, true), // SCC 185 Clock_gate_i2c1 (Clock_gate0, 1, 6, true), // SMB1 186 Clock_gate_i2c0 (Clock_gate0, 1, 5, true), // SMB0 187 Clock_gate_ssi0 (Clock_gate0, 1, 4, true), // SSI0 188 Clock_gate_msc0 (Clock_gate0, 1, 3, true), // MSC0 189 Clock_gate_otg0 (Clock_gate0, 1, 2, true), // OTG0 190 Clock_gate_bch (Clock_gate0, 1, 1, true), // BCH 191 Clock_gate_nemc (Clock_gate0, 1, 0, true), // NEMC 192 Clock_gate_cpu1 (Clock_gate1, 1, 15, true), // P1 193 Clock_gate_x2d (Clock_gate1, 1, 14, true), // X2D 194 Clock_gate_des (Clock_gate1, 1, 13, true), // DES 195 Clock_gate_i2c4 (Clock_gate1, 1, 12, true), // SMB4 196 Clock_gate_ahb_mon (Clock_gate1, 1, 11, true), // AHB_MON 197 Clock_gate_uart4 (Clock_gate1, 1, 10, true), // UART4 198 Clock_gate_hdmi (Clock_gate1, 1, 9, true), // HDMI 199 Clock_gate_otg1 (Clock_gate1, 1, 8, true), // OTG1 200 Clock_gate_gpvlc (Clock_gate1, 1, 7, true), // GPVLC 201 Clock_gate_aic1 (Clock_gate1, 1, 6, true), // AIC1 202 Clock_gate_compress (Clock_gate1, 1, 5, true), // COMPRESS 203 Clock_gate_gpu (Clock_gate1, 1, 4, true), // GPU 204 Clock_gate_pcm (Clock_gate1, 1, 3, true), // PCM 205 Clock_gate_vpu (Clock_gate1, 1, 2, true), // VPU 206 Clock_gate_tssi1 (Clock_gate1, 1, 1, true), // TSSI1 207 Clock_gate_i2c3 (Clock_gate1, 1, 0, true), // I2C3 208 209 Pll_enable_A (Pll_control_A, 1, 0), // APLLEN 210 Pll_enable_E (Pll_control_E, 1, 0), // EPLLEN 211 Pll_enable_M (Pll_control_M, 1, 0), // MPLLEN 212 Pll_enable_V (Pll_control_V, 1, 0), // VPLLEN 213 214 Pll_stable_A (Pll_control_A, 1, 4), // APLL_ON 215 Pll_stable_E (Pll_control_E, 1, 4), // EPLL_ON 216 Pll_stable_M (Pll_control_M, 1, 4), // MPLL_ON 217 Pll_stable_V (Pll_control_V, 1, 4), // VPLL_ON 218 219 Pll_bypass_A (Pll_control_A, 1, 1), // APLL_BP 220 Pll_bypass_E (Pll_control_E, 1, 1), // EPLL_BP 221 Pll_bypass_M (Pll_control_M, 1, 1), // MPLL_BP 222 Pll_bypass_V (Pll_control_V, 1, 1), // VPLL_BP 223 224 // Multipliers and dividers yield 1-based values. 225 226 Pll_multiplier_A (Pll_control_A, 0x1fff, 19, false, 1), // APLLM 227 Pll_multiplier_E (Pll_control_E, 0x1fff, 19, false, 1), // EPLLM 228 Pll_multiplier_M (Pll_control_M, 0x1fff, 19, false, 1), // MPLLM 229 Pll_multiplier_V (Pll_control_V, 0x1fff, 19, false, 1), // VPLLM 230 231 Pll_input_division_A (Pll_control_A, 0x3f, 13, false, 1), // APLLN 232 Pll_input_division_E (Pll_control_E, 0x3f, 13, false, 1), // EPLLN 233 Pll_input_division_M (Pll_control_M, 0x3f, 13, false, 1), // MPLLN 234 Pll_input_division_V (Pll_control_V, 0x3f, 13, false, 1), // VPLLN 235 236 Pll_output_division_A (Pll_control_A, 0x0f, 9, false, 1), // APLLOD 237 Pll_output_division_E (Pll_control_E, 0x0f, 9, false, 1), // EPLLOD 238 Pll_output_division_M (Pll_control_M, 0x0f, 9, false, 1), // MPLLOD 239 Pll_output_division_V (Pll_control_V, 0x0f, 9, false, 1); // VPLLOD 240 241 242 243 // Multiplexer instances. 244 245 #define Clocks(...) ((enum Clock_identifiers []) {__VA_ARGS__}) 246 #define Specific(CLOCK) ((enum Clock_identifiers) (CLOCK)) 247 248 static Mux mux_external (Clock_external), 249 250 // Clocks being propagated to others. 251 252 mux_clock_ssi (Clock_ssi), 253 mux_clock_msc (Clock_msc), 254 mux_hclock2 (Clock_hclock2), 255 mux_hclock2_pclock (Clock_hclock2_pclock), 256 mux_pclock (Clock_pclock), 257 258 // Main bus and peripheral clock sources. 259 260 mux_ahb2 (4, Clocks(Clock_none, Clock_main, Clock_pll_M, Clock_rtc_external)), 261 mux_core (4, Clocks(Clock_none, Clock_main, Clock_pll_M, Clock_pll_E)), 262 mux_main (4, Clocks(Clock_none, Clock_pll_A, Clock_external, Clock_rtc_external)), 263 264 // Memory and device clock sources. 265 266 mux_cim (2, Clocks(Clock_main, Clock_pll_M)), 267 mux_dev (3, Clocks(Clock_none, Clock_main, Clock_pll_M)), 268 mux_lcd (3, Clocks(Clock_main, Clock_pll_M, Clock_pll_V)), 269 mux_usb (3, Clocks(Clock_main, Clock_pll_M, Clock_pll_E /* , OTG PHY */)), 270 mux_usb_phy (4, Clocks(Specific(Clock_usb_phy_12MHz), Specific(Clock_usb_phy_24MHz), 271 Specific(Clock_usb_phy_48MHz), Specific(Clock_usb_phy_19_2MHz))), 272 273 // Clock selectors involving the external clock. 274 275 mux_i2s (4, Clocks(Clock_external, Clock_external, Clock_main, Clock_pll_E)), 276 mux_pcm (8, Clocks(Clock_external, Clock_external, Clock_external, Clock_external, 277 Clock_main, Clock_pll_M, Clock_pll_E, Clock_pll_V)), 278 mux_ssi (4, Clocks(Clock_external, Clock_external, Clock_main, Clock_pll_M)); 279 280 281 282 // Clock instances. 283 284 static Clock_null clock_none; 285 286 static Clock_passive clock_external(48000000), 287 clock_rtc_external(32768), 288 clock_usb_phy_12MHz(12000000), 289 clock_usb_phy_19_2MHz(19200000), 290 clock_usb_phy_24MHz(24000000), 291 clock_usb_phy_48MHz(48000000); 292 293 294 295 // Note the use of extra parentheses due to the annoying C++ "most vexing parse" 296 // problem. See: https://en.wikipedia.org/wiki/Most_vexing_parse 297 298 static Clock clock_ahb_mon((Source(mux_external)), (Control(Clock_gate_ahb_mon))), 299 300 clock_compress((Source(mux_external)), (Control(Clock_gate_compress))), 301 302 clock_des((Source(mux_external)), (Control(Clock_gate_des))), 303 304 clock_dma((Source(mux_external)), (Control(Clock_gate_dma))), 305 306 clock_gps((Source(mux_external)), (Control(Clock_gate_gps))), 307 308 clock_gpvlc((Source(mux_external)), (Control(Clock_gate_gpvlc))), 309 310 clock_i2c0((Source(mux_pclock)), (Control(Clock_gate_i2c0))), 311 312 clock_i2c1((Source(mux_pclock)), (Control(Clock_gate_i2c1))), 313 314 clock_i2c2((Source(mux_pclock)), (Control(Clock_gate_i2c2))), 315 316 clock_i2c3((Source(mux_pclock)), (Control(Clock_gate_i2c3))), 317 318 clock_i2c4((Source(mux_pclock)), (Control(Clock_gate_i2c4))), 319 320 clock_i2s0(Source(mux_i2s, Clock_source_i2s0), Control(Clock_gate_aic0)), 321 322 clock_i2s1(Source(mux_i2s, Clock_source_i2s1), Control(Clock_gate_aic1)), 323 324 clock_ipu((Source(mux_external)), (Control(Clock_gate_ipu))), 325 326 clock_kbc((Source(mux_external)), (Control(Clock_gate_kbc))), 327 328 clock_lcd((Source(mux_external)), (Control(Clock_gate_lcd))), 329 330 clock_main(Source(mux_main, Clock_source_main), Control(Clock_gate_main)), 331 332 clock_mac((Source(mux_external)), (Control(Clock_gate_mac))), 333 334 clock_msc((Source(mux_dev, Clock_source_msc))), 335 336 clock_nemc((Source(mux_hclock2)), (Control(Clock_gate_nemc))), 337 338 clock_otg0((Source(mux_external)), (Control(Clock_gate_otg0))), 339 340 clock_otg1((Source(mux_external)), (Control(Clock_gate_otg1))), 341 342 clock_owi((Source(mux_external)), (Control(Clock_gate_owi))), 343 344 clock_sadc((Source(mux_external)), (Control(Clock_gate_sadc))), 345 346 clock_scc((Source(mux_external)), (Control(Clock_gate_scc))), 347 348 clock_tssi0((Source(mux_external)), (Control(Clock_gate_tssi0))), 349 350 clock_tssi1((Source(mux_external)), (Control(Clock_gate_tssi1))), 351 352 clock_uart0((Source(mux_external)), (Control(Clock_gate_uart0))), 353 354 clock_uart1((Source(mux_external)), (Control(Clock_gate_uart1))), 355 356 clock_uart2((Source(mux_external)), (Control(Clock_gate_uart2))), 357 358 clock_uart3((Source(mux_external)), (Control(Clock_gate_uart3))), 359 360 clock_uart4((Source(mux_external)), (Control(Clock_gate_uart4))), 361 362 clock_usb_phy(Source(mux_usb_phy, Clock_source_usb_phy)), 363 364 clock_x2d((Source(mux_external)), (Control(Clock_gate_x2d))), 365 366 // Special parent clock for hclock2 and pclock. 367 368 clock_hclock2_pclock(Source(mux_ahb2, Clock_source_hclock2)), 369 370 // SSI channel clocks depending on a common parent divider. 371 372 clock_ssi0((Source(mux_clock_ssi)), Control(Clock_gate_ssi0)), 373 374 clock_ssi1((Source(mux_clock_ssi)), Control(Clock_gate_ssi1)); 375 376 static Clock_divided 377 clock_bch(Source(mux_core, Clock_source_bch), 378 Control(Clock_gate_bch, Clock_change_enable_bch, Clock_busy_bch), 379 Divider(Clock_divider_bch)), 380 381 clock_cim(Source(mux_cim, Clock_source_cim), 382 Control(Clock_gate_cim, Clock_change_enable_cim, Clock_busy_cim), 383 Divider(Clock_divider_cim)), 384 385 clock_cpu(Source(mux_core, Clock_source_cpu), 386 Control(Field::undefined, Clock_change_enable_cpu, Clock_busy_cpu), 387 Divider(Clock_divider_cpu)), 388 389 clock_ddr(Source(mux_dev, Clock_source_ddr), 390 Control(Clock_gate_ddr, Clock_change_enable_ddr, Clock_busy_ddr), 391 Divider(Clock_divider_ddr)), 392 393 clock_gpu(Source(mux_core, Clock_source_gpu), 394 Control(Clock_gate_gpu, Clock_change_enable_gpu, Clock_busy_gpu), 395 Divider(Clock_divider_gpu)), 396 397 clock_hclock0(Source(mux_core, Clock_source_hclock0), 398 Control(Field::undefined, Clock_change_enable_ahb0), 399 Divider(Clock_divider_hclock0)), 400 401 clock_hclock2(Source(mux_hclock2_pclock), 402 Control(Field::undefined, Clock_change_enable_ahb2), 403 Divider(Clock_divider_hclock2)), 404 405 clock_hdmi(Source(mux_lcd, Clock_source_hdmi), 406 Control(Clock_gate_hdmi, Clock_change_enable_hdmi, Clock_busy_hdmi), 407 Divider(Clock_divider_hdmi)), 408 409 clock_l2cache(Source(mux_core, Clock_source_cpu), 410 Control(Field::undefined, Clock_change_enable_cpu, Clock_busy_cpu), 411 Divider(Clock_divider_l2cache)), 412 413 clock_lcd_pixel0(Source(mux_lcd, Clock_source_lcd0), 414 Control(Clock_gate_lcd, Clock_change_enable_lcd0, Clock_busy_lcd0), 415 Divider(Clock_divider_lcd0)), 416 417 clock_lcd_pixel1(Source(mux_lcd, Clock_source_lcd1), 418 Control(Clock_gate_lcd, Clock_change_enable_lcd1, Clock_busy_lcd1), 419 Divider(Clock_divider_lcd1)), 420 421 clock_msc0(Source(mux_clock_msc), 422 Control(Clock_gate_msc0, Clock_change_enable_msc0, Clock_busy_msc0), 423 Divider(Clock_divider_msc0, 2)), 424 425 clock_msc1(Source(mux_clock_msc), 426 Control(Clock_gate_msc1, Clock_change_enable_msc1, Clock_busy_msc1), 427 Divider(Clock_divider_msc1, 2)), 428 429 clock_msc2(Source(mux_clock_msc), 430 Control(Clock_gate_msc2, Clock_change_enable_msc2, Clock_busy_msc2), 431 Divider(Clock_divider_msc2, 2)), 432 433 clock_pcm(Source(mux_pcm, Clock_source_pcm), 434 Control(Clock_gate_pcm, Clock_change_enable_pcm, Clock_busy_pcm), 435 Divider(Clock_divider_pcm)), 436 437 clock_pclock(Source(mux_hclock2_pclock), 438 Control(Field::undefined, Clock_change_enable_ahb2), 439 Divider(Clock_divider_pclock)), 440 441 clock_ssi(Source(mux_ssi, Clock_source_ssi), 442 Control(Field::undefined, Clock_change_enable_ssi, Clock_busy_ssi), 443 Divider(Clock_divider_ssi)), 444 445 clock_uhc(Source(mux_usb, Clock_source_uhc), 446 Control(Clock_gate_uhc, Clock_change_enable_uhc, Clock_busy_uhc), 447 Divider(Clock_divider_uhc)), 448 449 clock_vpu(Source(mux_core, Clock_source_vpu), 450 Control(Clock_gate_vpu, Clock_change_enable_vpu, Clock_busy_vpu), 451 Divider(Clock_divider_vpu)); 452 453 static Clock_divided_fixed 454 clock_external_div_512((Source(mux_external)), (Divider_fixed(512))); 455 456 const double jz4780_pll_intermediate_min = 300000000, 457 jz4780_pll_intermediate_max = 1500000000; 458 459 static Pll clock_pll_A(Source(mux_external), 460 Control_pll(Pll_enable_A, Pll_stable_A, Pll_bypass_A), 461 Divider_pll(Pll_multiplier_A, Pll_input_division_A, 462 Pll_output_division_A, 463 jz4780_pll_intermediate_min, jz4780_pll_intermediate_max)), 464 465 clock_pll_E(Source(mux_external), 466 Control_pll(Pll_enable_E, Pll_stable_E, Pll_bypass_E), 467 Divider_pll(Pll_multiplier_E, Pll_input_division_E, 468 Pll_output_division_E, 469 jz4780_pll_intermediate_min, jz4780_pll_intermediate_max)), 470 471 clock_pll_M(Source(mux_external), 472 Control_pll(Pll_enable_M, Pll_stable_M, Pll_bypass_M), 473 Divider_pll(Pll_multiplier_M, Pll_input_division_M, 474 Pll_output_division_M, 475 jz4780_pll_intermediate_min, jz4780_pll_intermediate_max)), 476 477 clock_pll_V(Source(mux_external), 478 Control_pll(Pll_enable_V, Pll_stable_V, Pll_bypass_V), 479 Divider_pll(Pll_multiplier_V, Pll_input_division_V, 480 Pll_output_division_V, 481 jz4780_pll_intermediate_min, jz4780_pll_intermediate_max)); 482 483 484 485 // Clock register. 486 487 static Clock_base *clocks[Clock_jz4780_identifier_count] = { 488 &clock_none, 489 490 &clock_none, // Clock_aic 491 &clock_none, // Clock_aic_bitclk 492 &clock_none, // Clock_aic_pclk 493 &clock_none, // Clock_can0 494 &clock_none, // Clock_can1 495 &clock_none, // Clock_cdbus 496 &clock_cim, 497 &clock_cpu, 498 &clock_ddr, 499 &clock_dma, 500 &clock_none, // Clock_emac 501 &clock_external, 502 &clock_external_div_512, 503 &clock_hclock0, 504 &clock_hclock2, 505 &clock_hclock2_pclock, 506 &clock_hdmi, 507 &clock_i2c0, 508 &clock_i2c1, 509 &clock_i2c2, 510 &clock_i2c3, 511 &clock_i2c4, 512 &clock_i2s0, 513 &clock_none, // Clock_i2s0_rx 514 &clock_none, // Clock_i2s0_tx 515 &clock_i2s1, 516 &clock_none, // Clock_i2s1_rx 517 &clock_none, // Clock_i2s1_tx 518 &clock_none, // Clock_kbc 519 &clock_l2cache, 520 &clock_lcd, 521 &clock_lcd_pixel0, 522 &clock_lcd_pixel1, 523 &clock_mac, 524 &clock_main, 525 &clock_none, // Clock_mipi_csi 526 &clock_msc, 527 &clock_msc0, 528 &clock_msc1, 529 &clock_msc2, 530 &clock_nemc, 531 &clock_otg0, 532 &clock_otg1, 533 &clock_pclock, 534 &clock_pcm, 535 &clock_pll_A, 536 &clock_pll_E, 537 &clock_pll_M, 538 &clock_pll_V, 539 &clock_none, // Clock_pwm0 540 &clock_none, // Clock_pwm1 541 &clock_external_div_512,// Clock_rtc 542 &clock_rtc_external, 543 &clock_sadc, 544 &clock_scc, 545 &clock_none, // Clock_sfc 546 &clock_ssi, 547 &clock_ssi0, 548 &clock_ssi1, 549 &clock_none, // Clock_ssi2 550 &clock_none, // Clock_timer 551 &clock_uart0, 552 &clock_uart1, 553 &clock_uart2, 554 &clock_uart3, 555 &clock_uart4, 556 &clock_none, // Clock_udc 557 &clock_uhc, 558 &clock_none, // Clock_uprt 559 &clock_usb_phy, 560 &clock_vpu, 561 562 /* JZ4780-specific clocks. */ 563 564 &clock_usb_phy_12MHz, 565 &clock_usb_phy_19_2MHz, 566 &clock_usb_phy_24MHz, 567 &clock_usb_phy_48MHz, 568 }; 569 570 571 572 // Peripheral abstraction. 573 574 Cpm_jz4780_chip::Cpm_jz4780_chip(l4_addr_t addr) 575 : Cpm_chip(addr, clocks) 576 { 577 } 578 579 580 581 // C language interface functions. 582 583 void 584 *jz4780_cpm_init(l4_addr_t cpm_base) 585 { 586 return (void *) new Cpm_jz4780_chip(cpm_base); 587 } 588 589 const char * 590 jz4780_cpm_clock_type(void *cpm, enum Clock_identifiers clock) 591 { 592 return static_cast<Cpm_jz4780_chip *>(cpm)->clock_type(clock); 593 } 594 595 int 596 jz4780_cpm_have_clock(void *cpm, enum Clock_identifiers clock) 597 { 598 return static_cast<Cpm_jz4780_chip *>(cpm)->have_clock(clock); 599 } 600 601 void 602 jz4780_cpm_start_clock(void *cpm, enum Clock_identifiers clock) 603 { 604 static_cast<Cpm_jz4780_chip *>(cpm)->start_clock(clock); 605 } 606 607 void 608 jz4780_cpm_stop_clock(void *cpm, enum Clock_identifiers clock) 609 { 610 static_cast<Cpm_jz4780_chip *>(cpm)->stop_clock(clock); 611 } 612 613 int 614 jz4780_cpm_get_parameters(void *cpm, enum Clock_identifiers clock, uint32_t parameters[]) 615 { 616 return static_cast<Cpm_jz4780_chip *>(cpm)->get_parameters(clock, parameters); 617 } 618 619 int 620 jz4780_cpm_set_parameters(void *cpm, enum Clock_identifiers clock, int num_parameters, uint32_t parameters[]) 621 { 622 return static_cast<Cpm_jz4780_chip *>(cpm)->set_parameters(clock, num_parameters, parameters); 623 } 624 625 uint8_t 626 jz4780_cpm_get_source(void *cpm, enum Clock_identifiers clock) 627 { 628 return static_cast<Cpm_jz4780_chip *>(cpm)->get_source(clock); 629 } 630 631 void 632 jz4780_cpm_set_source(void *cpm, enum Clock_identifiers clock, uint8_t source) 633 { 634 static_cast<Cpm_jz4780_chip *>(cpm)->set_source(clock, source); 635 } 636 637 enum Clock_identifiers 638 jz4780_cpm_get_source_clock(void *cpm, enum Clock_identifiers clock) 639 { 640 return static_cast<Cpm_jz4780_chip *>(cpm)->get_source_clock(clock); 641 } 642 643 void 644 jz4780_cpm_set_source_clock(void *cpm, enum Clock_identifiers clock, enum Clock_identifiers source) 645 { 646 static_cast<Cpm_jz4780_chip *>(cpm)->set_source_clock(clock, source); 647 } 648 649 uint64_t 650 jz4780_cpm_get_source_frequency(void *cpm, enum Clock_identifiers clock) 651 { 652 return static_cast<Cpm_jz4780_chip *>(cpm)->get_source_frequency(clock); 653 } 654 655 uint64_t 656 jz4780_cpm_get_frequency(void *cpm, enum Clock_identifiers clock) 657 { 658 return static_cast<Cpm_jz4780_chip *>(cpm)->get_frequency(clock); 659 } 660 661 int 662 jz4780_cpm_set_frequency(void *cpm, enum Clock_identifiers clock, uint64_t frequency) 663 { 664 return static_cast<Cpm_jz4780_chip *>(cpm)->set_frequency(clock, frequency); 665 }