1 /* 2 * RTC (real-time clock) support for various devices. 3 * 4 * Copyright (C) 2023, 2024 Paul Boddie <paul@boddie.org.uk> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 19 * Boston, MA 02110-1301, USA 20 */ 21 22 #pragma once 23 24 #ifdef __cplusplus 25 26 // Register locations. 27 28 enum Regs : unsigned 29 { 30 Rtc_control = 0x000, // RTCCR 31 Rtc_seconds = 0x004, // RTCSR 32 Rtc_alarm_seconds = 0x008, // RTCSAR 33 Rtc_regulator = 0x00c, // RTCGR 34 35 Hibernate_control = 0x020, // HCR 36 Hibernate_wakeup_filter_counter = 0x024, // HWFCR 37 Hibernate_reset_counter = 0x028, // HRCR 38 Hibernate_wakeup_control = 0x02c, // HWCR 39 Hibernate_wakeup_status = 0x030, // HWRSR 40 Hibernate_scratch_pattern = 0x034, // HSPR 41 Hibernate_write_enable_pattern = 0x03c, // WENR 42 Hibernate_wakeup_pin_configure = 0x048, // WKUPPINCR (X1600) 43 Power_on_control_register = 0x048, // PWRONCR (JZ4780) 44 }; 45 46 // Field definitions. 47 48 enum Control_bits : unsigned 49 { 50 Control_write_ready = 0x80, // WRDY 51 Control_1Hz = 0x40, // 1HZ 52 Control_1Hz_irq_enable = 0x20, // 1HZIE 53 Control_alarm = 0x10, // AF 54 Control_alarm_irq_enable = 0x08, // AIE 55 Control_alarm_enable = 0x04, // AE 56 Control_external_divided = 0x02, // SELEXC (JZ4780) 57 Control_rtc_enable = 0x01, // RTCE 58 }; 59 60 enum Regulator_bits : unsigned 61 { 62 Regulator_lock = 0x80000000, // LOCK 63 Regulator_adjust_count_mask = 0x03ff0000, // ADJC 64 Regulator_1Hz_cycle_count_mask = 0x0000ffff, // NC1HZ 65 }; 66 67 enum Regulator_limits : unsigned 68 { 69 Regulator_adjust_count_limit = 0x03ff, // ADJC 70 Regulator_1Hz_cycle_count_limit = 0xffff, // NC1HZ 71 }; 72 73 enum Regulator_shifts : unsigned 74 { 75 Regulator_adjust_count_shift = 16, // ADJC 76 Regulator_1Hz_cycle_count_shift = 0, // NC1HZ 77 }; 78 79 enum Hibernate_control_bits : unsigned 80 { 81 Hibernate_power_down = 0x01, // PD 82 }; 83 84 enum Hibernate_wakeup_filter_counter_bits : unsigned 85 { 86 Wakeup_minimum_time_mask = 0xffe0, // HWFCR 87 }; 88 89 enum Hibernate_reset_counter_bits : unsigned 90 { 91 Reset_assert_time_mask = 0x7800, // HRCR 92 }; 93 94 enum Hibernate_wakeup_control_bits : unsigned 95 { 96 Power_detect_enable_mask = 0xfffffff8, // EPDET 97 Rtc_alarm_wakeup_enable = 0x00000001, // EALM 98 }; 99 100 enum Hibernate_wakeup_status_bits : unsigned 101 { 102 Accident_power_down = 0x0100, // APD 103 Hibernate_reset = 0x0020, // HR 104 Pad_pin_reset = 0x0010, // PPR 105 Wakeup_pin_status = 0x0002, // PIN 106 Rtc_alarm_status = 0x0001, // ALM 107 }; 108 109 enum Hibernate_write_enable_pattern_bits : unsigned 110 { 111 Write_enable_status = 0x80000000, // WEN 112 Write_enable_pattern_mask = 0x0000ffff, // WENPAT 113 Write_enable_pattern = 0x0000a55a, // WENPAT 114 }; 115 116 enum Hibernate_wakeup_pin_configure_bits : unsigned 117 { 118 Rtc_oscillator_test_enable = 0x00080000, // OSC_TE 119 Oscillator_xtclk_rtclk = 0x00040000, // OSC_RETON 120 Oscillator_xtclk_low = 0x00000000, // OSC_RETON 121 Rtc_internal_oscillator_enable = 0x00010000, // OSC_EN 122 Wakeup_pin_extended_press_mask = 0x000000f0, // P_JUD_LEN 123 Wakeup_pin_extended_press_enable = 0x0000000f, // P_RST_LEN 124 }; 125 126 enum Power_on_control_register_bits : unsigned 127 { 128 Power_off_assert_length_mask = 0x000000f0, // PWROFF_LEN 129 Power_on_enable = 0x00000001, // PWRON_EN 130 }; 131 132 #endif /* __cplusplus */