1 /* 2 * Clock and power management. This exposes the combined functionality 3 * provided by the X1600 and related SoCs. The power management 4 * functionality could be exposed using a separate driver. 5 * 6 * Copyright (C) 2017, 2018, 2020, 2021, 2023 Paul Boddie <paul@boddie.org.uk> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 21 * Boston, MA 02110-1301, USA 22 */ 23 24 #include <l4/devices/hw_mmio_register_block.h> 25 #include "cpm-x1600.h" 26 #include <math.h> 27 #include <stdio.h> 28 29 30 31 // Register locations. 32 33 enum Regs : unsigned 34 { 35 Clock_control = 0x000, // CPCCR 36 Low_power_control = 0x004, // LCR 37 Clock_gate0 = 0x020, // CLKGR0 38 Clock_gate1 = 0x028, // CLKGR1 39 Sleep_control = 0x024, // OPCR (oscillator and power control) 40 Clock_status = 0x0d4, // CPCSR 41 Divider_ddr = 0x02c, // DDRCDR 42 Divider_mac = 0x054, // MACCDR 43 Divider0_i2s0 = 0x060, // I2S0CDR 44 Divider1_i2s0 = 0x070, // I2S0CDR1 45 Divider0_i2s1 = 0x07c, // I2S1CDR (from X2000 manual) 46 Divider1_i2s1 = 0x080, // I2S1CDR1 (from X2000 manual) 47 Divider_lcd = 0x064, // LPCDR 48 Divider_msc0 = 0x068, // MSC0CDR 49 Divider_msc1 = 0x0a4, // MSC1CDR 50 Divider_sfc = 0x074, // SFCCDR 51 Divider_ssi = 0x05c, // SSICDR 52 Divider_cim = 0x078, // CIMCDR 53 Divider_pwm = 0x06c, // PWMCDR 54 Divider_can0 = 0x0a0, // CAN0CDR 55 Divider_can1 = 0x0a8, // CAN1CDR 56 Divider_cdbus = 0x0ac, // CDBUSCDR 57 Divider_macphy0 = 0x0e4, // MPHY0C 58 Cpm_interrupt = 0x0b0, // CPM_INTR 59 Cpm_interrupt_en = 0x0b4, // CPM_INTRE 60 Cpm_swi = 0x0bc, // CPM_SFTINT 61 Ddr_gate = 0x0d0, // DRCG 62 Cpm_scratch_prot = 0x038, // CPSPPR 63 Cpm_scratch = 0x034, // CPSPR 64 Usb_param_control0 = 0x03c, // USBPCR 65 Usb_reset_detect = 0x040, // USBRDT 66 Usb_vbus_jitter = 0x044, // USBVBFIL 67 Usb_param_control1 = 0x048, // USBPCR1 68 Pll_control = 0x00c, // CPPCR 69 Pll_control_A = 0x010, // CPAPCR 70 Pll_control_M = 0x014, // CPMPCR 71 Pll_control_E = 0x018, // CPEPCR 72 Pll_fraction_A = 0x084, // CPAPACR 73 Pll_fraction_M = 0x088, // CPMPACR 74 Pll_fraction_E = 0x08c, // CPEPACR 75 }; 76 77 enum Clock_source_values : unsigned 78 { 79 Source_mME_main = 0, 80 Source_mME_pll_M = 1, 81 Source_mME_pll_E = 2, 82 83 // Special value 84 85 Source_mask = 0x3, 86 }; 87 88 89 90 // Register field definitions. 91 92 static Field Clock_source_main (Clock_control, 3, 30), // SEL_SRC (output to SCLK_A) 93 Clock_source_cpu (Clock_control, 3, 28), // SEL_CPLL (output to CCLK) 94 Clock_source_hclock0 (Clock_control, 3, 26), // SEL_H0PLL (output to AHB0) 95 Clock_source_hclock2 (Clock_control, 3, 24), // SEL_H2PLL (output to AHB2) 96 Clock_source_can0 (Divider_can0, 3, 30), // CA0CS 97 Clock_source_can1 (Divider_can1, 3, 30), // CA1CS 98 Clock_source_cdbus (Divider_cdbus, 3, 30), // CDCS 99 Clock_source_cim (Divider_cim, 3, 30), // CIMPCS 100 Clock_source_ddr (Divider_ddr, 3, 30), // DCS 101 Clock_source_i2s0 (Divider0_i2s0, 1, 30), // I2PCS 102 Clock_source_i2s1 (Divider0_i2s1, 1, 30), // I2PCS 103 Clock_source_lcd (Divider_lcd, 3, 30), // LPCS 104 Clock_source_mac (Divider_mac, 3, 30), // MACPCS 105 Clock_source_msc0 (Divider_msc0, 3, 30), // MPCS 106 Clock_source_msc1 (Divider_msc1, 3, 30), // MPCS 107 Clock_source_pwm (Divider_pwm, 3, 30), // PWMPCS 108 Clock_source_sfc (Divider_sfc, 3, 30), // SFCS 109 Clock_source_ssi (Divider_ssi, 3, 30), // SPCS 110 111 Clock_busy_cpu (Clock_status, 1, 0), 112 Clock_busy_ddr (Divider_ddr, 1, 28), 113 Clock_busy_mac (Divider_mac, 1, 28), 114 Clock_busy_lcd (Divider_lcd, 1, 28), 115 Clock_busy_msc0 (Divider_msc0, 1, 28), 116 Clock_busy_msc1 (Divider_msc1, 1, 28), 117 Clock_busy_sfc (Divider_sfc, 1, 28), 118 Clock_busy_ssi (Divider_ssi, 1, 28), 119 Clock_busy_cim (Divider_cim, 1, 28), 120 Clock_busy_pwm (Divider_pwm, 1, 28), 121 Clock_busy_can0 (Divider_can0, 1, 28), 122 Clock_busy_can1 (Divider_can1, 1, 28), 123 Clock_busy_cdbus (Divider_cdbus, 1, 28), 124 125 Clock_change_enable_cpu (Clock_control, 1, 22), 126 Clock_change_enable_ahb0 (Clock_control, 1, 21), 127 Clock_change_enable_ahb2 (Clock_control, 1, 20), 128 Clock_change_enable_ddr (Divider_ddr, 1, 29), 129 Clock_change_enable_mac (Divider_mac, 1, 29), 130 Clock_gate_i2s0 (Divider0_i2s0, 1, 29), // CE_I2S is gate, not change enable 131 Clock_gate_i2s1 (Divider0_i2s1, 1, 29), // CE_I2S is gate, not change enable 132 Clock_change_enable_lcd (Divider_lcd, 1, 29), 133 Clock_change_enable_msc0 (Divider_msc0, 1, 29), 134 Clock_change_enable_msc1 (Divider_msc1, 1, 29), 135 Clock_change_enable_sfc (Divider_sfc, 1, 29), 136 Clock_change_enable_ssi (Divider_ssi, 1, 29), 137 Clock_change_enable_cim (Divider_cim, 1, 29), 138 Clock_change_enable_pwm (Divider_pwm, 1, 29), 139 Clock_change_enable_can0 (Divider_can0, 1, 29), 140 Clock_change_enable_can1 (Divider_can1, 1, 29), 141 Clock_change_enable_cdbus (Divider_cdbus, 1, 29), 142 143 Clock_divider_can0 (Divider_can0, 0xff, 0), // CAN0CDR 144 Clock_divider_can1 (Divider_can1, 0xff, 0), // CAN1CDR 145 Clock_divider_cdbus (Divider_cdbus, 0xff, 0), // CDBUSCDR 146 Clock_divider_cim (Divider_cim, 0xff, 0), // CIMCDR 147 Clock_divider_cpu (Clock_control, 0x0f, 0), // CDIV 148 Clock_divider_ddr (Divider_ddr, 0x0f, 0), // DDRCDR 149 Clock_divider_hclock0 (Clock_control, 0x0f, 8), // H0DIV (fast AHB peripherals) 150 Clock_divider_hclock2 (Clock_control, 0x0f, 12), // H2DIV (fast AHB peripherals) 151 Clock_divider_i2s0_m (Divider0_i2s0, 0x1ff, 20), // I2SDIV_M 152 Clock_divider_i2s0_n (Divider0_i2s0, 0xfffff, 0), // I2SDIV_N 153 Clock_divider_i2s0_d (Divider1_i2s0, 0xfffff, 0), // I2SDIV_D 154 Clock_divider_i2s1_m (Divider0_i2s1, 0x1ff, 20), // I2SDIV_M 155 Clock_divider_i2s1_n (Divider0_i2s1, 0xfffff, 0), // I2SDIV_N 156 Clock_divider_i2s1_d (Divider1_i2s1, 0xfffff, 0), // I2SDIV_D 157 Clock_divider_l2cache (Clock_control, 0x0f, 4), // L2CDIV 158 Clock_divider_lcd (Divider_lcd, 0xff, 0), // LPCDR 159 Clock_divider_mac (Divider_mac, 0xff, 0), // MACCDR 160 Clock_divider_msc0 (Divider_msc0, 0xff, 0), // MSC0CDR 161 Clock_divider_msc1 (Divider_msc1, 0xff, 0), // MSC1CDR 162 Clock_divider_pclock (Clock_control, 0x0f, 16), // PDIV (slow APB peripherals) 163 Clock_divider_pwm (Divider_pwm, 0x0f, 0), // PWMCDR 164 Clock_divider_sfc (Divider_sfc, 0xff, 0), // SFCCDR 165 Clock_divider_ssi (Divider_ssi, 0xff, 0), // SSICDR 166 167 Clock_divider_i2s0_n_auto (Divider1_i2s0, 1, 31), // I2S_NEN 168 Clock_divider_i2s0_d_auto (Divider1_i2s0, 1, 30), // I2S_DEN 169 Clock_divider_i2s1_n_auto (Divider1_i2s1, 1, 31), // I2S_NEN 170 Clock_divider_i2s1_d_auto (Divider1_i2s1, 1, 30), // I2S_DEN 171 172 Clock_gate_main (Clock_control, 1, 23, true), // GATE_SCLKA 173 Clock_gate_ddr (Clock_gate0, 1, 31, true), // DDR 174 Clock_gate_ahb0 (Clock_gate0, 1, 29, true), // AHB0 175 Clock_gate_apb0 (Clock_gate0, 1, 28, true), // APB0 176 Clock_gate_rtc (Clock_gate0, 1, 27, true), // RTC 177 Clock_gate_aes (Clock_gate0, 1, 24, true), // AES 178 Clock_gate_lcd_pixel (Clock_gate0, 1, 23, true), // LCD 179 Clock_gate_cim (Clock_gate0, 1, 22, true), // CIM 180 Clock_gate_dma (Clock_gate0, 1, 21, true), // PDMA 181 Clock_gate_ost (Clock_gate0, 1, 20, true), // OST 182 Clock_gate_ssi0 (Clock_gate0, 1, 19, true), // SSI0 183 Clock_gate_timer (Clock_gate0, 1, 18, true), // TCU 184 Clock_gate_dtrng (Clock_gate0, 1, 17, true), // DTRNG 185 Clock_gate_uart2 (Clock_gate0, 1, 16, true), // UART2 186 Clock_gate_uart1 (Clock_gate0, 1, 15, true), // UART1 187 Clock_gate_uart0 (Clock_gate0, 1, 14, true), // UART0 188 Clock_gate_sadc (Clock_gate0, 1, 13, true), // SADC 189 Clock_gate_audio (Clock_gate0, 1, 11, true), // AUDIO 190 Clock_gate_ssi_slv (Clock_gate0, 1, 10, true), // SSI_SLV 191 Clock_gate_i2c1 (Clock_gate0, 1, 8, true), // I2C1 192 Clock_gate_i2c0 (Clock_gate0, 1, 7, true), // I2C0 193 Clock_gate_msc1 (Clock_gate0, 1, 5, true), // MSC1 194 Clock_gate_msc0 (Clock_gate0, 1, 4, true), // MSC0 195 Clock_gate_otg (Clock_gate0, 1, 3, true), // OTG 196 Clock_gate_sfc (Clock_gate0, 1, 2, true), // SFC 197 Clock_gate_efuse (Clock_gate0, 1, 1, true), // EFUSE 198 Clock_gate_nemc (Clock_gate0, 1, 0, true), // NEMC 199 Clock_gate_arb (Clock_gate1, 1, 30, true), // ARB 200 Clock_gate_mipi_csi (Clock_gate1, 1, 28, true), // MIPI_CSI 201 Clock_gate_intc (Clock_gate1, 1, 26, true), // INTC 202 Clock_gate_gmac0 (Clock_gate1, 1, 23, true), // GMAC0 203 Clock_gate_uart3 (Clock_gate1, 1, 16, true), // UART3 204 Clock_gate_i2s0_tx (Clock_gate1, 1, 9, true), // I2S0_dev_tclk 205 Clock_gate_i2s0_rx (Clock_gate1, 1, 8, true), // I2S0_dev_rclk 206 Clock_gate_hash (Clock_gate1, 1, 6, true), // HASH 207 Clock_gate_pwm (Clock_gate1, 1, 5, true), // PWM 208 Clock_gate_cdbus (Clock_gate1, 1, 2, true), // CDBUS 209 Clock_gate_can1 (Clock_gate1, 1, 1, true), // CAN1 210 Clock_gate_can0 (Clock_gate1, 1, 0, true), // CAN0 211 212 Pll_enable_A (Pll_control_A, 1, 0), // APLLEN 213 Pll_enable_E (Pll_control_E, 1, 0), // EPLLEN 214 Pll_enable_M (Pll_control_M, 1, 0), // MPLLEN 215 216 Pll_stable_A (Pll_control_A, 1, 3), // APLL_ON 217 Pll_stable_E (Pll_control_E, 1, 3), // EPLL_ON 218 Pll_stable_M (Pll_control_M, 1, 3), // MPLL_ON 219 220 Pll_bypass_A (Pll_control_A, 1, 30), // APLL_BP 221 Pll_bypass_E (Pll_control_E, 1, 26), // EPLL_BP 222 Pll_bypass_M (Pll_control_M, 1, 28), // MPLL_BP 223 224 Pll_multiplier_A (Pll_control_A, 0xfff, 20), // APLLM 225 Pll_multiplier_E (Pll_control_E, 0x3f, 20), // EPLLM (observed) 226 Pll_multiplier_M (Pll_control_M, 0xfff, 20), // MPLLM 227 228 Pll_input_division_A (Pll_control_A, 0x3f, 14), // APLLN 229 Pll_input_division_E (Pll_control_E, 0x3f, 14), // EPLLN 230 Pll_input_division_M (Pll_control_M, 0x3f, 14), // MPLLN 231 232 Pll_output_division1_A (Pll_control_A, 0x07, 11), // APLLOD1 233 Pll_output_division1_E (Pll_control_E, 0x07, 11), // EPLLOD1 234 Pll_output_division1_M (Pll_control_M, 0x07, 11), // MPLLOD1 235 236 Pll_output_division0_A (Pll_control_A, 0x07, 8), // APLLOD0 237 Pll_output_division0_E (Pll_control_E, 0x07, 8), // EPLLOD0 238 Pll_output_division0_M (Pll_control_M, 0x07, 8); // MPLLOD0 239 240 241 242 // Multiplexer instances. 243 244 #define Clocks(...) ((enum Clock_identifiers []) {__VA_ARGS__}) 245 246 static Mux mux_external (Clock_external), 247 mux_hclock0 (Clock_hclock0), 248 mux_hclock2 (Clock_hclock2), 249 mux_pclock (Clock_pclock), 250 mux_main (3, Clocks(Clock_none, Clock_external, Clock_pll_A)), 251 mux_core (3, Clocks(Clock_none, Clock_main, Clock_pll_M)), 252 mux_bus (4, Clocks(Clock_main, Clock_pll_M, Clock_pll_E, Clock_external)), 253 mux_dev (3, Clocks(Clock_main, Clock_pll_M, Clock_pll_E)), 254 mux_i2s (2, Clocks(Clock_main, Clock_pll_E)), 255 mux_i2s0_rx (Clock_i2s0), 256 mux_i2s0_tx (Clock_i2s1); 257 258 259 260 // Clock instances. 261 262 static Clock_null clock_none; 263 264 static Clock_passive clock_external; 265 266 // Note the use of extra parentheses due to the annoying C++ "most vexing parse" 267 // problem. See: https://en.wikipedia.org/wiki/Most_vexing_parse 268 269 static Clock clock_audio((Source(mux_hclock2)), (Control(Clock_gate_audio))), 270 271 clock_dma((Source(mux_hclock2)), (Control(Clock_gate_dma))), 272 273 clock_i2c((Source(mux_pclock)), (Control(Clock_gate_i2c0))), 274 275 clock_i2c0((Source(mux_pclock)), (Control(Clock_gate_i2c0))), 276 277 clock_i2c1((Source(mux_pclock)), (Control(Clock_gate_i2c1))), 278 279 clock_i2s0(Source(mux_i2s, Clock_source_i2s0), Control(Clock_gate_i2s0)), 280 281 clock_i2s1(Source(mux_i2s, Clock_source_i2s1), Control(Clock_gate_i2s1)), 282 283 clock_main(Source(mux_main, Clock_source_main), Control(Clock_gate_main)), 284 285 clock_mipi_csi((Source(mux_hclock0)), Control(Clock_gate_mipi_csi)), 286 287 clock_otg((Source(mux_hclock2)), (Control(Clock_gate_otg))), 288 289 clock_timer((Source(mux_pclock)), (Control(Clock_gate_timer))), 290 291 clock_uart0((Source(mux_external)), (Control(Clock_gate_uart0))), 292 293 clock_uart1((Source(mux_external)), (Control(Clock_gate_uart1))), 294 295 clock_uart2((Source(mux_external)), (Control(Clock_gate_uart2))), 296 297 clock_uart3((Source(mux_external)), (Control(Clock_gate_uart3))); 298 299 static Clock_divided 300 clock_can0(Source(mux_bus, Clock_source_can0), 301 Control(Clock_gate_can0, Clock_change_enable_can0, Clock_busy_can0), 302 Divider(Clock_divider_can0)), 303 304 clock_can1(Source(mux_bus, Clock_source_can1), 305 Control(Clock_gate_can1, Clock_change_enable_can1, Clock_busy_can1), 306 Divider(Clock_divider_can1)), 307 308 clock_cdbus(Source(mux_dev, Clock_source_cdbus), 309 Control(Clock_gate_cdbus, Clock_change_enable_cdbus, Clock_busy_cdbus), 310 Divider(Clock_divider_cdbus)), 311 312 clock_cim(Source(mux_dev, Clock_source_cim), 313 Control(Clock_gate_cim, Clock_change_enable_cim, Clock_busy_cim), 314 Divider(Clock_divider_cim)), 315 316 clock_cpu(Source(mux_core, Clock_source_cpu), 317 Control(Field::undefined, Clock_change_enable_cpu, Clock_busy_cpu), 318 Divider(Clock_divider_cpu)), 319 320 clock_ddr(Source(mux_core, Clock_source_ddr), 321 Control(Clock_gate_ddr, Clock_change_enable_ddr, Clock_busy_ddr), 322 Divider(Clock_divider_ddr)), 323 324 clock_hclock0(Source(mux_core, Clock_source_hclock0), 325 Control(Clock_gate_ahb0, Clock_change_enable_ahb0), 326 Divider(Clock_divider_hclock0)), 327 328 clock_hclock2(Source(mux_core, Clock_source_hclock2), 329 Control(Clock_gate_apb0, Clock_change_enable_ahb2), 330 Divider(Clock_divider_hclock2)), 331 332 clock_lcd_pixel(Source(mux_dev, Clock_source_lcd), 333 Control(Clock_gate_lcd_pixel, Clock_change_enable_lcd, Clock_busy_lcd), 334 Divider(Clock_divider_lcd)), 335 336 clock_mac(Source(mux_dev, Clock_source_mac), 337 Control(Clock_gate_gmac0, Clock_change_enable_mac, Clock_busy_mac), 338 Divider(Clock_divider_mac)), 339 340 clock_msc(Source(mux_dev, Clock_source_msc0), 341 Control(Clock_gate_msc0, Clock_change_enable_msc0, Clock_busy_msc0), 342 Divider(Clock_divider_msc0)), 343 344 clock_msc0(Source(mux_dev, Clock_source_msc0), 345 Control(Clock_gate_msc0, Clock_change_enable_msc0, Clock_busy_msc0), 346 Divider(Clock_divider_msc0)), 347 348 clock_msc1(Source(mux_dev, Clock_source_msc1), 349 Control(Clock_gate_msc1, Clock_change_enable_msc1, Clock_busy_msc1), 350 Divider(Clock_divider_msc1)), 351 352 clock_pclock(Source(mux_core, Clock_source_hclock2), 353 Control(Clock_gate_apb0, Clock_change_enable_ahb2), 354 Divider(Clock_divider_pclock)), 355 356 clock_pwm(Source(mux_dev, Clock_source_pwm), 357 Control(Clock_gate_pwm, Clock_change_enable_pwm, Clock_busy_pwm), 358 Divider(Clock_divider_pwm)), 359 360 clock_pwm0(Source(mux_dev, Clock_source_pwm), 361 Control(Clock_gate_pwm, Clock_change_enable_pwm, Clock_busy_pwm), 362 Divider(Clock_divider_pwm)), 363 364 clock_sfc(Source(mux_dev, Clock_source_sfc), 365 Control(Clock_gate_sfc, Clock_change_enable_sfc, Clock_busy_sfc), 366 Divider(Clock_divider_sfc)), 367 368 clock_ssi(Source(mux_dev, Clock_source_ssi), 369 Control(Clock_gate_ssi0, Clock_change_enable_ssi, Clock_busy_ssi), 370 Divider(Clock_divider_ssi)); 371 372 static Clock_divided_i2s 373 clock_i2s0_rx(Source(mux_i2s0_rx), 374 Control(Clock_gate_i2s0_rx), 375 Divider_i2s(Clock_divider_i2s0_m, Clock_divider_i2s0_n, 376 Clock_divider_i2s0_d, Clock_divider_i2s0_n_auto, 377 Clock_divider_i2s0_d_auto)), 378 379 clock_i2s0_tx(Source(mux_i2s0_tx), 380 Control(Clock_gate_i2s0_tx), 381 Divider_i2s(Clock_divider_i2s1_m, Clock_divider_i2s1_n, 382 Clock_divider_i2s1_d, Clock_divider_i2s1_n_auto, 383 Clock_divider_i2s1_d_auto)); 384 385 static Pll clock_pll_A(Source(mux_external), 386 Control_pll(Pll_enable_A, Pll_stable_A, Pll_bypass_A), 387 Divider_pll(Pll_multiplier_A, Pll_input_division_A, 388 Pll_output_division0_A, Pll_output_division1_A)), 389 390 clock_pll_E(Source(mux_external), 391 Control_pll(Pll_enable_E, Pll_stable_E, Pll_bypass_E), 392 Divider_pll(Pll_multiplier_E, Pll_input_division_E, 393 Pll_output_division0_E, Pll_output_division1_E)), 394 395 clock_pll_M(Source(mux_external), 396 Control_pll(Pll_enable_M, Pll_stable_M, Pll_bypass_M), 397 Divider_pll(Pll_multiplier_M, Pll_input_division_M, 398 Pll_output_division0_M, Pll_output_division1_M)); 399 400 401 402 // Clock register. 403 404 static Clock_base *clocks[Clock_identifier_count] = { 405 &clock_audio, 406 &clock_none, // Clock_aic_bitclk 407 &clock_none, // Clock_aic_pclk 408 &clock_can0, 409 &clock_can1, 410 &clock_cdbus, 411 &clock_cim, 412 &clock_cpu, 413 &clock_ddr, 414 &clock_dma, 415 &clock_none, // Clock_emac 416 &clock_external, 417 &clock_hclock0, 418 &clock_hclock2, 419 &clock_none, // Clock_hdmi 420 &clock_i2c, 421 &clock_i2c0, 422 &clock_i2c1, 423 &clock_i2s0, // supplies i2s0_rx 424 &clock_i2s0_rx, 425 &clock_i2s0_tx, 426 &clock_i2s1, // supplies i2s0_tx 427 &clock_none, // Clock_i2s1_rx 428 &clock_none, // Clock_i2s1_tx 429 &clock_none, // Clock_kbc 430 &clock_none, // Clock_lcd 431 &clock_lcd_pixel, 432 &clock_mac, 433 &clock_main, 434 &clock_mipi_csi, 435 &clock_msc, 436 &clock_msc0, 437 &clock_msc1, 438 &clock_none, 439 &clock_otg, 440 &clock_pclock, 441 &clock_pll_A, 442 &clock_pll_E, 443 &clock_pll_M, 444 &clock_pwm, 445 &clock_pwm0, 446 &clock_none, // Clock_pwm1 447 &clock_none, // Clock_scc 448 &clock_sfc, 449 &clock_none, // Clock_smb0 450 &clock_none, // Clock_smb1 451 &clock_none, // Clock_smb2 452 &clock_none, // Clock_smb3 453 &clock_none, // Clock_smb4 454 &clock_ssi, 455 &clock_timer, 456 &clock_uart0, 457 &clock_uart1, 458 &clock_uart2, 459 &clock_uart3, 460 &clock_none, // Clock_udc 461 &clock_none, // Clock_uhc 462 &clock_none, // Clock_uprt 463 }; 464 465 466 467 // If implemented as a Hw::Device, various properties would be 468 // initialised in the constructor and obtained from the device tree 469 // definitions. 470 471 Cpm_x1600_chip::Cpm_x1600_chip(l4_addr_t addr, uint32_t exclk_freq) 472 : _cpm_regs(addr, clocks, exclk_freq) 473 { 474 // add_cid("cpm"); 475 // add_cid("cpm-x1600"); 476 // register_property("exclk_freq", &exclk_freq); 477 } 478 479 const char * 480 Cpm_x1600_chip::clock_type(enum Clock_identifiers clock) 481 { 482 return clocks[clock]->clock_type(); 483 } 484 485 int 486 Cpm_x1600_chip::have_clock(enum Clock_identifiers clock) 487 { 488 return clocks[clock]->have_clock(_cpm_regs); 489 } 490 491 void 492 Cpm_x1600_chip::start_clock(enum Clock_identifiers clock) 493 { 494 clocks[clock]->start_clock(_cpm_regs); 495 } 496 497 void 498 Cpm_x1600_chip::stop_clock(enum Clock_identifiers clock) 499 { 500 clocks[clock]->stop_clock(_cpm_regs); 501 } 502 503 int 504 Cpm_x1600_chip::get_parameters(enum Clock_identifiers clock, uint32_t parameters[]) 505 { 506 Clock_divided_base *clk = dynamic_cast<Clock_divided_base *>(clocks[clock]); 507 508 if (clk != NULL) 509 return clk->get_parameters(_cpm_regs, parameters); 510 else 511 return 0; 512 } 513 514 int 515 Cpm_x1600_chip::set_parameters(enum Clock_identifiers clock, int num_parameters, uint32_t parameters[]) 516 { 517 Clock_divided_base *clk = dynamic_cast<Clock_divided_base *>(clocks[clock]); 518 519 if (clk != NULL) 520 return clk->set_parameters(_cpm_regs, num_parameters, parameters); 521 else 522 return 0; 523 } 524 525 uint8_t 526 Cpm_x1600_chip::get_source(enum Clock_identifiers clock) 527 { 528 Clock_active *clk = dynamic_cast<Clock_active *>(clocks[clock]); 529 530 if (clk != NULL) 531 return clk->get_source(_cpm_regs); 532 else 533 return 0; 534 } 535 536 enum Clock_identifiers 537 Cpm_x1600_chip::get_source_clock(enum Clock_identifiers clock) 538 { 539 Clock_active *clk = dynamic_cast<Clock_active *>(clocks[clock]); 540 541 if (clk != NULL) 542 return clk->get_source_clock(_cpm_regs); 543 else 544 return Clock_undefined; 545 } 546 547 void 548 Cpm_x1600_chip::set_source_clock(enum Clock_identifiers clock, enum Clock_identifiers source) 549 { 550 Clock_active *clk = dynamic_cast<Clock_active *>(clocks[clock]); 551 552 if (clk != NULL) 553 clk->set_source_clock(_cpm_regs, source); 554 } 555 556 void 557 Cpm_x1600_chip::set_source(enum Clock_identifiers clock, uint8_t source) 558 { 559 Clock_active *clk = dynamic_cast<Clock_active *>(clocks[clock]); 560 561 if (clk != NULL) 562 clk->set_source(_cpm_regs, source); 563 } 564 565 uint32_t 566 Cpm_x1600_chip::get_source_frequency(enum Clock_identifiers clock) 567 { 568 Clock_active *clk = dynamic_cast<Clock_active *>(clocks[clock]); 569 570 if (clk != NULL) 571 return clk->get_source_frequency(_cpm_regs); 572 else 573 return 0; 574 } 575 576 uint32_t 577 Cpm_x1600_chip::get_frequency(enum Clock_identifiers clock) 578 { 579 return clocks[clock]->get_frequency(_cpm_regs); 580 } 581 582 int 583 Cpm_x1600_chip::set_frequency(enum Clock_identifiers clock, uint32_t frequency) 584 { 585 Clock_divided_base *clk = dynamic_cast<Clock_divided_base *>(clocks[clock]); 586 587 if (clk != NULL) 588 return clk->set_frequency(_cpm_regs, frequency); 589 else 590 return 0; 591 } 592 593 594 595 // C language interface functions. 596 597 void 598 *x1600_cpm_init(l4_addr_t cpm_base) 599 { 600 /* Initialise the clock and power management peripheral with the 601 register memory region and a 24MHz EXCLK frequency. */ 602 603 return (void *) new Cpm_x1600_chip(cpm_base, 24000000); 604 } 605 606 const char * 607 x1600_cpm_clock_type(void *cpm, enum Clock_identifiers clock) 608 { 609 return static_cast<Cpm_x1600_chip *>(cpm)->clock_type(clock); 610 } 611 612 int 613 x1600_cpm_have_clock(void *cpm, enum Clock_identifiers clock) 614 { 615 return static_cast<Cpm_x1600_chip *>(cpm)->have_clock(clock); 616 } 617 618 void 619 x1600_cpm_start_clock(void *cpm, enum Clock_identifiers clock) 620 { 621 static_cast<Cpm_x1600_chip *>(cpm)->start_clock(clock); 622 } 623 624 void 625 x1600_cpm_stop_clock(void *cpm, enum Clock_identifiers clock) 626 { 627 static_cast<Cpm_x1600_chip *>(cpm)->stop_clock(clock); 628 } 629 630 int 631 x1600_cpm_get_parameters(void *cpm, enum Clock_identifiers clock, uint32_t parameters[]) 632 { 633 return static_cast<Cpm_x1600_chip *>(cpm)->get_parameters(clock, parameters); 634 } 635 636 int 637 x1600_cpm_set_parameters(void *cpm, enum Clock_identifiers clock, int num_parameters, uint32_t parameters[]) 638 { 639 return static_cast<Cpm_x1600_chip *>(cpm)->set_parameters(clock, num_parameters, parameters); 640 } 641 642 uint8_t 643 x1600_cpm_get_source(void *cpm, enum Clock_identifiers clock) 644 { 645 return static_cast<Cpm_x1600_chip *>(cpm)->get_source(clock); 646 } 647 648 void 649 x1600_cpm_set_source(void *cpm, enum Clock_identifiers clock, uint8_t source) 650 { 651 static_cast<Cpm_x1600_chip *>(cpm)->set_source(clock, source); 652 } 653 654 enum Clock_identifiers 655 x1600_cpm_get_source_clock(void *cpm, enum Clock_identifiers clock) 656 { 657 return static_cast<Cpm_x1600_chip *>(cpm)->get_source_clock(clock); 658 } 659 660 void 661 x1600_cpm_set_source_clock(void *cpm, enum Clock_identifiers clock, enum Clock_identifiers source) 662 { 663 static_cast<Cpm_x1600_chip *>(cpm)->set_source_clock(clock, source); 664 } 665 666 uint32_t 667 x1600_cpm_get_source_frequency(void *cpm, enum Clock_identifiers clock) 668 { 669 return static_cast<Cpm_x1600_chip *>(cpm)->get_source_frequency(clock); 670 } 671 672 uint32_t 673 x1600_cpm_get_frequency(void *cpm, enum Clock_identifiers clock) 674 { 675 return static_cast<Cpm_x1600_chip *>(cpm)->get_frequency(clock); 676 } 677 678 int 679 x1600_cpm_set_frequency(void *cpm, enum Clock_identifiers clock, uint32_t frequency) 680 { 681 return static_cast<Cpm_x1600_chip *>(cpm)->set_frequency(clock, frequency); 682 }