1 /* 2 * Clock and power management. This exposes the combined functionality 3 * provided by the jz4780 and related SoCs. The power management 4 * functionality could be exposed using a separate driver. 5 * 6 * Copyright (C) 2017, 2018, 2020, 2021, 2023 Paul Boddie <paul@boddie.org.uk> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 21 * Boston, MA 02110-1301, USA 22 */ 23 24 #include <l4/devices/hw_mmio_register_block.h> 25 #include "cpm-jz4780.h" 26 27 28 29 // Register locations. 30 31 enum Regs : unsigned 32 { 33 Clock_control = 0x000, // CPCCR 34 Low_power_control = 0x004, // LCR 35 Clock_gate0 = 0x020, // CLKGR0 36 Clock_gate1 = 0x028, // CLKGR1 37 Sleep_control = 0x024, // OPCR (oscillator and power control) 38 Clock_status = 0x0d4, // CPCSR 39 40 Divider_bch = 0x0ac, // BCHCDR 41 Divider_cim = 0x07c, // CIMCDR 42 Divider_ddr = 0x02c, // DDRCDR 43 Divider_gpu = 0x088, // GPUCDR 44 Divider_hdmi = 0x08c, // HDMICDR 45 Divider_i2s0 = 0x060, // I2SCDR 46 Divider_i2s1 = 0x0a0, // I2S1CDR 47 Divider_lcd0 = 0x054, // LP0CDR 48 Divider_lcd1 = 0x064, // LP1CDR 49 Divider_msc0 = 0x068, // MSC0CDR 50 Divider_msc1 = 0x0a4, // MSC1CDR 51 Divider_msc2 = 0x0a8, // MSC2CDR 52 Divider_pcm = 0x084, // PCMCDR 53 Divider_ssi = 0x074, // SSICDR 54 Divider_uhc = 0x06c, // UHCCDR 55 Divider_vpu = 0x030, // VPUCDR 56 57 Cpm_interrupt = 0x0b0, // CPM_INTR 58 Cpm_interrupt_en = 0x0b4, // CPM_INTRE 59 Cpm_scratch = 0x034, // CPSPR 60 Cpm_scratch_prot = 0x038, // CPSPPR 61 62 Usb_param_control0 = 0x03c, // USBPCR 63 Usb_reset_detect = 0x040, // USBRDT 64 Usb_vbus_jitter = 0x044, // USBVBFIL 65 Usb_param_control1 = 0x048, // USBPCR1 66 67 Pll_control = 0x00c, // CPPCR 68 Pll_control_A = 0x010, // CPAPCR 69 Pll_control_M = 0x014, // CPMPCR 70 Pll_control_E = 0x018, // CPEPCR 71 Pll_control_V = 0x01c, // CPVPCR 72 }; 73 74 75 76 // Register field definitions. 77 78 static Field Clock_source_main (Clock_control, 3, 30), // SEL_SRC (output to SCLK_A) 79 Clock_source_cpu (Clock_control, 3, 28), // SEL_CPLL (output to CCLK) 80 Clock_source_hclock0 (Clock_control, 3, 26), // SEL_H0PLL (output to AHB0) 81 Clock_source_hclock2 (Clock_control, 3, 24), // SEL_H2PLL (output to AHB2) 82 Clock_source_bch (Divider_bch, 3, 30), // BPCS 83 Clock_source_cim (Divider_cim, 1, 31), // CIMPCS 84 Clock_source_ddr (Divider_ddr, 3, 30), // DCS 85 Clock_source_gpu (Divider_gpu, 3, 30), // GPCS 86 Clock_source_hdmi (Divider_hdmi, 3, 30), // HPCS 87 Clock_source_i2s0 (Divider_i2s0, 3, 30), // I2CS, I2PCS 88 Clock_source_i2s1 (Divider_i2s1, 3, 30), // I2CS, I2PCS 89 Clock_source_lcd0 (Divider_lcd0, 3, 30), // LPCS 90 Clock_source_lcd1 (Divider_lcd1, 3, 30), // LPCS 91 Clock_source_msc (Divider_msc0, 3, 30), // MPCS 92 Clock_source_pcm (Divider_pcm, 7, 29), // PCMS, PCMPCS 93 Clock_source_ssi (Divider_ssi, 3, 30), // SCS, SPCS 94 Clock_source_uhc (Divider_uhc, 3, 30), // UHCS 95 Clock_source_usb_phy (Usb_param_control1, 3, 24), // REFCLKDIV 96 Clock_source_vpu (Divider_vpu, 3, 30), // VCS 97 98 Clock_busy_cpu (Clock_status, 1, 0), 99 Clock_busy_hclock0 (Clock_status, 1, 1), 100 Clock_busy_hclock2 (Clock_status, 1, 2), 101 Clock_busy_bch (Divider_bch, 1, 28), 102 Clock_busy_cim (Divider_cim, 1, 29), 103 Clock_busy_ddr (Divider_ddr, 1, 28), 104 Clock_busy_gpu (Divider_gpu, 1, 28), 105 Clock_busy_hdmi (Divider_hdmi, 1, 28), 106 Clock_busy_i2s0 (Divider_i2s0, 1, 28), 107 Clock_busy_i2s1 (Divider_i2s1, 1, 28), 108 Clock_busy_lcd0 (Divider_lcd0, 1, 27), 109 Clock_busy_lcd1 (Divider_lcd1, 1, 27), 110 Clock_busy_msc0 (Divider_msc0, 1, 28), 111 Clock_busy_msc1 (Divider_msc1, 1, 28), 112 Clock_busy_msc2 (Divider_msc2, 1, 28), 113 Clock_busy_pcm (Divider_pcm, 1, 27), 114 Clock_busy_ssi (Divider_ssi, 1, 28), 115 Clock_busy_uhc (Divider_uhc, 1, 28), 116 Clock_busy_vpu (Divider_vpu, 1, 28), 117 118 Clock_change_enable_cpu (Clock_control, 1, 22), 119 Clock_change_enable_ahb0 (Clock_control, 1, 21), 120 Clock_change_enable_ahb2 (Clock_control, 1, 20), 121 Clock_change_enable_bch (Divider_bch, 1, 29), 122 Clock_change_enable_cim (Divider_cim, 1, 30), 123 Clock_change_enable_ddr (Divider_ddr, 1, 29), 124 Clock_change_enable_gpu (Divider_gpu, 1, 29), 125 Clock_change_enable_hdmi (Divider_hdmi, 1, 29), 126 Clock_change_enable_i2s0 (Divider_i2s0, 1, 29), 127 Clock_change_enable_i2s1 (Divider_i2s1, 1, 29), 128 Clock_change_enable_lcd0 (Divider_lcd0, 1, 28), 129 Clock_change_enable_lcd1 (Divider_lcd1, 1, 28), 130 Clock_change_enable_msc0 (Divider_msc0, 1, 29), 131 Clock_change_enable_msc1 (Divider_msc1, 1, 29), 132 Clock_change_enable_msc2 (Divider_msc2, 1, 29), 133 Clock_change_enable_pcm (Divider_pcm, 1, 28), 134 Clock_change_enable_ssi (Divider_ssi, 1, 29), 135 Clock_change_enable_uhc (Divider_uhc, 1, 29), 136 Clock_change_enable_vpu (Divider_vpu, 1, 29), 137 138 Clock_divider_cpu (Clock_control, 0x0f, 0), // CDIV 139 Clock_divider_hclock0 (Clock_control, 0x0f, 8), // H0DIV (fast AHB peripherals) 140 Clock_divider_hclock2 (Clock_control, 0x0f, 12), // H2DIV (fast AHB peripherals) 141 Clock_divider_l2cache (Clock_control, 0x0f, 4), // L2CDIV 142 Clock_divider_pclock (Clock_control, 0x0f, 16), // PDIV (slow APB peripherals) 143 Clock_divider_bch (Divider_bch, 0x0f, 0), // BCHCDR 144 Clock_divider_cim (Divider_cim, 0xff, 0), // CIMCDR 145 Clock_divider_ddr (Divider_ddr, 0x0f, 0), // DDRCDR 146 Clock_divider_gpu (Divider_gpu, 0x0f, 0), // GPUCDR 147 Clock_divider_hdmi (Divider_hdmi, 0xff, 0), // HDMICDR 148 Clock_divider_i2s0 (Divider_i2s0, 0xff, 0), // I2SCDR 149 Clock_divider_i2s1 (Divider_i2s1, 0xff, 0), // I2SCDR 150 Clock_divider_lcd0 (Divider_lcd0, 0xff, 0), // LPCDR 151 Clock_divider_lcd1 (Divider_lcd1, 0xff, 0), // LPCDR 152 Clock_divider_msc0 (Divider_msc0, 0xff, 0), // MSC0CDR 153 Clock_divider_msc1 (Divider_msc1, 0xff, 0), // MSC1CDR 154 Clock_divider_msc2 (Divider_msc2, 0xff, 0), // MSC2CDR 155 Clock_divider_pcm (Divider_pcm, 0xff, 0), // PCMCDR 156 Clock_divider_ssi (Divider_ssi, 0xff, 0), // SSICDR 157 Clock_divider_uhc (Divider_uhc, 0xff, 0), // UHCCDR 158 Clock_divider_vpu (Divider_vpu, 0x0f, 0), // VPUCDR 159 160 Clock_gate_main (Clock_control, 1, 23, true), // GATE_SCLKA 161 Clock_gate_ddr (Clock_gate0, 3, 30, true), // DDR1, DDR0 162 Clock_gate_ipu (Clock_gate0, 1, 29, true), // IPU 163 Clock_gate_lcd (Clock_gate0, 3, 27, true), // LCD, TVE 164 Clock_gate_cim (Clock_gate0, 1, 26, true), // CIM 165 Clock_gate_i2c2 (Clock_gate0, 1, 25, true), // SMB2 166 Clock_gate_uhc (Clock_gate0, 1, 24, true), // UHC 167 Clock_gate_mac (Clock_gate0, 1, 23, true), // MAC 168 Clock_gate_gps (Clock_gate0, 1, 22, true), // GPS 169 Clock_gate_dma (Clock_gate0, 1, 21, true), // PDMA 170 //Clock_gate_ssi2 (Clock_gate0, 1, 20, true), // SSI2 171 Clock_gate_ssi1 (Clock_gate0, 1, 19, true), // SSI1 172 Clock_gate_uart3 (Clock_gate0, 1, 18, true), // UART3 173 Clock_gate_uart2 (Clock_gate0, 1, 17, true), // UART2 174 Clock_gate_uart1 (Clock_gate0, 1, 16, true), // UART1 175 Clock_gate_uart0 (Clock_gate0, 1, 15, true), // UART0 176 Clock_gate_sadc (Clock_gate0, 1, 14, true), // SADC 177 Clock_gate_kbc (Clock_gate0, 1, 13, true), // KBC 178 Clock_gate_msc2 (Clock_gate0, 1, 12, true), // MSC2 179 Clock_gate_msc1 (Clock_gate0, 1, 11, true), // MSC1 180 Clock_gate_owi (Clock_gate0, 1, 10, true), // OWI 181 Clock_gate_tssi0 (Clock_gate0, 1, 9, true), // TSSI0 182 Clock_gate_aic0 (Clock_gate0, 1, 8, true), // AIC0 183 Clock_gate_scc (Clock_gate0, 1, 7, true), // SCC 184 Clock_gate_i2c1 (Clock_gate0, 1, 6, true), // SMB1 185 Clock_gate_i2c0 (Clock_gate0, 1, 5, true), // SMB0 186 Clock_gate_ssi0 (Clock_gate0, 1, 4, true), // SSI0 187 Clock_gate_msc0 (Clock_gate0, 1, 3, true), // MSC0 188 Clock_gate_otg0 (Clock_gate0, 1, 2, true), // OTG0 189 Clock_gate_bch (Clock_gate0, 1, 1, true), // BCH 190 Clock_gate_nemc (Clock_gate0, 1, 0, true), // NEMC 191 Clock_gate_cpu1 (Clock_gate1, 1, 15, true), // P1 192 Clock_gate_x2d (Clock_gate1, 1, 14, true), // X2D 193 Clock_gate_des (Clock_gate1, 1, 13, true), // DES 194 Clock_gate_i2c4 (Clock_gate1, 1, 12, true), // SMB4 195 Clock_gate_ahb_mon (Clock_gate1, 1, 11, true), // AHB_MON 196 Clock_gate_uart4 (Clock_gate1, 1, 10, true), // UART4 197 Clock_gate_hdmi (Clock_gate1, 1, 9, true), // HDMI 198 Clock_gate_otg1 (Clock_gate1, 1, 8, true), // OTG1 199 Clock_gate_gpvlc (Clock_gate1, 1, 7, true), // GPVLC 200 Clock_gate_aic1 (Clock_gate1, 1, 6, true), // AIC1 201 Clock_gate_compress (Clock_gate1, 1, 5, true), // COMPRESS 202 Clock_gate_gpu (Clock_gate1, 1, 4, true), // GPU 203 Clock_gate_pcm (Clock_gate1, 1, 3, true), // PCM 204 Clock_gate_vpu (Clock_gate1, 1, 2, true), // VPU 205 Clock_gate_tssi1 (Clock_gate1, 1, 1, true), // TSSI1 206 Clock_gate_i2c3 (Clock_gate1, 1, 0, true), // I2C3 207 208 Pll_enable_A (Pll_control_A, 1, 0), // APLLEN 209 Pll_enable_E (Pll_control_E, 1, 0), // EPLLEN 210 Pll_enable_M (Pll_control_M, 1, 0), // MPLLEN 211 Pll_enable_V (Pll_control_V, 1, 0), // VPLLEN 212 213 Pll_stable_A (Pll_control_A, 1, 4), // APLL_ON 214 Pll_stable_E (Pll_control_E, 1, 4), // EPLL_ON 215 Pll_stable_M (Pll_control_M, 1, 4), // MPLL_ON 216 Pll_stable_V (Pll_control_V, 1, 4), // VPLL_ON 217 218 Pll_bypass_A (Pll_control_A, 1, 1), // APLL_BP 219 Pll_bypass_E (Pll_control_E, 1, 1), // EPLL_BP 220 Pll_bypass_M (Pll_control_M, 1, 1), // MPLL_BP 221 Pll_bypass_V (Pll_control_V, 1, 1), // VPLL_BP 222 223 Pll_multiplier_A (Pll_control_A, 0x1fff, 19), // APLLM 224 Pll_multiplier_E (Pll_control_E, 0x1fff, 19), // EPLLM 225 Pll_multiplier_M (Pll_control_M, 0x1fff, 19), // MPLLM 226 Pll_multiplier_V (Pll_control_V, 0x1fff, 19), // VPLLM 227 228 Pll_input_division_A (Pll_control_A, 0x3f, 13), // APLLN 229 Pll_input_division_E (Pll_control_E, 0x3f, 13), // EPLLN 230 Pll_input_division_M (Pll_control_M, 0x3f, 13), // MPLLN 231 Pll_input_division_V (Pll_control_V, 0x3f, 13), // VPLLN 232 233 Pll_output_division_A (Pll_control_A, 0x0f, 9), // APLLOD 234 Pll_output_division_E (Pll_control_E, 0x0f, 9), // EPLLOD 235 Pll_output_division_M (Pll_control_M, 0x0f, 9), // MPLLOD 236 Pll_output_division_V (Pll_control_V, 0x0f, 9); // VPLLOD 237 238 239 240 // Multiplexer instances. 241 242 #define Clocks(...) ((enum Clock_identifiers []) {__VA_ARGS__}) 243 #define Specific(CLOCK) ((enum Clock_identifiers) (CLOCK)) 244 245 static Mux mux_external (Clock_external), 246 247 // Clocks being propagated to others. 248 249 mux_clock_ssi (Clock_ssi), 250 mux_clock_msc (Clock_msc), 251 mux_hclock2 (Clock_hclock2), 252 mux_hclock2_pclock (Clock_hclock2_pclock), 253 mux_pclock (Clock_pclock), 254 255 // Main bus and peripheral clock sources. 256 257 mux_ahb2 (4, Clocks(Clock_none, Clock_main, Clock_pll_M, Clock_rtc_external)), 258 mux_core (4, Clocks(Clock_none, Clock_main, Clock_pll_M, Clock_pll_E)), 259 mux_main (4, Clocks(Clock_none, Clock_pll_A, Clock_external, Clock_rtc_external)), 260 261 // Memory and device clock sources. 262 263 mux_cim (2, Clocks(Clock_main, Clock_pll_M)), 264 mux_dev (3, Clocks(Clock_none, Clock_main, Clock_pll_M)), 265 mux_lcd (3, Clocks(Clock_main, Clock_pll_M, Clock_pll_V)), 266 mux_usb (3, Clocks(Clock_main, Clock_pll_M, Clock_pll_E /* , OTG PHY */)), 267 mux_usb_phy (4, Clocks(Specific(Clock_usb_phy_12MHz), Specific(Clock_usb_phy_24MHz), 268 Specific(Clock_usb_phy_48MHz), Specific(Clock_usb_phy_19_2MHz))), 269 270 // Clock selectors involving the external clock. 271 272 mux_i2s (4, Clocks(Clock_external, Clock_external, Clock_main, Clock_pll_E)), 273 mux_pcm (8, Clocks(Clock_external, Clock_external, Clock_external, Clock_external, 274 Clock_main, Clock_pll_M, Clock_pll_E, Clock_pll_V)), 275 mux_ssi (4, Clocks(Clock_external, Clock_external, Clock_main, Clock_pll_M)); 276 277 278 279 // Clock instances. 280 281 static Clock_null clock_none; 282 283 static Clock_passive clock_external(48000000), 284 clock_rtc_external(32768), 285 clock_usb_phy_12MHz(12000000), 286 clock_usb_phy_19_2MHz(19200000), 287 clock_usb_phy_24MHz(24000000), 288 clock_usb_phy_48MHz(48000000); 289 290 291 292 // Note the use of extra parentheses due to the annoying C++ "most vexing parse" 293 // problem. See: https://en.wikipedia.org/wiki/Most_vexing_parse 294 295 static Clock clock_ahb_mon((Source(mux_external)), (Control(Clock_gate_ahb_mon))), 296 297 clock_compress((Source(mux_external)), (Control(Clock_gate_compress))), 298 299 clock_des((Source(mux_external)), (Control(Clock_gate_des))), 300 301 clock_dma((Source(mux_external)), (Control(Clock_gate_dma))), 302 303 clock_gps((Source(mux_external)), (Control(Clock_gate_gps))), 304 305 clock_gpvlc((Source(mux_external)), (Control(Clock_gate_gpvlc))), 306 307 clock_i2c0((Source(mux_pclock)), (Control(Clock_gate_i2c0))), 308 309 clock_i2c1((Source(mux_pclock)), (Control(Clock_gate_i2c1))), 310 311 clock_i2c2((Source(mux_pclock)), (Control(Clock_gate_i2c2))), 312 313 clock_i2c3((Source(mux_pclock)), (Control(Clock_gate_i2c3))), 314 315 clock_i2c4((Source(mux_pclock)), (Control(Clock_gate_i2c4))), 316 317 clock_i2s0(Source(mux_i2s, Clock_source_i2s0), Control(Clock_gate_aic0)), 318 319 clock_i2s1(Source(mux_i2s, Clock_source_i2s1), Control(Clock_gate_aic1)), 320 321 clock_ipu((Source(mux_external)), (Control(Clock_gate_ipu))), 322 323 clock_kbc((Source(mux_external)), (Control(Clock_gate_kbc))), 324 325 clock_lcd((Source(mux_external)), (Control(Clock_gate_lcd))), 326 327 clock_main(Source(mux_main, Clock_source_main), Control(Clock_gate_main)), 328 329 clock_mac((Source(mux_external)), (Control(Clock_gate_mac))), 330 331 clock_msc((Source(mux_dev, Clock_source_msc))), 332 333 clock_nemc((Source(mux_hclock2)), (Control(Clock_gate_nemc))), 334 335 clock_otg0((Source(mux_external)), (Control(Clock_gate_otg0))), 336 337 clock_otg1((Source(mux_external)), (Control(Clock_gate_otg1))), 338 339 clock_owi((Source(mux_external)), (Control(Clock_gate_owi))), 340 341 clock_sadc((Source(mux_external)), (Control(Clock_gate_sadc))), 342 343 clock_scc((Source(mux_external)), (Control(Clock_gate_scc))), 344 345 clock_tssi0((Source(mux_external)), (Control(Clock_gate_tssi0))), 346 347 clock_tssi1((Source(mux_external)), (Control(Clock_gate_tssi1))), 348 349 clock_uart0((Source(mux_external)), (Control(Clock_gate_uart0))), 350 351 clock_uart1((Source(mux_external)), (Control(Clock_gate_uart1))), 352 353 clock_uart2((Source(mux_external)), (Control(Clock_gate_uart2))), 354 355 clock_uart3((Source(mux_external)), (Control(Clock_gate_uart3))), 356 357 clock_uart4((Source(mux_external)), (Control(Clock_gate_uart4))), 358 359 clock_usb_phy(Source(mux_usb_phy, Clock_source_usb_phy)), 360 361 clock_x2d((Source(mux_external)), (Control(Clock_gate_x2d))), 362 363 // Special parent clock for hclock2 and pclock. 364 365 clock_hclock2_pclock(Source(mux_ahb2, Clock_source_hclock2)), 366 367 // SSI channel clocks depending on a common parent divider. 368 369 clock_ssi0((Source(mux_clock_ssi)), Control(Clock_gate_ssi0)), 370 371 clock_ssi1((Source(mux_clock_ssi)), Control(Clock_gate_ssi1)); 372 373 static Clock_divided 374 clock_bch(Source(mux_core, Clock_source_bch), 375 Control(Clock_gate_bch, Clock_change_enable_bch, Clock_busy_bch), 376 Divider(Clock_divider_bch)), 377 378 clock_cim(Source(mux_cim, Clock_source_cim), 379 Control(Clock_gate_cim, Clock_change_enable_cim, Clock_busy_cim), 380 Divider(Clock_divider_cim)), 381 382 clock_cpu(Source(mux_core, Clock_source_cpu), 383 Control(Field::undefined, Clock_change_enable_cpu, Clock_busy_cpu), 384 Divider(Clock_divider_cpu)), 385 386 clock_ddr(Source(mux_dev, Clock_source_ddr), 387 Control(Clock_gate_ddr, Clock_change_enable_ddr, Clock_busy_ddr), 388 Divider(Clock_divider_ddr)), 389 390 clock_gpu(Source(mux_core, Clock_source_gpu), 391 Control(Clock_gate_gpu, Clock_change_enable_gpu, Clock_busy_gpu), 392 Divider(Clock_divider_gpu)), 393 394 clock_hclock0(Source(mux_core, Clock_source_hclock0), 395 Control(Field::undefined, Clock_change_enable_ahb0), 396 Divider(Clock_divider_hclock0)), 397 398 clock_hclock2(Source(mux_hclock2_pclock), 399 Control(Field::undefined, Clock_change_enable_ahb2), 400 Divider(Clock_divider_hclock2)), 401 402 clock_hdmi(Source(mux_lcd, Clock_source_hdmi), 403 Control(Clock_gate_hdmi, Clock_change_enable_hdmi, Clock_busy_hdmi), 404 Divider(Clock_divider_hdmi)), 405 406 clock_l2cache(Source(mux_core, Clock_source_cpu), 407 Control(Field::undefined, Clock_change_enable_cpu, Clock_busy_cpu), 408 Divider(Clock_divider_l2cache)), 409 410 clock_lcd_pixel0(Source(mux_lcd, Clock_source_lcd0), 411 Control(Clock_gate_lcd, Clock_change_enable_lcd0, Clock_busy_lcd0), 412 Divider(Clock_divider_lcd0)), 413 414 clock_lcd_pixel1(Source(mux_lcd, Clock_source_lcd1), 415 Control(Clock_gate_lcd, Clock_change_enable_lcd1, Clock_busy_lcd1), 416 Divider(Clock_divider_lcd1)), 417 418 clock_msc0(Source(mux_clock_msc), 419 Control(Clock_gate_msc0, Clock_change_enable_msc0, Clock_busy_msc0), 420 Divider(Clock_divider_msc0, 2)), 421 422 clock_msc1(Source(mux_clock_msc), 423 Control(Clock_gate_msc1, Clock_change_enable_msc1, Clock_busy_msc1), 424 Divider(Clock_divider_msc1, 2)), 425 426 clock_msc2(Source(mux_clock_msc), 427 Control(Clock_gate_msc2, Clock_change_enable_msc2, Clock_busy_msc2), 428 Divider(Clock_divider_msc2, 2)), 429 430 clock_pcm(Source(mux_pcm, Clock_source_pcm), 431 Control(Clock_gate_pcm, Clock_change_enable_pcm, Clock_busy_pcm), 432 Divider(Clock_divider_pcm)), 433 434 clock_pclock(Source(mux_hclock2_pclock), 435 Control(Field::undefined, Clock_change_enable_ahb2), 436 Divider(Clock_divider_pclock)), 437 438 clock_ssi(Source(mux_ssi, Clock_source_ssi), 439 Control(Field::undefined, Clock_change_enable_ssi, Clock_busy_ssi), 440 Divider(Clock_divider_ssi)), 441 442 clock_uhc(Source(mux_usb, Clock_source_uhc), 443 Control(Clock_gate_uhc, Clock_change_enable_uhc, Clock_busy_uhc), 444 Divider(Clock_divider_uhc)), 445 446 clock_vpu(Source(mux_core, Clock_source_vpu), 447 Control(Clock_gate_vpu, Clock_change_enable_vpu, Clock_busy_vpu), 448 Divider(Clock_divider_vpu)); 449 450 static Clock_divided_fixed 451 clock_external_div_512((Source(mux_external)), (Divider_fixed(512))); 452 453 const double jz4780_pll_intermediate_min = 300000000, 454 jz4780_pll_intermediate_max = 1500000000; 455 456 static Pll clock_pll_A(Source(mux_external), 457 Control_pll(Pll_enable_A, Pll_stable_A, Pll_bypass_A), 458 Divider_pll(Pll_multiplier_A, Pll_input_division_A, 459 Pll_output_division_A, 460 jz4780_pll_intermediate_min, jz4780_pll_intermediate_max, 461 true)), 462 463 clock_pll_E(Source(mux_external), 464 Control_pll(Pll_enable_E, Pll_stable_E, Pll_bypass_E), 465 Divider_pll(Pll_multiplier_E, Pll_input_division_E, 466 Pll_output_division_E, 467 jz4780_pll_intermediate_min, jz4780_pll_intermediate_max, 468 true)), 469 470 clock_pll_M(Source(mux_external), 471 Control_pll(Pll_enable_M, Pll_stable_M, Pll_bypass_M), 472 Divider_pll(Pll_multiplier_M, Pll_input_division_M, 473 Pll_output_division_M, 474 jz4780_pll_intermediate_min, jz4780_pll_intermediate_max, 475 true)), 476 477 clock_pll_V(Source(mux_external), 478 Control_pll(Pll_enable_V, Pll_stable_V, Pll_bypass_V), 479 Divider_pll(Pll_multiplier_V, Pll_input_division_V, 480 Pll_output_division_V, 481 jz4780_pll_intermediate_min, jz4780_pll_intermediate_max, 482 true)); 483 484 485 486 // Clock register. 487 488 static Clock_base *clocks[Clock_jz4780_identifier_count] = { 489 &clock_none, 490 491 &clock_none, // Clock_aic 492 &clock_none, // Clock_aic_bitclk 493 &clock_none, // Clock_aic_pclk 494 &clock_none, // Clock_can0 495 &clock_none, // Clock_can1 496 &clock_none, // Clock_cdbus 497 &clock_cim, 498 &clock_cpu, 499 &clock_ddr, 500 &clock_dma, 501 &clock_none, // Clock_emac 502 &clock_external, 503 &clock_external_div_512, 504 &clock_hclock0, 505 &clock_hclock2, 506 &clock_hclock2_pclock, 507 &clock_hdmi, 508 &clock_i2c0, 509 &clock_i2c1, 510 &clock_i2c2, 511 &clock_i2c3, 512 &clock_i2c4, 513 &clock_i2s0, 514 &clock_none, // Clock_i2s0_rx 515 &clock_none, // Clock_i2s0_tx 516 &clock_i2s1, 517 &clock_none, // Clock_i2s1_rx 518 &clock_none, // Clock_i2s1_tx 519 &clock_none, // Clock_kbc 520 &clock_l2cache, 521 &clock_lcd, 522 &clock_lcd_pixel0, 523 &clock_lcd_pixel1, 524 &clock_mac, 525 &clock_main, 526 &clock_none, // Clock_mipi_csi 527 &clock_msc, 528 &clock_msc0, 529 &clock_msc1, 530 &clock_msc2, 531 &clock_nemc, 532 &clock_otg0, 533 &clock_otg1, 534 &clock_pclock, 535 &clock_pcm, 536 &clock_pll_A, 537 &clock_pll_E, 538 &clock_pll_M, 539 &clock_pll_V, 540 &clock_none, // Clock_pwm0 541 &clock_none, // Clock_pwm1 542 &clock_external_div_512,// Clock_rtc 543 &clock_rtc_external, 544 &clock_sadc, 545 &clock_scc, 546 &clock_none, // Clock_sfc 547 &clock_ssi, 548 &clock_ssi0, 549 &clock_ssi1, 550 &clock_none, // Clock_ssi2 551 &clock_none, // Clock_timer 552 &clock_uart0, 553 &clock_uart1, 554 &clock_uart2, 555 &clock_uart3, 556 &clock_uart4, 557 &clock_none, // Clock_udc 558 &clock_uhc, 559 &clock_none, // Clock_uprt 560 &clock_usb_phy, 561 &clock_vpu, 562 563 /* JZ4780-specific clocks. */ 564 565 &clock_usb_phy_12MHz, 566 &clock_usb_phy_19_2MHz, 567 &clock_usb_phy_24MHz, 568 &clock_usb_phy_48MHz, 569 }; 570 571 572 573 // Peripheral abstraction. 574 575 Cpm_jz4780_chip::Cpm_jz4780_chip(l4_addr_t addr) 576 : Cpm_chip(addr, clocks) 577 { 578 } 579 580 581 582 // C language interface functions. 583 584 void 585 *jz4780_cpm_init(l4_addr_t cpm_base) 586 { 587 return (void *) new Cpm_jz4780_chip(cpm_base); 588 } 589 590 const char * 591 jz4780_cpm_clock_type(void *cpm, enum Clock_identifiers clock) 592 { 593 return static_cast<Cpm_jz4780_chip *>(cpm)->clock_type(clock); 594 } 595 596 int 597 jz4780_cpm_have_clock(void *cpm, enum Clock_identifiers clock) 598 { 599 return static_cast<Cpm_jz4780_chip *>(cpm)->have_clock(clock); 600 } 601 602 void 603 jz4780_cpm_start_clock(void *cpm, enum Clock_identifiers clock) 604 { 605 static_cast<Cpm_jz4780_chip *>(cpm)->start_clock(clock); 606 } 607 608 void 609 jz4780_cpm_stop_clock(void *cpm, enum Clock_identifiers clock) 610 { 611 static_cast<Cpm_jz4780_chip *>(cpm)->stop_clock(clock); 612 } 613 614 int 615 jz4780_cpm_get_parameters(void *cpm, enum Clock_identifiers clock, uint32_t parameters[]) 616 { 617 return static_cast<Cpm_jz4780_chip *>(cpm)->get_parameters(clock, parameters); 618 } 619 620 int 621 jz4780_cpm_set_parameters(void *cpm, enum Clock_identifiers clock, int num_parameters, uint32_t parameters[]) 622 { 623 return static_cast<Cpm_jz4780_chip *>(cpm)->set_parameters(clock, num_parameters, parameters); 624 } 625 626 uint8_t 627 jz4780_cpm_get_source(void *cpm, enum Clock_identifiers clock) 628 { 629 return static_cast<Cpm_jz4780_chip *>(cpm)->get_source(clock); 630 } 631 632 void 633 jz4780_cpm_set_source(void *cpm, enum Clock_identifiers clock, uint8_t source) 634 { 635 static_cast<Cpm_jz4780_chip *>(cpm)->set_source(clock, source); 636 } 637 638 enum Clock_identifiers 639 jz4780_cpm_get_source_clock(void *cpm, enum Clock_identifiers clock) 640 { 641 return static_cast<Cpm_jz4780_chip *>(cpm)->get_source_clock(clock); 642 } 643 644 void 645 jz4780_cpm_set_source_clock(void *cpm, enum Clock_identifiers clock, enum Clock_identifiers source) 646 { 647 static_cast<Cpm_jz4780_chip *>(cpm)->set_source_clock(clock, source); 648 } 649 650 uint64_t 651 jz4780_cpm_get_source_frequency(void *cpm, enum Clock_identifiers clock) 652 { 653 return static_cast<Cpm_jz4780_chip *>(cpm)->get_source_frequency(clock); 654 } 655 656 uint64_t 657 jz4780_cpm_get_frequency(void *cpm, enum Clock_identifiers clock) 658 { 659 return static_cast<Cpm_jz4780_chip *>(cpm)->get_frequency(clock); 660 } 661 662 int 663 jz4780_cpm_set_frequency(void *cpm, enum Clock_identifiers clock, uint64_t frequency) 664 { 665 return static_cast<Cpm_jz4780_chip *>(cpm)->set_frequency(clock, frequency); 666 }