1 /* 2 * Copyright (C) 2017, 2018 Paul Boddie <paul@boddie.org.uk> 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 17 * Boston, MA 02110-1301, USA 18 */ 19 20 #include <l4/devices/i2c-jz4780.h> 21 #include <l4/devices/hw_mmio_register_block.h> 22 23 #include <l4/sys/icu.h> 24 #include <l4/util/util.h> 25 #include <sys/time.h> 26 27 #include <cstdio> 28 29 /* 30 I2C pins: 31 32 I2C0: PD30/SMB0_SDA, PD31/SMB0_SCK 33 I2C1: PD30/SMB1_SDA, PD31/SMB1_SCK (pulled up on CI20) 34 I2C2: PF16/SMB2_SDA, PF17/SMB2_SCK 35 PWM: PD10/SMB3_SDA, PD11/SMB3_SCK 36 PWM: PE3/SMB4_SDA, PE4/SMB4_SCK 37 I2C4: PE12/SMB4_SDA, PE13/SMB4_SCK 38 HDMI: PF25/SMB4_SDA/DDCSDA, PF24/SMB4_SCK/DDCSCK 39 40 See: http://mipscreator.imgtec.com/CI20/hardware/board/ci20_jz4780_v2.0.pdf 41 */ 42 43 enum Regs 44 { 45 Smb_control = 0x000, // SMBCON 46 Smb_target_address = 0x004, // SMBTAR 47 Smb_slave_address = 0x008, // SMBSAR 48 Smb_data_command = 0x010, // SMBDC 49 Std_high_count = 0x014, // SMBSHCNT 50 Std_low_count = 0x018, // SMBSLCNT 51 Fast_high_count = 0x01c, // SMBFHCNT 52 Fast_low_count = 0x020, // SMBFLCNT 53 Int_status = 0x02c, // SMBINTST (read-only) 54 Int_mask = 0x030, // SMBINTM 55 56 Rx_fifo_thold = 0x038, // SMBRXTL 57 Tx_fifo_thold = 0x03c, // SMBTXTL 58 Int_combined_clear = 0x040, // SMBCINT (read-only) 59 Int_rx_uf_clear = 0x044, // SMBCRXUF (read-only) 60 Int_rx_of_clear = 0x048, // SMBCRXOF (read-only) 61 Int_tx_of_clear = 0x04c, // SMBCTXOF (read-only) 62 Int_rd_req_clear = 0x050, // SMBCRXREQ (read-only) 63 Int_tx_abort_clear = 0x054, // SMBCTXABT (read-only) 64 Int_rx_done_clear = 0x058, // SMBCRXDN (read-only) 65 Int_activity_clear = 0x05c, // SMBCACT (read-only) 66 Int_stop_clear = 0x060, // SMBCSTP (read-only) 67 Int_start_clear = 0x064, // SMBCSTT (read-only) 68 Int_call_clear = 0x068, // SMBCGC (read-only) 69 Smb_enable = 0x06c, // SMBENB 70 Smb_status = 0x070, // SMBST (read-only) 71 72 Tx_fifo_count = 0x074, // SMBTXFLR (read-only) 73 Rx_fifo_count = 0x078, // SMBRXFLR (read-only) 74 75 Trans_abort_status0 = 0x080, // SMBABTSRC (read-only) 76 Trans_abort_status1 = 0x084, // ... (read-only) 77 78 Smb_dma_ctrl = 0x088, // SMBDMACR 79 Smb_trans_data_lvl = 0x08c, // SMBDMATDLR 80 Smb_recv_data_lvl = 0x090, // SMBDMARDLR 81 Smb_sda_setup_time = 0x094, // SMBSDASU 82 Smb_ack_call = 0x098, // SMBACKGC 83 84 Smb_enable_status = 0x09c, // SMBENBST (read-only) 85 Smb_sda_hold_time = 0x0d0, // SMBSDAHD 86 87 Smb_block_offset = 0x1000 88 }; 89 90 enum Smb_control_bits : unsigned 91 { 92 Smb_no_stop_empty = 0x80, // STPHLD (no STP condition when queue empty) 93 Smb_disable_slave = 0x40, // SLVDIS (slave disabled) 94 Smb_enable_restart = 0x20, // REST 95 Smb_enable_master = 0x01, // MD (master enabled) 96 Smb_speed_bit = 1, // SPD 97 }; 98 99 enum Smb_enable_bits : unsigned 100 { 101 Smb_enable_enabled = 0x01, // SMBEN 102 }; 103 104 enum Smb_status_bits : unsigned 105 { 106 Smb_status_master_act = 0x20, // MSTACT (master active) 107 Smb_status_rx_nempty = 0x08, // RFNE (read queue not empty) 108 Smb_status_tx_empty = 0x04, // TFE (write queue empty) 109 Smb_status_tx_nfull = 0x02, // TFNF (write queue not full) 110 Smb_status_active = 0x01, // ACT (device active as master or slave) 111 }; 112 113 enum Smb_target_bits : unsigned 114 { 115 Smb_target_7bits = 0x7f, 116 }; 117 118 enum Smb_hold_control_bits : unsigned 119 { 120 Smb_hold_enable = 0x100, // HDENB 121 Smb_hold_disable = 0x000, // HDENB 122 Smb_hold_mask = 0x1ff, 123 }; 124 125 enum Smb_setup_control_bits : unsigned 126 { 127 Smb_setup_mask = 0x0ff, 128 }; 129 130 enum Smb_command_bits : unsigned 131 { 132 Smb_command_read = 0x100, // CMD 133 Smb_command_write = 0x000, // CMD 134 }; 135 136 enum Smb_fifo_bits : unsigned 137 { 138 Smb_fifo_limit = 16, 139 }; 140 141 enum Int_bits : unsigned 142 { 143 Int_call = 0x800, // IGC (general call received) 144 Int_start = 0x400, // ISTT (start/restart condition occurred) 145 Int_stop = 0x200, // ISTP (stop condition occurred) 146 Int_activity = 0x100, // IACT (bus activity interrupt) 147 Int_rx_done = 0x080, // RXDN (read from master device done) 148 Int_tx_abort = 0x040, // TXABT (transmit abort) 149 Int_rd_req = 0x020, // RDREQ (read request from master device) 150 Int_tx_empty = 0x010, // TXEMP (threshold reached or passed) 151 Int_tx_of = 0x008, // TXOF (overflow when writing to queue) 152 Int_rx_full = 0x004, // RXFL (threshold reached or exceeded) 153 Int_rx_of = 0x002, // RXOF (overflow from device) 154 Int_rx_uf = 0x001, // RXUF (underflow when reading from queue) 155 }; 156 157 158 159 // Initialise a channel. 160 161 I2c_jz4780_channel::I2c_jz4780_channel(l4_addr_t start, 162 Cpm_jz4780_chip *cpm, 163 uint32_t frequency) 164 : _cpm(cpm), _frequency(frequency) 165 { 166 _regs = new Hw::Mmio_register_block<32>(start); 167 } 168 169 // Enable the channel. 170 171 void 172 I2c_jz4780_channel::enable() 173 { 174 _regs[Smb_control] = _regs[Smb_control] | Smb_no_stop_empty; 175 176 _regs[Smb_enable] = Smb_enable_enabled; 177 while (!(_regs[Smb_enable_status] & Smb_enable_enabled)); 178 } 179 180 // Disable the channel. 181 182 void 183 I2c_jz4780_channel::disable() 184 { 185 _regs[Smb_enable] = 0; 186 while (_regs[Smb_enable_status] & Smb_enable_enabled); 187 } 188 189 // Set the frequency-related peripheral parameters. 190 191 void 192 I2c_jz4780_channel::set_frequency() 193 { 194 // The APB clock (PCLK) is used to drive I2C transfers. Its value must be 195 // obtained from the CPM unit. It is known as SMB_CLK here and is scaled to 196 // kHz in order to keep the numbers easily representable, as is the bus 197 // frequency. 198 199 uint32_t smb_clk = _cpm->get_pclock_frequency() / 1000; 200 uint32_t i2c_clk = _frequency / 1000; 201 unsigned speed = (i2c_clk <= 100) ? 1 : 2; 202 203 _regs[Smb_control] = _regs[Smb_control] | (speed << Smb_speed_bit) | 204 Smb_disable_slave | 205 Smb_enable_restart | 206 Smb_enable_master; 207 208 // According to the programming manual, if the PCLK period is T{SMB_CLK} 209 // then the I2C clock period is... 210 211 // T{SCL} = T{SCL_high} + T{SCL_low} 212 213 // Where... 214 215 // T{SCL_low} = T{SMB_CLK} * (#cycles for low signal) 216 // T{SCL_high} = T{SMB_CLK} * (#cycles for high signal) 217 218 // Since, with minimum periods being defined... 219 220 // T{SCL} >= T{min_SCL} 221 // T{SCL_low} >= T{min_SCL_low} 222 // T{SCL_high} >= T{min_SCL_high} 223 // T{min_SCL} = T{min_SCL_low} + T{min_SCL_high} 224 225 // Then the following applies... 226 227 // T{SMB_CLK} * (#cycles for low signal)) >= T{min_SCL_low} 228 // T{SMB_CLK} * (#cycles for high signal) >= T{min_SCL_high} 229 230 // To work with different clock speeds while maintaining the low-to-high 231 // ratios: 232 233 // T{min_SCL_low} = T{min_SCL} * T{min_SCL_low} / T{min_SCL} 234 // = T{min_SCL} * (T{min_SCL_low} / (T{min_SCL_low} + T{min_SCL_high})) 235 236 // T{min_SCL_high} = T{min_SCL} * T{min_SCL_high} / T{min_SCL} 237 // = T{min_SCL} * (T{min_SCL_high} / (T{min_SCL_low} + T{min_SCL_high})) 238 239 // Constraints are given with respect to the high and low count registers. 240 241 // #cycles for high signal = SMBxHCNT + 8 242 // #cycles for low signal = SMBxLCNT + 1 243 244 // From earlier, this yields... 245 246 // T{SMB_CLK} * (SMBxLCNT + 1) >= T{min_SCL_low} 247 // T{SMB_CLK} * (SMBxHCNT + 8) >= T{min_SCL_high} 248 249 // Rearranging... 250 251 // SMBxLCNT >= (T{min_SCL_low} / T{SMB_CLK}) - 1 252 // >= T{min_SCL_low} * SMB_CLK - 1 253 254 // SMBxHCNT >= (T{min_SCL_high} / T{SMB_CLK}) - 8 255 // >= T{min_SCL_high} * SMB_CLK - 8 256 257 // Introducing the definitions for the high and low periods... 258 259 // SMBxLCNT >= T{min_SCL} * (T{min_SCL_low} / (T{min_SCL_low} + T{min_SCL_high})) * SMB_CLK - 1 260 // >= (T{min_SCL_low} / T{min_SCL}) * SMB_CLK / I2C_CLK - 1 261 262 // SMBxHCNT >= T{min_SCL} * (T{min_SCL_high} / (T{min_SCL_low} + T{min_SCL_high})) * SMB_CLK - 8 263 // >= (T{min_SCL_high} / T{min_SCL}) * SMB_CLK / I2C_CLK - 8 264 265 uint32_t high_reg, low_reg; 266 uint32_t high_count, low_count; 267 int32_t hold_count; 268 uint32_t setup_count; 269 270 // Level hold times: 271 272 // Standard Fast 273 // SCL low 4.7us 1.3us 274 // SCL high 4.0us 0.6us + 275 // SCL period 8.7us 1.9us = 276 277 if (i2c_clk <= 100) // 100 kHz 278 { 279 low_count = (smb_clk * 47) / (i2c_clk * 87) - 1; 280 high_count = (smb_clk * 40) / (i2c_clk * 87) - 8; 281 low_reg = Std_low_count; 282 high_reg = Std_high_count; 283 } 284 else 285 { 286 low_count = (smb_clk * 13) / (i2c_clk * 19) - 1; 287 high_count = (smb_clk * 6) / (i2c_clk * 19) - 8; 288 low_reg = Fast_low_count; 289 high_reg = Fast_high_count; 290 } 291 292 // Minimum counts are 8 and 6 for low and high respectively. 293 294 _regs[low_reg] = low_count < 8 ? 8 : low_count; 295 _regs[high_reg] = high_count < 6 ? 6 : high_count; 296 297 // Data hold and setup times: 298 299 // Standard Fast 300 // t{HD;DAT} 300ns 300ns 301 // t{SU;DAT} 250ns 100ns 302 303 // T{delay} = (SMBSDAHD + 1) * T{SMB_CLK} 304 // SMBSDAHD = T{delay} / T{SMB_CLK} - 1 305 // SMBSDAHD = SMB_CLK * T{delay} - 1 306 307 hold_count = (smb_clk * 300) / 1000000 - 1; 308 309 _regs[Smb_sda_hold_time] = (_regs[Smb_sda_hold_time] & ~Smb_hold_mask) | 310 (hold_count >= 0 ? Smb_hold_enable : Smb_hold_disable) | 311 (hold_count < 0 ? 0 : hold_count < 255 ? hold_count : 255); 312 313 // T{delay} = (SMBSDASU - 1) * T{SMB_CLK} 314 // SMBSDASU = T{delay} / T{SMB_CLK} + 1 315 // SMBSDASU = SMB_CLK * T{delay} + 1 316 317 if (i2c_clk <= 100) 318 setup_count = (smb_clk * 250) / 1000000 + 1; 319 else 320 setup_count = (smb_clk * 100) / 1000000 + 1; 321 322 _regs[Smb_sda_setup_time] = (_regs[Smb_sda_setup_time] & ~Smb_setup_mask) | 323 (setup_count < 255 ? setup_count : 255); 324 } 325 326 // Set the target address and enable transfer. 327 // NOTE: Only supporting 7-bit addresses currently. 328 329 void 330 I2c_jz4780_channel::set_target(uint8_t address) 331 { 332 disable(); 333 set_frequency(); 334 _regs[Smb_target_address] = address & Smb_target_7bits; 335 enable(); 336 init_parameters(); 337 queued = 0; 338 } 339 340 341 342 // Reset interrupt flags upon certain conditions. 343 344 void 345 I2c_jz4780_channel::reset_flags() 346 { 347 volatile uint32_t r; 348 349 _regs[Int_mask] = 0; 350 351 // Read from the register to clear interrupts. 352 353 r = _regs[Int_combined_clear]; 354 (void) r; 355 } 356 357 // Initialise interrupt flags and queue thresholds for reading and writing. 358 359 void 360 I2c_jz4780_channel::init_parameters() 361 { 362 // Handle read queue conditions for data, write queue conditions for commands. 363 364 reset_flags(); 365 366 _regs[Int_mask] = Int_rx_full | // read condition (reading needed) 367 Int_rx_of | // abort condition 368 Int_tx_empty | // write condition (writing needed) 369 Int_tx_abort; // abort condition 370 371 _regs[Tx_fifo_thold] = 0; // write when 0 in queue 372 373 // Make sure that the stop condition does not occur automatically. 374 375 _regs[Smb_control] = _regs[Smb_control] | Smb_no_stop_empty; 376 } 377 378 379 380 // Return whether the device is active. 381 382 int 383 I2c_jz4780_channel::active() 384 { 385 return _regs[Smb_status] & Smb_status_master_act; 386 } 387 388 // Return whether data is available to receive. 389 390 int 391 I2c_jz4780_channel::have_input() 392 { 393 return _regs[Smb_status] & Smb_status_rx_nempty; 394 } 395 396 // Return whether data is queued for sending. 397 398 int 399 I2c_jz4780_channel::have_output() 400 { 401 return !(_regs[Smb_status] & Smb_status_tx_empty); 402 } 403 404 // Return whether data can be queued for sending. 405 406 int 407 I2c_jz4780_channel::can_send() 408 { 409 return _regs[Smb_status] & Smb_status_tx_nfull; 410 } 411 412 // Return whether a receive operation has failed. 413 414 int 415 I2c_jz4780_channel::read_failed() 416 { 417 return _regs[Int_status] & Int_rx_of; 418 } 419 420 // Return whether a send operation has failed. 421 422 int 423 I2c_jz4780_channel::write_failed() 424 { 425 return _regs[Int_status] & Int_tx_abort; 426 } 427 428 429 430 // Send read commands for empty queue entries. 431 432 void 433 I2c_jz4780_channel::queue_reads() 434 { 435 unsigned remaining = _total - _reqpos; 436 unsigned can_queue = Smb_fifo_limit - queued + 1; 437 438 if (!remaining) 439 { 440 _regs[Smb_data_command] = Smb_command_read; 441 return; 442 } 443 444 // Keep the number of reads in progress below the length of the read queue. 445 446 if (!can_queue) 447 { 448 //printf("remaining=%d queued=%d\n", remaining, queued); 449 return; 450 } 451 452 if (remaining < can_queue) 453 can_queue = remaining; 454 455 // Queue read requests for any remaining queue entries. 456 457 for (unsigned i = 0; i < can_queue; i++) 458 _regs[Smb_data_command] = Smb_command_read; 459 460 // Track queued messages and requested positions. 461 462 queued += can_queue; 463 _reqpos += can_queue; 464 465 if (_total == _reqpos) 466 printf("Written %d read requests.\n", _reqpos); 467 } 468 469 // Send write commands for empty queue entries. 470 471 void 472 I2c_jz4780_channel::queue_writes(uint8_t buf[], unsigned *pos, unsigned total) 473 { 474 // Queue write requests for any remaining queue entries. 475 476 while ((*pos < total) && can_send() && !write_failed()) 477 { 478 _regs[Smb_data_command] = Smb_command_write | buf[*pos]; 479 (*pos)++; 480 } 481 } 482 483 // Store read command results from the queue. 484 485 void 486 I2c_jz4780_channel::store_reads() 487 { 488 int have_read = 0; 489 490 // Read any input and store it in the buffer. 491 492 while (have_input() && (_pos < _total)) 493 { 494 _buf[_pos] = _regs[Smb_data_command] & 0xff; 495 queued--; 496 _pos++; 497 498 have_read = 1; 499 } 500 501 // Update the threshold to be notified of any reduced remaining amount. 502 503 if (have_read) 504 set_read_threshold(); 505 506 //printf("Read to %d, still %d queued.\n", _pos, queued); 507 } 508 509 // Read from the target device. 510 511 void 512 I2c_jz4780_channel::start_read(uint8_t buf[], unsigned total) 513 { 514 printf("intst=%x\n", (uint32_t) _regs[Int_status]); 515 516 _buf = buf; 517 _total = total; 518 _pos = 0; 519 _reqpos = 0; 520 _fail = 0; 521 _stop = 0; 522 523 set_read_threshold(); 524 } 525 526 void 527 I2c_jz4780_channel::set_read_threshold() 528 { 529 unsigned remaining = _total - _pos; 530 531 if (!remaining) 532 return; 533 534 if (remaining <= Smb_fifo_limit) 535 _regs[Rx_fifo_thold] = remaining - 1; // read all remaining 536 else 537 _regs[Rx_fifo_thold] = Smb_fifo_limit - 1; // read to limit 538 539 //printf("rxthold=%d\n", (uint32_t) _regs[Rx_fifo_thold] + 1); 540 } 541 542 void 543 I2c_jz4780_channel::read() 544 { 545 if (read_failed() || write_failed()) 546 { 547 printf("intst*=%x\n", (uint32_t) _regs[Int_status]); 548 printf("rxfifo=%d\n", (uint32_t) _regs[Rx_fifo_count] & 0x3f); 549 printf("smbabtsrc=%x\n", (uint32_t) _regs[Trans_abort_status0]); 550 _fail = 1; 551 return; 552 } 553 554 //printf("rxfifo=%d\n", (uint32_t) _regs[Rx_fifo_count]); 555 //printf("intst=%x\n", (uint32_t) _regs[Int_status]); 556 557 if (_pos < _total) 558 { 559 if (_regs[Int_status] & Int_rx_full) 560 store_reads(); 561 if (_regs[Int_status] & Int_tx_empty) 562 queue_reads(); 563 } 564 else 565 { 566 stop(); 567 _regs[Int_mask] = 0; 568 } 569 } 570 571 int 572 I2c_jz4780_channel::read_done() 573 { 574 return _pos == _total; 575 } 576 577 unsigned 578 I2c_jz4780_channel::have_read() 579 { 580 return _pos; 581 } 582 583 int 584 I2c_jz4780_channel::read_incomplete() 585 { 586 return _fail; 587 } 588 589 // Write to the target device. 590 591 void 592 I2c_jz4780_channel::write(uint8_t buf[], unsigned total) 593 { 594 unsigned pos = 0; 595 596 while ((pos < total) && !write_failed()) 597 { 598 queue_writes(buf, &pos, total); 599 } 600 } 601 602 // Explicitly stop communication. 603 604 void 605 I2c_jz4780_channel::stop() 606 { 607 if (_stop) 608 return; 609 610 _regs[Smb_control] = _regs[Smb_control] & ~Smb_no_stop_empty; 611 _stop = 1; 612 printf("Stop sent.\n"); 613 } 614 615 616 617 // Initialise the I2C controller. 618 619 I2c_jz4780_chip::I2c_jz4780_chip(l4_addr_t start, l4_addr_t end, 620 Cpm_jz4780_chip *cpm, 621 uint32_t frequency) 622 : _start(start), _end(end), _cpm(cpm), _frequency(frequency) 623 { 624 } 625 626 // Obtain a channel object. 627 628 I2c_jz4780_channel * 629 I2c_jz4780_chip::get_channel(uint8_t channel) 630 { 631 l4_addr_t block = _start + channel * Smb_block_offset; 632 633 if (block < _end) 634 { 635 _cpm->start_i2c(channel); 636 return new I2c_jz4780_channel(block, _cpm, _frequency); 637 } 638 else 639 throw -L4_EINVAL; 640 } 641 642 643 644 // C language interface functions. 645 646 void *jz4780_i2c_init(l4_addr_t start, l4_addr_t end, void *cpm, uint32_t frequency) 647 { 648 return (void *) new I2c_jz4780_chip(start, end, static_cast<Cpm_jz4780_chip *>(cpm), frequency); 649 } 650 651 void *jz4780_i2c_get_channel(void *i2c, uint8_t channel) 652 { 653 return static_cast<I2c_jz4780_chip *>(i2c)->get_channel(channel); 654 } 655 656 void jz4780_i2c_set_target(void *i2c_channel, uint8_t addr) 657 { 658 static_cast<I2c_jz4780_channel *>(i2c_channel)->set_target(addr); 659 } 660 661 void jz4780_i2c_start_read(void *i2c_channel, uint8_t buf[], unsigned total) 662 { 663 static_cast<I2c_jz4780_channel *>(i2c_channel)->start_read(buf, total); 664 } 665 666 void jz4780_i2c_read(void *i2c_channel) 667 { 668 static_cast<I2c_jz4780_channel *>(i2c_channel)->read(); 669 } 670 671 int jz4780_i2c_read_done(void *i2c_channel) 672 { 673 return static_cast<I2c_jz4780_channel *>(i2c_channel)->read_done(); 674 } 675 676 unsigned jz4780_i2c_have_read(void *i2c_channel) 677 { 678 return static_cast<I2c_jz4780_channel *>(i2c_channel)->have_read(); 679 } 680 681 int jz4780_i2c_read_incomplete(void *i2c_channel) 682 { 683 return static_cast<I2c_jz4780_channel *>(i2c_channel)->read_incomplete(); 684 } 685 686 void jz4780_i2c_write(void *i2c_channel, uint8_t buf[], unsigned total) 687 { 688 static_cast<I2c_jz4780_channel *>(i2c_channel)->write(buf, total); 689 } 690 691 void jz4780_i2c_stop(void *i2c_channel) 692 { 693 static_cast<I2c_jz4780_channel *>(i2c_channel)->stop(); 694 }