1 /* 2 * Copyright (C) 2017, 2018, 2020 Paul Boddie <paul@boddie.org.uk> 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 17 * Boston, MA 02110-1301, USA 18 */ 19 20 #pragma once 21 22 #include "cpm.h" 23 24 #include <l4/sys/types.h> 25 #include <stdint.h> 26 27 28 29 #ifdef __cplusplus 30 31 #include <l4/devices/hw_register_block.h> 32 33 /* A simple abstraction for accessing the CPM registers. 34 * A proper device could inherit from Hw::Device and use an 35 * Int_property for _exclk_freq and _rtclk_freq. */ 36 37 class Cpm_jz4780_chip : public Cpm_chip 38 { 39 private: 40 Hw::Register_block<32> _regs; 41 uint32_t _exclk_freq, _rtclk_freq; 42 43 // Utility methods. 44 45 uint32_t get_field(uint32_t reg, uint32_t mask, uint8_t shift); 46 void set_field(uint32_t reg, uint32_t mask, uint8_t shift, uint32_t value); 47 uint8_t _get_divider(uint32_t reg, uint32_t mask, uint8_t shift); 48 49 // PLL control. 50 51 int have_pll(uint32_t pll_reg); 52 int pll_enabled(uint32_t pll_reg); 53 int pll_bypassed(uint32_t pll_reg); 54 55 // General frequency modifiers. 56 57 uint16_t get_multiplier(uint32_t pll_reg); 58 void set_multiplier(uint32_t pll_reg, uint16_t multiplier); 59 uint8_t get_input_division(uint32_t pll_reg); 60 void set_input_division(uint32_t pll_reg, uint8_t divider); 61 uint8_t get_output_division(uint32_t pll_reg); 62 void set_output_division(uint32_t pll_reg, uint8_t divider); 63 64 // Clock dividers. 65 66 void set_hdmi_divider(uint16_t division); 67 void set_lcd_pixel_divider(uint16_t division); 68 69 // Clock control. 70 71 void _update_i2c(uint8_t channel, int enable); 72 73 // Input frequencies. 74 75 uint32_t get_pll_frequency(uint32_t pll_reg); 76 77 // Clock sources. 78 79 void set_hclock2_source(uint8_t source); 80 void set_hdmi_source(uint8_t source); 81 void set_lcd_source(uint8_t source); 82 83 public: 84 void set_pclock_source(uint8_t source); 85 Cpm_jz4780_chip(l4_addr_t addr, uint32_t exclk_freq, uint32_t rtclk_freq); 86 87 int have_clock(); 88 void start_clock(); 89 90 // Clock divider values. 91 92 uint8_t get_cpu_divider(); 93 uint8_t get_hclock0_divider(); 94 uint8_t get_hclock2_divider(); 95 uint8_t get_pclock_divider(); 96 uint8_t get_hdmi_divider(); 97 uint8_t get_lcd_pixel_divider(); 98 uint8_t get_memory_divider(); 99 100 // Clock control. 101 102 void start_hdmi(); 103 void stop_hdmi(); 104 105 void start_lcd(); 106 void stop_lcd(); 107 108 void start_i2c(uint8_t channel); 109 void stop_i2c(uint8_t channel); 110 111 // Input frequencies. 112 113 uint8_t get_main_source(); 114 uint32_t get_main_frequency(); 115 116 // Clock sources, providing the input frequency. 117 118 uint8_t get_cpu_source(); 119 uint8_t get_hclock0_source(); 120 uint8_t get_hclock2_source(); 121 uint8_t get_hdmi_source(); 122 uint8_t get_lcd_source(); 123 uint8_t get_memory_source(); 124 uint8_t get_pclock_source(); 125 126 uint32_t get_cpu_source_frequency(); 127 uint32_t get_hclock0_source_frequency(); 128 uint32_t get_hclock2_source_frequency(); 129 uint32_t get_hdmi_source_frequency(); 130 uint32_t get_lcd_source_frequency(); 131 uint32_t get_memory_source_frequency(); 132 uint32_t get_pclock_source_frequency(); 133 134 // Final, calculated frequencies. 135 136 uint32_t get_cpu_frequency(); 137 uint32_t get_hclock0_frequency(); 138 uint32_t get_hclock2_frequency(); 139 uint32_t get_hdmi_frequency(); 140 uint32_t get_lcd_pixel_frequency(); 141 uint32_t get_memory_frequency(); 142 uint32_t get_pclock_frequency(); 143 144 uint32_t get_apll_frequency(); 145 uint32_t get_epll_frequency(); 146 uint32_t get_mpll_frequency(); 147 uint32_t get_vpll_frequency(); 148 149 void set_hdmi_frequency(uint32_t pclk); 150 void set_lcd_pixel_frequency(uint32_t pclk); 151 void set_lcd_frequencies(uint32_t pclk, uint8_t multiplier); 152 void set_pll_parameters(uint32_t pll_reg, uint16_t multiplier, uint8_t in_divider, uint8_t out_divider); 153 154 void update_output_frequency(); 155 }; 156 157 #endif /* __cplusplus */ 158 159 160 161 /* C language interface. */ 162 163 EXTERN_C_BEGIN 164 165 void *jz4780_cpm_init(l4_addr_t cpm_base); 166 167 int jz4780_cpm_have_clock(void *cpm); 168 void jz4780_cpm_start_clock(void *cpm); 169 170 void jz4780_cpm_start_hdmi(void *cpm); 171 void jz4780_cpm_stop_hdmi(void *cpm); 172 173 void jz4780_cpm_start_lcd(void *cpm); 174 void jz4780_cpm_stop_lcd(void *cpm); 175 176 uint8_t jz4780_cpm_get_cpu_divider(void *cpm); 177 uint8_t jz4780_cpm_get_hclock0_divider(void *cpm); 178 uint8_t jz4780_cpm_get_hclock2_divider(void *cpm); 179 uint8_t jz4780_cpm_get_hdmi_divider(void *cpm); 180 uint8_t jz4780_cpm_get_lcd_pixel_divider(void *cpm); 181 uint8_t jz4780_cpm_get_memory_divider(void *cpm); 182 uint8_t jz4780_cpm_get_pclock_divider(void *cpm); 183 184 uint8_t jz4780_cpm_get_hclock0_source(void *cpm); 185 uint8_t jz4780_cpm_get_hclock2_source(void *cpm); 186 uint8_t jz4780_cpm_get_hdmi_source(void *cpm); 187 uint8_t jz4780_cpm_get_lcd_source(void *cpm); 188 uint8_t jz4780_cpm_get_memory_source(void *cpm); 189 uint8_t jz4780_cpm_get_pclock_source(void *cpm); 190 191 uint32_t jz4780_cpm_get_hclock0_source_frequency(void *cpm); 192 uint32_t jz4780_cpm_get_hclock2_source_frequency(void *cpm); 193 uint32_t jz4780_cpm_get_hdmi_source_frequency(void *cpm); 194 uint32_t jz4780_cpm_get_lcd_source_frequency(void *cpm); 195 uint32_t jz4780_cpm_get_memory_source_frequency(void *cpm); 196 uint32_t jz4780_cpm_get_pclock_source_frequency(void *cpm); 197 198 void jz4780_cpm_set_pclock_source(void *cpm, uint8_t source); 199 200 uint8_t jz4780_cpm_get_main_source(void *cpm); 201 uint32_t jz4780_cpm_get_main_frequency(void *cpm); 202 203 uint32_t jz4780_cpm_get_cpu_frequency(void *cpm); 204 uint32_t jz4780_cpm_get_hclock0_frequency(void *cpm); 205 uint32_t jz4780_cpm_get_hclock2_frequency(void *cpm); 206 uint32_t jz4780_cpm_get_hdmi_frequency(void *cpm); 207 uint32_t jz4780_cpm_get_lcd_pixel_frequency(void *cpm); 208 uint32_t jz4780_cpm_get_memory_frequency(void *cpm); 209 uint32_t jz4780_cpm_get_pclock_frequency(void *cpm); 210 211 uint32_t jz4780_cpm_get_apll_frequency(void *cpm); 212 uint32_t jz4780_cpm_get_epll_frequency(void *cpm); 213 uint32_t jz4780_cpm_get_mpll_frequency(void *cpm); 214 uint32_t jz4780_cpm_get_vpll_frequency(void *cpm); 215 216 void jz4780_cpm_set_hdmi_frequency(void *cpm, uint32_t pclk); 217 void jz4780_cpm_set_lcd_pixel_frequency(void *cpm, uint32_t pclk); 218 void jz4780_cpm_set_lcd_frequencies(void *cpm, uint32_t pclk, uint8_t ratio); 219 void jz4780_cpm_set_mpll_parameters(void *cpm, uint16_t multiplier, uint8_t in_divider, uint8_t out_divider); 220 221 EXTERN_C_END