1 /* 2 * Clock and power management. This exposes the combined functionality 3 * provided by the X1600 and related SoCs. The power management 4 * functionality could be exposed using a separate driver. 5 * 6 * Copyright (C) 2017, 2018, 2020, 2021, 2023 Paul Boddie <paul@boddie.org.uk> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 21 * Boston, MA 02110-1301, USA 22 */ 23 24 #include <l4/devices/hw_mmio_register_block.h> 25 #include "cpm-x1600.h" 26 #include <math.h> 27 #include <stdio.h> 28 29 30 31 // Register locations. 32 33 enum Regs : unsigned 34 { 35 Clock_control = 0x000, // CPCCR 36 Low_power_control = 0x004, // LCR 37 Clock_gate0 = 0x020, // CLKGR0 38 Clock_gate1 = 0x028, // CLKGR1 39 Sleep_control = 0x024, // OPCR (oscillator and power control) 40 Clock_status = 0x0d4, // CPCSR 41 Divider_ddr = 0x02c, // DDRCDR 42 Divider_mac = 0x054, // MACCDR 43 Divider0_i2s0 = 0x060, // I2S0CDR 44 Divider1_i2s0 = 0x070, // I2S0CDR1 45 Divider0_i2s1 = 0x07c, // I2S1CDR (from X2000 manual) 46 Divider1_i2s1 = 0x080, // I2S1CDR1 (from X2000 manual) 47 Divider_lcd = 0x064, // LPCDR 48 Divider_msc0 = 0x068, // MSC0CDR 49 Divider_msc1 = 0x0a4, // MSC1CDR 50 Divider_sfc = 0x074, // SFCCDR 51 Divider_ssi = 0x05c, // SSICDR 52 Divider_cim = 0x078, // CIMCDR 53 Divider_pwm = 0x06c, // PWMCDR 54 Divider_can0 = 0x0a0, // CAN0CDR 55 Divider_can1 = 0x0a8, // CAN1CDR 56 Divider_cdbus = 0x0ac, // CDBUSCDR 57 Divider_macphy0 = 0x0e4, // MPHY0C 58 Cpm_interrupt = 0x0b0, // CPM_INTR 59 Cpm_interrupt_en = 0x0b4, // CPM_INTRE 60 Cpm_swi = 0x0bc, // CPM_SFTINT 61 Ddr_gate = 0x0d0, // DRCG 62 Cpm_scratch_prot = 0x038, // CPSPPR 63 Cpm_scratch = 0x034, // CPSPR 64 Usb_param_control0 = 0x03c, // USBPCR 65 Usb_reset_detect = 0x040, // USBRDT 66 Usb_vbus_jitter = 0x044, // USBVBFIL 67 Usb_param_control1 = 0x048, // USBPCR1 68 Pll_control = 0x00c, // CPPCR 69 Pll_control_A = 0x010, // CPAPCR 70 Pll_control_M = 0x014, // CPMPCR 71 Pll_control_E = 0x018, // CPEPCR 72 Pll_fraction_A = 0x084, // CPAPACR 73 Pll_fraction_M = 0x088, // CPMPACR 74 Pll_fraction_E = 0x08c, // CPEPACR 75 }; 76 77 enum Clock_source_values : unsigned 78 { 79 Source_mME_main = 0, 80 Source_mME_pll_M = 1, 81 Source_mME_pll_E = 2, 82 83 // Special value 84 85 Source_mask = 0x3, 86 }; 87 88 89 90 // Register field definitions. 91 92 static Field Clock_source_main (Clock_control, 3, 30), // SEL_SRC (output to SCLK_A) 93 Clock_source_cpu (Clock_control, 3, 28), // SEL_CPLL (output to CCLK) 94 Clock_source_hclock0 (Clock_control, 3, 26), // SEL_H0PLL (output to AHB0) 95 Clock_source_hclock2 (Clock_control, 3, 24), // SEL_H2PLL (output to AHB2) 96 Clock_source_can0 (Divider_can0, 3, 30), // CA0CS 97 Clock_source_can1 (Divider_can1, 3, 30), // CA1CS 98 Clock_source_cdbus (Divider_cdbus, 3, 30), // CDCS 99 Clock_source_cim (Divider_cim, 3, 30), // CIMPCS 100 Clock_source_ddr (Divider_ddr, 3, 30), // DCS 101 Clock_source_i2s (Divider0_i2s0, 1, 31), // I2PCS 102 Clock_source_lcd (Divider_lcd, 3, 30), // LPCS 103 Clock_source_mac (Divider_mac, 3, 30), // MACPCS 104 Clock_source_msc0 (Divider_msc0, 3, 30), // MPCS 105 Clock_source_msc1 (Divider_msc1, 3, 30), // MPCS 106 Clock_source_pwm (Divider_pwm, 3, 30), // PWMPCS 107 Clock_source_sfc (Divider_sfc, 3, 30), // SFCS 108 Clock_source_ssi (Divider_ssi, 3, 30), // SPCS 109 110 Clock_busy_cpu (Clock_status, 1, 0), 111 Clock_busy_ddr (Divider_ddr, 1, 28), 112 Clock_busy_mac (Divider_mac, 1, 28), 113 Clock_busy_lcd (Divider_lcd, 1, 28), 114 Clock_busy_msc0 (Divider_msc0, 1, 28), 115 Clock_busy_msc1 (Divider_msc1, 1, 28), 116 Clock_busy_sfc (Divider_sfc, 1, 28), 117 Clock_busy_ssi (Divider_ssi, 1, 28), 118 Clock_busy_cim (Divider_cim, 1, 28), 119 Clock_busy_pwm (Divider_pwm, 1, 28), 120 Clock_busy_can0 (Divider_can0, 1, 28), 121 Clock_busy_can1 (Divider_can1, 1, 28), 122 Clock_busy_cdbus (Divider_cdbus, 1, 28), 123 124 Clock_change_enable_cpu (Clock_control, 1, 22), 125 Clock_change_enable_ahb0 (Clock_control, 1, 21), 126 Clock_change_enable_ahb2 (Clock_control, 1, 20), 127 Clock_change_enable_ddr (Divider_ddr, 1, 29), 128 Clock_change_enable_mac (Divider_mac, 1, 29), 129 Clock_change_enable_i2s (Divider0_i2s0, 1, 29), 130 Clock_change_enable_lcd (Divider_lcd, 1, 29), 131 Clock_change_enable_msc0 (Divider_msc0, 1, 29), 132 Clock_change_enable_msc1 (Divider_msc1, 1, 29), 133 Clock_change_enable_sfc (Divider_sfc, 1, 29), 134 Clock_change_enable_ssi (Divider_ssi, 1, 29), 135 Clock_change_enable_cim (Divider_cim, 1, 29), 136 Clock_change_enable_pwm (Divider_pwm, 1, 29), 137 Clock_change_enable_can0 (Divider_can0, 1, 29), 138 Clock_change_enable_can1 (Divider_can1, 1, 29), 139 Clock_change_enable_cdbus (Divider_cdbus, 1, 29), 140 141 Clock_divider_can0 (Divider_can0, 0xff, 0), // CAN0CDR 142 Clock_divider_can1 (Divider_can1, 0xff, 0), // CAN1CDR 143 Clock_divider_cdbus (Divider_cdbus, 0xff, 0), // CDBUSCDR 144 Clock_divider_cim (Divider_cim, 0xff, 0), // CIMCDR 145 Clock_divider_cpu (Clock_control, 0x0f, 0), // CDIV 146 Clock_divider_ddr (Divider_ddr, 0x0f, 0), // DDRCDR 147 Clock_divider_hclock0 (Clock_control, 0x0f, 8), // H0DIV (fast AHB peripherals) 148 Clock_divider_hclock2 (Clock_control, 0x0f, 12), // H2DIV (fast AHB peripherals) 149 Clock_divider_i2s0_m (Divider0_i2s0, 0x1ff, 20), // I2SDIV_M 150 Clock_divider_i2s0_n (Divider0_i2s0, 0xfffff, 0), // I2SDIV_N 151 Clock_divider_i2s0_d (Divider1_i2s0, 0xfffff, 0), // I2SDIV_D 152 Clock_divider_i2s1_m (Divider0_i2s1, 0x1ff, 20), // I2SDIV_M 153 Clock_divider_i2s1_n (Divider0_i2s1, 0xfffff, 0), // I2SDIV_N 154 Clock_divider_i2s1_d (Divider1_i2s1, 0xfffff, 0), // I2SDIV_D 155 Clock_divider_l2cache (Clock_control, 0x0f, 4), // L2CDIV 156 Clock_divider_lcd (Divider_lcd, 0xff, 0), // LPCDR 157 Clock_divider_mac (Divider_mac, 0xff, 0), // MACCDR 158 Clock_divider_msc0 (Divider_msc0, 0xff, 0), // MSC0CDR 159 Clock_divider_msc1 (Divider_msc1, 0xff, 0), // MSC1CDR 160 Clock_divider_pclock (Clock_control, 0x0f, 16), // PDIV (slow APB peripherals) 161 Clock_divider_pwm (Divider_pwm, 0x0f, 0), // PWMCDR 162 Clock_divider_sfc (Divider_sfc, 0xff, 0), // SFCCDR 163 Clock_divider_ssi (Divider_ssi, 0xff, 0), // SSICDR 164 165 Clock_gate_main (Clock_control, 1, 23), // GATE_SCLKA 166 Clock_gate_ddr (Clock_gate0, 1, 31), // DDR 167 Clock_gate_ahb0 (Clock_gate0, 1, 29), // AHB0 168 Clock_gate_apb0 (Clock_gate0, 1, 28), // APB0 169 Clock_gate_rtc (Clock_gate0, 1, 27), // RTC 170 Clock_gate_aes (Clock_gate0, 1, 24), // AES 171 Clock_gate_lcd_pixel (Clock_gate0, 1, 23), // LCD 172 Clock_gate_cim (Clock_gate0, 1, 22), // CIM 173 Clock_gate_dma (Clock_gate0, 1, 21), // PDMA 174 Clock_gate_ost (Clock_gate0, 1, 20), // OST 175 Clock_gate_ssi0 (Clock_gate0, 1, 19), // SSI0 176 Clock_gate_timer (Clock_gate0, 1, 18), // TCU 177 Clock_gate_dtrng (Clock_gate0, 1, 17), // DTRNG 178 Clock_gate_uart2 (Clock_gate0, 1, 16), // UART2 179 Clock_gate_uart1 (Clock_gate0, 1, 15), // UART1 180 Clock_gate_uart0 (Clock_gate0, 1, 14), // UART0 181 Clock_gate_sadc (Clock_gate0, 1, 13), // SADC 182 Clock_gate_audio (Clock_gate0, 1, 11), // AUDIO 183 Clock_gate_ssi_slv (Clock_gate0, 1, 10), // SSI_SLV 184 Clock_gate_i2c1 (Clock_gate0, 1, 8), // I2C1 185 Clock_gate_i2c0 (Clock_gate0, 1, 7), // I2C0 186 Clock_gate_msc1 (Clock_gate0, 1, 5), // MSC1 187 Clock_gate_msc0 (Clock_gate0, 1, 4), // MSC0 188 Clock_gate_otg (Clock_gate0, 1, 3), // OTG 189 Clock_gate_sfc (Clock_gate0, 1, 2), // SFC 190 Clock_gate_efuse (Clock_gate0, 1, 1), // EFUSE 191 Clock_gate_nemc (Clock_gate0, 1, 0), // NEMC 192 Clock_gate_arb (Clock_gate1, 1, 30), // ARB 193 Clock_gate_mipi_csi (Clock_gate1, 1, 28), // MIPI_CSI 194 Clock_gate_intc (Clock_gate1, 1, 26), // INTC 195 Clock_gate_gmac0 (Clock_gate1, 1, 23), // GMAC0 196 Clock_gate_uart3 (Clock_gate1, 1, 16), // UART3 197 Clock_gate_i2s0_tx (Clock_gate1, 1, 9), // I2S0_dev_tclk 198 Clock_gate_i2s0_rx (Clock_gate1, 1, 8), // I2S0_dev_rclk 199 Clock_gate_hash (Clock_gate1, 1, 6), // HASH 200 Clock_gate_pwm (Clock_gate1, 1, 5), // PWM 201 Clock_gate_cdbus (Clock_gate1, 1, 2), // CDBUS 202 Clock_gate_can1 (Clock_gate1, 1, 1), // CAN1 203 Clock_gate_can0 (Clock_gate1, 1, 0), // CAN0 204 205 Pll_enable_A (Pll_control_A, 1, 0), // APLLEN 206 Pll_enable_E (Pll_control_E, 1, 0), // EPLLEN 207 Pll_enable_M (Pll_control_M, 1, 0), // MPLLEN 208 209 Pll_stable_A (Pll_control_A, 1, 3), // APLL_ON 210 Pll_stable_E (Pll_control_E, 1, 3), // EPLL_ON 211 Pll_stable_M (Pll_control_M, 1, 3), // MPLL_ON 212 213 Pll_bypass_A (Pll_control_A, 1, 30), // APLL_BP 214 Pll_bypass_E (Pll_control_E, 1, 26), // EPLL_BP 215 Pll_bypass_M (Pll_control_M, 1, 28), // MPLL_BP 216 217 Pll_multiplier_A (Pll_control_A, 0x1fff, 20), // APLLM 218 Pll_multiplier_E (Pll_control_E, 0x1fff, 20), // EPLLM 219 Pll_multiplier_M (Pll_control_M, 0x1fff, 20), // MPLLM 220 221 Pll_input_division_A (Pll_control_A, 0x3f, 14), // APLLN 222 Pll_input_division_E (Pll_control_E, 0x3f, 14), // EPLLN 223 Pll_input_division_M (Pll_control_M, 0x3f, 14), // MPLLN 224 225 Pll_output_division1_A (Pll_control_A, 0x07, 11), // APLLOD1 226 Pll_output_division1_E (Pll_control_E, 0x07, 11), // EPLLOD1 227 Pll_output_division1_M (Pll_control_M, 0x07, 11), // MPLLOD1 228 229 Pll_output_division0_A (Pll_control_A, 0x07, 8), // APLLOD0 230 Pll_output_division0_E (Pll_control_E, 0x07, 8), // EPLLOD0 231 Pll_output_division0_M (Pll_control_M, 0x07, 8); // MPLLOD0 232 233 234 235 // Multiplexer instances. 236 237 #define Clocks(...) ((enum Clock_identifiers []) {__VA_ARGS__}) 238 239 static Mux mux_external (Clock_external), 240 mux_pclock (Clock_pclock), 241 mux_ahb2_apb (Clock_ahb2_apb), 242 mux_core (3, Clocks(Clock_none, Clock_main, Clock_pll_M)), 243 mux_bus (4, Clocks(Clock_main, Clock_pll_M, Clock_pll_E, Clock_external)), 244 mux_dev (3, Clocks(Clock_main, Clock_pll_M, Clock_pll_E)), 245 mux_i2s (2, Clocks(Clock_main, Clock_pll_E)); 246 247 248 249 // Clock instances. 250 251 static Clock_passive clock_external; 252 253 static Clock_null clock_none; 254 255 static Clock clock_ahb2_apb(Source(mux_core, Clock_source_hclock2)), 256 257 clock_can0(Source(mux_bus, Clock_source_can0), 258 Control(Clock_gate_can0, Clock_change_enable_can0, Clock_busy_can0), 259 Divider(Clock_divider_can0)), 260 261 clock_can1(Source(mux_bus, Clock_source_can1), 262 Control(Clock_gate_can1, Clock_change_enable_can1, Clock_busy_can1), 263 Divider(Clock_divider_can1)), 264 265 clock_cdbus(Source(mux_dev, Clock_source_cdbus), 266 Control(Clock_gate_cdbus, Clock_change_enable_cdbus, Clock_busy_cdbus), 267 Divider(Clock_divider_cdbus)), 268 269 clock_cim(Source(mux_dev, Clock_source_cim), 270 Control(Clock_gate_cim, Clock_change_enable_cim, Clock_busy_cim), 271 Divider(Clock_divider_cim)), 272 273 clock_cpu(Source(mux_core, Clock_source_cpu), 274 Control(Field::undefined, Clock_change_enable_cpu, Clock_busy_cpu), 275 Divider(Clock_divider_cpu)), 276 277 clock_ddr(Source(mux_core, Clock_source_ddr), 278 Control(Clock_gate_ddr, Clock_change_enable_ddr, Clock_busy_ddr), 279 Divider(Clock_divider_ddr)), 280 281 clock_dma(Source(mux_pclock), Control(Clock_gate_dma), Divider::undefined), 282 283 clock_hclock0(Source(mux_core, Clock_source_hclock0), 284 Control(Clock_gate_ahb0, Clock_change_enable_ahb0), 285 Divider(Clock_divider_hclock0)), 286 287 clock_hclock2(Source(mux_ahb2_apb), 288 Control(Clock_gate_apb0, Clock_change_enable_ahb2), 289 Divider(Clock_divider_hclock2)), 290 291 clock_i2c(Source(mux_pclock), Control(Clock_gate_i2c0), Divider::undefined), 292 293 clock_i2c0(Source(mux_pclock), Control(Clock_gate_i2c0), Divider::undefined), 294 295 clock_i2c1(Source(mux_pclock), Control(Clock_gate_i2c1), Divider::undefined), 296 297 clock_lcd_pixel(Source(mux_dev, Clock_source_lcd), 298 Control(Clock_gate_lcd_pixel, Clock_change_enable_lcd, Clock_busy_lcd), 299 Divider(Clock_divider_lcd)), 300 301 clock_mac(Source(mux_dev, Clock_source_mac), 302 Control(Clock_gate_gmac0, Clock_change_enable_mac, Clock_busy_mac), 303 Divider(Clock_divider_mac)), 304 305 clock_main(Source(mux_core, Clock_source_main), 306 Control(Clock_gate_main)), 307 308 clock_msc(Source(mux_dev, Clock_source_msc0), 309 Control(Clock_gate_msc0, Clock_change_enable_msc0, Clock_busy_msc0), 310 Divider(Clock_divider_msc0)), 311 312 clock_msc0(Source(mux_dev, Clock_source_msc0), 313 Control(Clock_gate_msc0, Clock_change_enable_msc0, Clock_busy_msc0), 314 Divider(Clock_divider_msc0)), 315 316 clock_msc1(Source(mux_dev, Clock_source_msc1), 317 Control(Clock_gate_msc1, Clock_change_enable_msc1, Clock_busy_msc1), 318 Divider(Clock_divider_msc1)), 319 320 clock_pclock(Source(mux_ahb2_apb), 321 Control(Clock_gate_apb0, Field::undefined, Field::undefined), 322 Divider(Clock_divider_pclock)), 323 324 clock_pwm(Source(mux_dev, Clock_source_pwm), 325 Control(Clock_gate_pwm, Clock_change_enable_pwm, Clock_busy_pwm), 326 Divider(Clock_divider_pwm)), 327 328 clock_pwm0(Source(mux_dev, Clock_source_pwm), 329 Control(Clock_gate_pwm, Clock_change_enable_pwm, Clock_busy_pwm), 330 Divider(Clock_divider_pwm)), 331 332 clock_sfc(Source(mux_dev, Clock_source_sfc), 333 Control(Clock_gate_sfc, Clock_change_enable_sfc, Clock_busy_sfc), 334 Divider(Clock_divider_sfc)), 335 336 clock_ssi(Source(mux_dev, Clock_source_ssi), 337 Control(Clock_gate_ssi0, Clock_change_enable_ssi, Clock_busy_ssi), 338 Divider(Clock_divider_ssi)), 339 340 clock_timer(Source(mux_pclock), Control(Clock_gate_timer), Divider::undefined), 341 342 clock_uart0(Source(mux_external), Control(Clock_gate_uart0), Divider::undefined), 343 344 clock_uart1(Source(mux_external), Control(Clock_gate_uart1), Divider::undefined), 345 346 clock_uart2(Source(mux_external), Control(Clock_gate_uart2), Divider::undefined), 347 348 clock_uart3(Source(mux_external), Control(Clock_gate_uart3), Divider::undefined); 349 350 static Clock_divided_i2s clock_i2s0_rx(Source(mux_i2s, Clock_source_i2s), 351 Control(Clock_gate_i2s0_rx, Clock_change_enable_i2s), 352 Divider_i2s(Clock_divider_i2s0_m, Clock_divider_i2s0_n, 353 Clock_divider_i2s0_d)), 354 355 clock_i2s0_tx(Source(mux_i2s, Clock_source_i2s), 356 Control(Clock_gate_i2s0_tx, Clock_change_enable_i2s), 357 Divider_i2s(Clock_divider_i2s1_m, Clock_divider_i2s1_n, 358 Clock_divider_i2s1_d)); 359 360 static Pll clock_pll_A(Source(mux_external), 361 Control_pll(Pll_enable_A, Pll_stable_A, Pll_bypass_A), 362 Divider_pll(Pll_multiplier_A, Pll_input_division_A, 363 Pll_output_division0_A, Pll_output_division1_A)), 364 365 clock_pll_E(Source(mux_external), 366 Control_pll(Pll_enable_E, Pll_stable_E, Pll_bypass_E), 367 Divider_pll(Pll_multiplier_E, Pll_input_division_E, 368 Pll_output_division0_E, Pll_output_division1_E)), 369 370 clock_pll_M(Source(mux_external), 371 Control_pll(Pll_enable_M, Pll_stable_M, Pll_bypass_M), 372 Divider_pll(Pll_multiplier_M, Pll_input_division_M, 373 Pll_output_division0_M, Pll_output_division1_M)); 374 375 376 377 // Clock register. 378 379 static Clock_base *clocks[Clock_identifier_count] = { 380 &clock_ahb2_apb, 381 &clock_none, // Clock_aic_bitclk 382 &clock_none, // Clock_aic_pclk 383 &clock_can0, 384 &clock_can1, 385 &clock_cdbus, 386 &clock_cim, 387 &clock_cpu, 388 &clock_ddr, 389 &clock_dma, 390 &clock_none, // Clock_emac 391 &clock_external, 392 &clock_hclock0, 393 &clock_hclock2, 394 &clock_none, // Clock_hdmi 395 &clock_i2c, 396 &clock_i2c0, 397 &clock_i2c1, 398 &clock_none, // Clock_i2s 399 &clock_i2s0_rx, 400 &clock_i2s0_tx, 401 &clock_none, // Clock_kbc 402 &clock_none, // Clock_lcd 403 &clock_lcd_pixel, 404 &clock_mac, 405 &clock_main, 406 &clock_msc, 407 &clock_msc0, 408 &clock_msc1, 409 &clock_none, 410 &clock_pclock, 411 &clock_pll_A, 412 &clock_pll_E, 413 &clock_pll_M, 414 &clock_pwm, 415 &clock_pwm0, 416 &clock_none, // Clock_pwm1 417 &clock_none, // Clock_scc 418 &clock_sfc, 419 &clock_none, // Clock_smb0 420 &clock_none, // Clock_smb1 421 &clock_none, // Clock_smb2 422 &clock_none, // Clock_smb3 423 &clock_none, // Clock_smb4 424 &clock_ssi, 425 &clock_timer, 426 &clock_uart0, 427 &clock_uart1, 428 &clock_uart2, 429 &clock_uart3, 430 &clock_none, // Clock_udc 431 &clock_none, // Clock_uhc 432 &clock_none, // Clock_uprt 433 }; 434 435 436 437 // If implemented as a Hw::Device, various properties would be 438 // initialised in the constructor and obtained from the device tree 439 // definitions. 440 441 Cpm_x1600_chip::Cpm_x1600_chip(l4_addr_t addr, uint32_t exclk_freq) 442 : _cpm_regs(addr, clocks, exclk_freq) 443 { 444 // add_cid("cpm"); 445 // add_cid("cpm-x1600"); 446 // register_property("exclk_freq", &exclk_freq); 447 } 448 449 const char * 450 Cpm_x1600_chip::clock_type(enum Clock_identifiers clock) 451 { 452 return clocks[clock]->clock_type(); 453 } 454 455 int 456 Cpm_x1600_chip::have_clock(enum Clock_identifiers clock) 457 { 458 return clocks[clock]->have_clock(_cpm_regs); 459 } 460 461 void 462 Cpm_x1600_chip::start_clock(enum Clock_identifiers clock) 463 { 464 clocks[clock]->start_clock(_cpm_regs); 465 } 466 467 void 468 Cpm_x1600_chip::stop_clock(enum Clock_identifiers clock) 469 { 470 clocks[clock]->stop_clock(_cpm_regs); 471 } 472 473 uint32_t 474 Cpm_x1600_chip::get_divider(enum Clock_identifiers clock) 475 { 476 Clock *clk = dynamic_cast<Clock *>(clocks[clock]); 477 478 if (clk != NULL) 479 return clk->get_divider(_cpm_regs); 480 else 481 return 1; 482 } 483 484 void 485 Cpm_x1600_chip::set_divider(enum Clock_identifiers clock, uint32_t division) 486 { 487 Clock *clk = dynamic_cast<Clock *>(clocks[clock]); 488 489 if (clk != NULL) 490 clk->set_divider(_cpm_regs, division); 491 } 492 493 uint8_t 494 Cpm_x1600_chip::get_source(enum Clock_identifiers clock) 495 { 496 Clock_active *clk = dynamic_cast<Clock_active *>(clocks[clock]); 497 498 if (clk != NULL) 499 return clk->get_source(_cpm_regs); 500 else 501 return 0; 502 } 503 504 void 505 Cpm_x1600_chip::set_source(enum Clock_identifiers clock, uint8_t source) 506 { 507 Clock_active *clk = dynamic_cast<Clock_active *>(clocks[clock]); 508 509 if (clk != NULL) 510 clk->set_source(_cpm_regs, source); 511 } 512 513 uint32_t 514 Cpm_x1600_chip::get_source_frequency(enum Clock_identifiers clock) 515 { 516 Clock_active *clk = dynamic_cast<Clock_active *>(clocks[clock]); 517 518 if (clk != NULL) 519 return clk->get_source_frequency(_cpm_regs); 520 else 521 return 0; 522 } 523 524 uint32_t 525 Cpm_x1600_chip::get_frequency(enum Clock_identifiers clock) 526 { 527 return clocks[clock]->get_frequency(_cpm_regs); 528 } 529 530 void 531 Cpm_x1600_chip::set_frequency(enum Clock_identifiers clock, uint32_t frequency) 532 { 533 switch (clock) 534 { 535 // The pixel frequency is based on the selected clock source (SCLK_A, MPLL or 536 // EPLL). 537 538 case Clock_lcd_pixel: 539 { 540 541 // Switch to the MPLL and attempt to set the divider. 542 543 Clock *lcd = dynamic_cast<Clock *>(clocks[Clock_lcd_pixel]); 544 Clock_base *pll = clocks[Clock_pll_M]; 545 546 if (lcd != NULL) 547 { 548 lcd->set_source(_cpm_regs, Source_mME_pll_M); 549 pll->start_clock(_cpm_regs); 550 lcd->set_divider(_cpm_regs, lcd->get_source_frequency(_cpm_regs) / frequency); 551 } 552 break; 553 } 554 555 default: 556 break; 557 } 558 } 559 560 void 561 Cpm_x1600_chip::set_pll_parameters(enum Clock_identifiers clock, uint16_t multiplier, 562 uint8_t in_divider, uint8_t out_divider) 563 { 564 Pll *pll = dynamic_cast<Pll *>(clocks[clock]); 565 566 if (pll != NULL) 567 pll->set_parameters(_cpm_regs, multiplier, in_divider, out_divider); 568 } 569 570 571 572 // C language interface functions. 573 574 void 575 *x1600_cpm_init(l4_addr_t cpm_base) 576 { 577 /* Initialise the clock and power management peripheral with the 578 register memory region and a 24MHz EXCLK frequency. */ 579 580 return (void *) new Cpm_x1600_chip(cpm_base, 24000000); 581 } 582 583 const char * 584 x1600_cpm_clock_type(void *cpm, enum Clock_identifiers clock) 585 { 586 return static_cast<Cpm_x1600_chip *>(cpm)->clock_type(clock); 587 } 588 589 int 590 x1600_cpm_have_clock(void *cpm, enum Clock_identifiers clock) 591 { 592 return static_cast<Cpm_x1600_chip *>(cpm)->have_clock(clock); 593 } 594 595 void 596 x1600_cpm_start_clock(void *cpm, enum Clock_identifiers clock) 597 { 598 static_cast<Cpm_x1600_chip *>(cpm)->start_clock(clock); 599 } 600 601 void 602 x1600_cpm_stop_clock(void *cpm, enum Clock_identifiers clock) 603 { 604 static_cast<Cpm_x1600_chip *>(cpm)->stop_clock(clock); 605 } 606 607 uint32_t 608 x1600_cpm_get_divider(void *cpm, enum Clock_identifiers clock) 609 { 610 return static_cast<Cpm_x1600_chip *>(cpm)->get_divider(clock); 611 } 612 613 void 614 x1600_cpm_set_divider(void *cpm, enum Clock_identifiers clock, uint32_t divider) 615 { 616 return static_cast<Cpm_x1600_chip *>(cpm)->set_divider(clock, divider); 617 } 618 619 uint8_t 620 x1600_cpm_get_source(void *cpm, enum Clock_identifiers clock) 621 { 622 return static_cast<Cpm_x1600_chip *>(cpm)->get_source(clock); 623 } 624 625 void 626 x1600_cpm_set_source(void *cpm, enum Clock_identifiers clock, uint8_t source) 627 { 628 static_cast<Cpm_x1600_chip *>(cpm)->set_source(clock, source); 629 } 630 631 uint32_t 632 x1600_cpm_get_source_frequency(void *cpm, enum Clock_identifiers clock) 633 { 634 return static_cast<Cpm_x1600_chip *>(cpm)->get_source_frequency(clock); 635 } 636 637 uint32_t 638 x1600_cpm_get_frequency(void *cpm, enum Clock_identifiers clock) 639 { 640 return static_cast<Cpm_x1600_chip *>(cpm)->get_frequency(clock); 641 } 642 643 void 644 x1600_cpm_set_frequency(void *cpm, enum Clock_identifiers clock, uint32_t frequency) 645 { 646 static_cast<Cpm_x1600_chip *>(cpm)->set_frequency(clock, frequency); 647 } 648 649 void 650 x1600_cpm_set_mpll_parameters(void *cpm, uint16_t multiplier, uint8_t in_divider, uint8_t out_divider) 651 { 652 static_cast<Cpm_x1600_chip *>(cpm)->set_pll_parameters(Clock_pll_M, multiplier, in_divider, out_divider); 653 }