1 /* 2 * Clock and power management. This exposes the combined functionality 3 * provided by the jz4780 and related SoCs. The power management 4 * functionality could be exposed using a separate driver. 5 * 6 * Copyright (C) 2017, 2018 Paul Boddie <paul@boddie.org.uk> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 21 * Boston, MA 02110-1301, USA 22 */ 23 24 #include <l4/devices/hw_mmio_register_block.h> 25 #include "cpm-jz4780.h" 26 27 28 29 enum Regs : unsigned 30 { 31 Clock_control = 0x000, // CPCCR 32 Low_power_control = 0x004, // LCR 33 Pll_control = 0x00c, // CPPCR 34 Pll_control_A = 0x010, // CPAPCR 35 Pll_control_M = 0x014, // CPMPCR 36 Pll_control_E = 0x018, // CPEPCR 37 Pll_control_V = 0x01c, // CPVPCR 38 Clock_gate0 = 0x020, // CLKGR0 39 Clock_gate1 = 0x028, // CLKGR1 40 Sleep_control = 0x024, // OPCR (oscillator and power control) 41 Ddr_divider = 0x02c, // DDRCDR 42 I2s_divider0 = 0x060, // I2SCDR 43 I2s_divider1 = 0x0a0, // I2S1CDR 44 Lcd_divider0 = 0x054, // LP0CDR 45 Lcd_divider1 = 0x064, // LP1CDR 46 Msc_divider0 = 0x068, // MSC0CDR 47 Msc_divider1 = 0x0a4, // MSC1CDR 48 Msc_divider2 = 0x0a8, // MSC2CDR 49 Uhc_divider = 0x06c, // UHCCDR 50 Ssi_divider = 0x074, // SSICDR 51 }; 52 53 enum Clock_bits : unsigned 54 { 55 Clock_enable = 22, // CE_CPU 56 Clock_pclock_divider = 16, // PDIV (slow APB peripherals) 57 Clock_hclock2_divider = 12, // H2DIV (fast AHB peripherals) 58 Clock_hclock0_divider = 8, // H0DIV (fast AHB peripherals) 59 Clock_cpu_divider = 0, // CDIV 60 }; 61 62 enum Pll_bits : unsigned 63 { 64 Pll_multiplier = 19, // xPLLM 65 Pll_input_division = 13, // xPLLN 66 Pll_output_division = 9, // xPLLOD 67 Pll_stable = 4, // xPLL_ON 68 Pll_bypassed = 1, // xPLLBP 69 Pll_enabled = 0, // xPLLEN 70 }; 71 72 enum Clock_source_bits : unsigned 73 { 74 Clock_source_main = 30, // SEL_SRC (output to SCLK_A) 75 Clock_source_cpu = 28, // SEL_CPLL (output to CCLK) 76 Clock_source_hclock0 = 26, // SEL_H0PLL (output to AHB0) 77 Clock_source_hclock2 = 24, // SEL_H2PLL (output to AHB2) 78 Clock_source_ddr = 30, // DCS 79 Clock_source_i2s = 31, // I2CS 80 Clock_source_lcd = 30, // LPCS 81 }; 82 83 enum Clock_sources : unsigned 84 { 85 Source_pll_A = 1, // APLL 86 Source_external = 2, // EXCLK 87 Source_realtime = 3, // RTCLK 88 Source_main_frequency = 1, // SCLK_A 89 Source_pll_M = 2, // MPLL 90 Source_pll_E = 3, // EPLL 91 Source_pll_V = 3, // VPLL 92 }; 93 94 enum Clock_gate_bits : unsigned 95 { 96 Clock_gate_lcd = 28, // LCD (in CLKGR0) 97 Clock_gate_tve = 27, // TVE (in CLKGR0) 98 Clock_gate_smb4 = 12, // SMB4 (in CLKGR1) 99 Clock_gate_smb3 = 0, // SMB3 (in CLKGR1) 100 Clock_gate_smb2 = 25, // SMB2 (in CLKGR0) 101 Clock_gate_smb1 = 6, // SMB2 (in CLKGR0) 102 Clock_gate_smb0 = 5, // SMB2 (in CLKGR0) 103 }; 104 105 enum Clock_gate_regs : unsigned 106 { 107 Clock_gate_reg_smb4 = Clock_gate1, 108 Clock_gate_reg_smb3 = Clock_gate1, 109 Clock_gate_reg_smb2 = Clock_gate0, 110 Clock_gate_reg_smb1 = Clock_gate0, 111 Clock_gate_reg_smb0 = Clock_gate0, 112 }; 113 114 enum Divider_bits : unsigned 115 { 116 Ddr_divider_value = 0, // DDRCDR 117 Lcd_divider_value = 0, // LPCDR 118 }; 119 120 enum Lcd_clock_bits : unsigned 121 { 122 Lcd_change_enable = 0x1000, // CE_LCD 123 Lcd_change_busy = 0x0800, // LCD_BUSY 124 Lcd_clock_stop = 0x0400, // LCD_STOP 125 }; 126 127 128 129 // If implemented as a Hw::Device, various properties would be 130 // initialised in the constructor and obtained from the device tree 131 // definitions. 132 133 Cpm_jz4780_chip::Cpm_jz4780_chip(l4_addr_t addr, uint32_t exclk_freq, uint32_t rtclk_freq) 134 : _exclk_freq(exclk_freq), _rtclk_freq(rtclk_freq) 135 { 136 _regs = new Hw::Mmio_register_block<32>(addr); 137 138 // add_cid("cpm"); 139 // add_cid("cpm-jz4780"); 140 // register_property("exclk_freq", &_exclk_freq); 141 } 142 143 // Clock/timer control. 144 // NOTE: For the time being, assume that the system is configured. 145 146 int 147 Cpm_jz4780_chip::have_clock() 148 { 149 // return !(_regs[Clock_gate] & (1 << Clock_gate_timer)); 150 return 1; 151 } 152 153 void 154 Cpm_jz4780_chip::start_clock() 155 { 156 // _regs[Clock_gate] = _regs[Clock_gate] & ~(1 << Clock_gate_timer); 157 } 158 159 160 161 // Utility methods. 162 163 uint32_t 164 Cpm_jz4780_chip::get_field(uint32_t reg, uint32_t mask, uint8_t shift) 165 { 166 return (_regs[reg] & (mask << shift)) >> shift; 167 } 168 169 void 170 Cpm_jz4780_chip::set_field(uint32_t reg, uint32_t mask, uint8_t shift, uint32_t value) 171 { 172 _regs[reg] = (_regs[reg] & (~(mask << shift))) | ((mask & value) << shift); 173 } 174 175 // General clock divider access. 176 177 uint8_t 178 Cpm_jz4780_chip::_get_divider(uint32_t reg, uint32_t mask, uint8_t shift) 179 { 180 uint8_t d = get_field(reg, mask, shift); 181 182 // NOTE: Value 14 stops the clock, 15 presumably resumes the clock. 183 184 return (d < 14) ? d + 1 : 1; 185 } 186 187 188 189 // PLL control. 190 191 // Return whether the PLL is stable. 192 193 int 194 Cpm_jz4780_chip::have_pll(uint32_t pll_reg) 195 { 196 return _regs[pll_reg] & (1 << Pll_stable); 197 } 198 199 int 200 Cpm_jz4780_chip::pll_enabled(uint32_t pll_reg) 201 { 202 return _regs[pll_reg] & (1 << Pll_enabled); 203 } 204 205 int 206 Cpm_jz4780_chip::pll_bypassed(uint32_t pll_reg) 207 { 208 return _regs[pll_reg] & (1 << Pll_bypassed); 209 } 210 211 // Feedback (13-bit) multiplier. 212 213 uint16_t 214 Cpm_jz4780_chip::get_multiplier(uint32_t pll_reg) 215 { 216 return get_field(pll_reg, 0x1fff, Pll_multiplier) + 1; 217 } 218 219 void 220 Cpm_jz4780_chip::set_multiplier(uint32_t pll_reg, uint16_t multiplier) 221 { 222 set_field(pll_reg, 0x1fff, Pll_multiplier, multiplier - 1); 223 } 224 225 // Input (6-bit) divider. 226 227 uint8_t 228 Cpm_jz4780_chip::get_input_division(uint32_t pll_reg) 229 { 230 return get_field(pll_reg, 0x3f, Pll_input_division) + 1; 231 } 232 233 void 234 Cpm_jz4780_chip::set_input_division(uint32_t pll_reg, uint8_t divider) 235 { 236 set_field(pll_reg, 0x3f, Pll_input_division, divider - 1); 237 } 238 239 // Output divider. 240 241 uint8_t 242 Cpm_jz4780_chip::get_output_division(uint32_t pll_reg) 243 { 244 uint8_t d = get_field(pll_reg, 0x0f, Pll_output_division); 245 246 // Zero yields a division of one. Otherwise enforce even results. 247 248 return d == 0 ? 1 : (d + 1) & 0x0e; 249 } 250 251 void 252 Cpm_jz4780_chip::set_output_division(uint32_t pll_reg, uint8_t divider) 253 { 254 uint8_t d = divider <= 1 ? 0 : (divider & 0x0e) - 1; 255 256 set_field(pll_reg, 0x0f, Pll_output_division, d); 257 } 258 259 uint32_t 260 Cpm_jz4780_chip::get_pll_frequency(uint32_t pll_reg) 261 { 262 // Test for PLL enable and not PLL bypass. 263 264 if (pll_enabled(pll_reg) && !pll_bypassed(pll_reg)) 265 return (_exclk_freq * get_multiplier(pll_reg)) / 266 (get_input_division(pll_reg) * get_output_division(pll_reg)); 267 else 268 return _exclk_freq; 269 } 270 271 void 272 Cpm_jz4780_chip::set_pll_parameters(uint32_t pll_reg, uint16_t multiplier, uint8_t in_divider, uint8_t out_divider) 273 { 274 set_multiplier(pll_reg, multiplier); 275 set_input_division(pll_reg, in_divider); 276 set_output_division(pll_reg, out_divider); 277 278 if (pll_enabled(pll_reg) && !pll_bypassed(pll_reg)) 279 while (!have_pll(pll_reg)); 280 } 281 282 283 284 // CPU clock (CCLK) divider. 285 286 uint8_t 287 Cpm_jz4780_chip::get_cpu_divider() 288 { 289 return _get_divider(Clock_control, 0xf, Clock_cpu_divider); 290 } 291 292 // Fast peripheral clock (H0CLK) divider. 293 294 uint8_t 295 Cpm_jz4780_chip::get_hclock0_divider() 296 { 297 return _get_divider(Clock_control, 0xf, Clock_hclock0_divider); 298 } 299 300 // Fast peripheral clock (H2CLK) divider. 301 302 uint8_t 303 Cpm_jz4780_chip::get_hclock2_divider() 304 { 305 return _get_divider(Clock_control, 0xf, Clock_hclock2_divider); 306 } 307 308 // Slow peripheral clock (PCLK) divider. 309 310 uint8_t 311 Cpm_jz4780_chip::get_pclock_divider() 312 { 313 return _get_divider(Clock_control, 0xf, Clock_pclock_divider); 314 } 315 316 // LCD clock (LPCLK) divider for LCD0 pixel clock. 317 318 uint8_t 319 Cpm_jz4780_chip::get_lcd_pixel_divider() 320 { 321 return get_field(Lcd_divider0, 0xff, Lcd_divider_value) + 1; 322 } 323 324 // Memory clock (DDR_CLK) divider. 325 326 uint8_t 327 Cpm_jz4780_chip::get_memory_divider() 328 { 329 return _get_divider(Ddr_divider, 0xf, Ddr_divider_value); 330 } 331 332 // LCD pixel clock divider. 333 // NOTE: This only supports the first LCD peripheral. 334 335 void 336 Cpm_jz4780_chip::set_lcd_pixel_divider(uint16_t division) 337 { 338 if ((division < 1) || (division > 256)) 339 return; 340 341 // Enable change. 342 343 _regs[Lcd_divider0] = _regs[Lcd_divider0] | Lcd_change_enable; 344 345 // Set the divider. 346 347 set_field(Lcd_divider0, 0xff, Lcd_divider_value, division - 1); 348 349 // Restart clock and disable change. 350 351 while (_regs[Lcd_divider0] & Lcd_change_busy); 352 _regs[Lcd_divider0] = _regs[Lcd_divider0] & ~Lcd_change_enable; 353 } 354 355 356 357 // Clock gating control. 358 359 void 360 Cpm_jz4780_chip::start_lcd() 361 { 362 _regs[Clock_gate0] = _regs[Clock_gate0] & ~(1 << Clock_gate_lcd); 363 } 364 365 void 366 Cpm_jz4780_chip::stop_lcd() 367 { 368 _regs[Clock_gate0] = _regs[Clock_gate0] | (1 << Clock_gate_lcd); 369 } 370 371 void 372 Cpm_jz4780_chip::_update_i2c(uint8_t channel, int enable) 373 { 374 uint8_t bit; 375 uint32_t reg; 376 switch (channel) 377 { 378 case 0: bit = Clock_gate_smb0; reg = Clock_gate_reg_smb0; break; 379 case 1: bit = Clock_gate_smb1; reg = Clock_gate_reg_smb1; break; 380 case 2: bit = Clock_gate_smb2; reg = Clock_gate_reg_smb2; break; 381 case 3: bit = Clock_gate_smb3; reg = Clock_gate_reg_smb3; break; 382 case 4: bit = Clock_gate_smb4; reg = Clock_gate_reg_smb4; break; 383 default: return; 384 } 385 if (enable) 386 _regs[reg] = _regs[reg] & ~(1 << bit); 387 else 388 _regs[reg] = _regs[reg] | (1 << bit); 389 } 390 391 void 392 Cpm_jz4780_chip::start_i2c(uint8_t channel) 393 { 394 _update_i2c(channel, 1); 395 } 396 397 void 398 Cpm_jz4780_chip::stop_i2c(uint8_t channel) 399 { 400 _update_i2c(channel, 0); 401 } 402 403 404 405 // Clock sources. 406 407 uint8_t 408 Cpm_jz4780_chip::get_memory_source() 409 { 410 return get_field(Ddr_divider, 0x3, Clock_source_ddr); 411 } 412 413 uint32_t 414 Cpm_jz4780_chip::get_memory_source_frequency() 415 { 416 switch (get_memory_source()) 417 { 418 case Source_main_frequency: 419 return get_main_frequency(); 420 case Source_pll_M: 421 return get_pll_frequency(Pll_control_M); 422 default: 423 return 0; 424 } 425 } 426 427 uint8_t 428 Cpm_jz4780_chip::get_cpu_source() 429 { 430 return get_field(Clock_control, 0x3, Clock_source_cpu); 431 } 432 433 uint32_t 434 Cpm_jz4780_chip::get_cpu_source_frequency() 435 { 436 switch (get_cpu_source()) 437 { 438 case Source_main_frequency: 439 return get_main_frequency(); 440 case Source_pll_M: 441 return get_pll_frequency(Pll_control_M); 442 case Source_pll_E: 443 return get_pll_frequency(Pll_control_E); 444 default: 445 return 0; 446 } 447 } 448 449 uint8_t 450 Cpm_jz4780_chip::get_hclock0_source() 451 { 452 return get_field(Clock_control, 0x3, Clock_source_hclock0); 453 } 454 455 uint32_t 456 Cpm_jz4780_chip::get_hclock0_source_frequency() 457 { 458 switch (get_hclock0_source()) 459 { 460 case Source_main_frequency: 461 return get_main_frequency(); 462 case Source_pll_M: 463 return get_pll_frequency(Pll_control_M); 464 case Source_pll_E: 465 return get_pll_frequency(Pll_control_E); 466 default: 467 return 0; 468 } 469 } 470 471 uint8_t 472 Cpm_jz4780_chip::get_hclock2_source() 473 { 474 return get_field(Clock_control, 0x3, Clock_source_hclock2); 475 } 476 477 uint32_t 478 Cpm_jz4780_chip::get_hclock2_source_frequency() 479 { 480 switch (get_hclock2_source()) 481 { 482 case Source_main_frequency: 483 return get_main_frequency(); 484 case Source_pll_M: 485 return get_pll_frequency(Pll_control_M); 486 case Source_realtime: 487 return _rtclk_freq; // "TCK" in the manual, RTCLK in Linux driver code 488 default: 489 return 0; 490 } 491 } 492 493 void 494 Cpm_jz4780_chip::set_hclock2_source(uint8_t source) 495 { 496 set_field(Clock_control, 0x3, Clock_source_hclock2, source); 497 } 498 499 uint8_t 500 Cpm_jz4780_chip::get_lcd_source() 501 { 502 return get_field(Lcd_divider0, 0x3, Clock_source_lcd); 503 } 504 505 uint32_t 506 Cpm_jz4780_chip::get_lcd_source_frequency() 507 { 508 switch (get_lcd_source()) 509 { 510 case Source_main_frequency: 511 return get_main_frequency(); 512 case Source_pll_M: 513 return get_pll_frequency(Pll_control_M); 514 case Source_pll_V: 515 return get_pll_frequency(Pll_control_V); 516 default: 517 return 0; 518 } 519 } 520 521 void 522 Cpm_jz4780_chip::set_lcd_source(uint8_t source) 523 { 524 // Stop clock and enable change. 525 526 _regs[Lcd_divider0] = _regs[Lcd_divider0] | Lcd_change_enable | Lcd_clock_stop; 527 528 // Set the source. 529 530 set_field(Lcd_divider0, 0x03, Clock_source_lcd, source); 531 532 // Restart clock and disable change. 533 534 while (_regs[Lcd_divider0] & Lcd_change_busy); 535 _regs[Lcd_divider0] = _regs[Lcd_divider0] & ~(Lcd_change_enable | Lcd_clock_stop); 536 } 537 538 uint8_t 539 Cpm_jz4780_chip::get_pclock_source() 540 { 541 return get_hclock2_source(); 542 } 543 544 uint32_t 545 Cpm_jz4780_chip::get_pclock_source_frequency() 546 { 547 return get_hclock2_source_frequency(); 548 } 549 550 void 551 Cpm_jz4780_chip::set_pclock_source(uint8_t source) 552 { 553 set_hclock2_source(source); 554 } 555 556 557 558 // Source frequency, used by various clock sources. 559 560 uint8_t 561 Cpm_jz4780_chip::get_main_source() 562 { 563 return get_field(Clock_control, 0x3, Clock_source_main); 564 } 565 566 uint32_t 567 Cpm_jz4780_chip::get_main_frequency() 568 { 569 switch (get_main_source()) 570 { 571 case Source_pll_A: 572 return get_pll_frequency(Pll_control_A); 573 case Source_external: 574 return _exclk_freq; 575 case Source_realtime: 576 return _rtclk_freq; 577 default: 578 return 0; 579 } 580 } 581 582 // Clock frequency for the CPU. 583 584 uint32_t 585 Cpm_jz4780_chip::get_cpu_frequency() 586 { 587 return get_cpu_source_frequency() / get_cpu_divider(); 588 } 589 590 // Clock frequency for fast peripherals. 591 592 uint32_t 593 Cpm_jz4780_chip::get_hclock0_frequency() 594 { 595 return get_hclock0_source_frequency() / get_hclock0_divider(); 596 } 597 598 // Clock frequency for fast peripherals. 599 600 uint32_t 601 Cpm_jz4780_chip::get_hclock2_frequency() 602 { 603 return get_hclock2_source_frequency() / get_hclock2_divider(); 604 } 605 606 // Clock frequency for slow peripherals. 607 608 uint32_t 609 Cpm_jz4780_chip::get_pclock_frequency() 610 { 611 return get_pclock_source_frequency() / get_pclock_divider(); 612 } 613 614 // Clock frequency for the LCD0 controller. 615 616 uint32_t 617 Cpm_jz4780_chip::get_lcd_pixel_frequency() 618 { 619 return get_lcd_source_frequency() / get_lcd_pixel_divider(); 620 } 621 622 // Clock frequency for the memory. 623 624 uint32_t 625 Cpm_jz4780_chip::get_memory_frequency() 626 { 627 return get_memory_source_frequency() / get_memory_divider(); 628 } 629 630 uint32_t 631 Cpm_jz4780_chip::get_apll_frequency() 632 { 633 return get_pll_frequency(Pll_control_A); 634 } 635 636 uint32_t 637 Cpm_jz4780_chip::get_epll_frequency() 638 { 639 return get_pll_frequency(Pll_control_E); 640 } 641 642 uint32_t 643 Cpm_jz4780_chip::get_mpll_frequency() 644 { 645 return get_pll_frequency(Pll_control_M); 646 } 647 648 uint32_t 649 Cpm_jz4780_chip::get_vpll_frequency() 650 { 651 return get_pll_frequency(Pll_control_V); 652 } 653 654 655 656 // Set the pixel frequency. 657 // Unlike the jz4740, HCLK/AHB0 is used as the device frequency, with the pixel 658 // frequency being based on the selected clock source (SCLK_A, MPLL or VPLL). 659 660 void 661 Cpm_jz4780_chip::set_lcd_pixel_frequency(uint32_t pclk) 662 { 663 // Switch to the video PLL and attempt to set the divider. 664 665 set_lcd_source(Source_pll_V); 666 set_lcd_pixel_divider(get_lcd_source_frequency() / pclk); 667 } 668 669 // NOTE: Compatibility method. Probably needs reviewing. 670 671 void 672 Cpm_jz4780_chip::set_lcd_frequencies(uint32_t pclk, uint8_t ratio) 673 { 674 (void) ratio; 675 set_lcd_pixel_frequency(pclk); 676 } 677 678 // NOTE: Empty method for compatibility. 679 680 void 681 Cpm_jz4780_chip::update_output_frequency() 682 { 683 } 684 685 686 687 // C language interface functions. 688 689 void 690 *jz4780_cpm_init(l4_addr_t cpm_base) 691 { 692 /* Initialise the clock and power management peripheral with the 693 register memory region and a 48MHz EXCLK frequency. */ 694 695 return (void *) new Cpm_jz4780_chip(cpm_base, 48000000, 32768); 696 } 697 698 int 699 jz4780_cpm_have_clock(void *cpm) 700 { 701 return static_cast<Cpm_jz4780_chip *>(cpm)->have_clock(); 702 } 703 704 void 705 jz4780_cpm_start_clock(void *cpm) 706 { 707 static_cast<Cpm_jz4780_chip *>(cpm)->start_clock(); 708 } 709 710 711 712 void 713 jz4780_cpm_start_lcd(void *cpm) 714 { 715 static_cast<Cpm_jz4780_chip *>(cpm)->start_lcd(); 716 } 717 718 void 719 jz4780_cpm_stop_lcd(void *cpm) 720 { 721 static_cast<Cpm_jz4780_chip *>(cpm)->stop_lcd(); 722 } 723 724 725 726 uint8_t 727 jz4780_cpm_get_cpu_divider(void *cpm) 728 { 729 return static_cast<Cpm_jz4780_chip *>(cpm)->get_cpu_divider(); 730 } 731 732 uint8_t 733 jz4780_cpm_get_hclock0_divider(void *cpm) 734 { 735 return static_cast<Cpm_jz4780_chip *>(cpm)->get_hclock0_divider(); 736 } 737 738 uint8_t 739 jz4780_cpm_get_hclock2_divider(void *cpm) 740 { 741 return static_cast<Cpm_jz4780_chip *>(cpm)->get_hclock2_divider(); 742 } 743 744 uint8_t 745 jz4780_cpm_get_lcd_pixel_divider(void *cpm) 746 { 747 return static_cast<Cpm_jz4780_chip *>(cpm)->get_lcd_pixel_divider(); 748 } 749 750 uint8_t 751 jz4780_cpm_get_memory_divider(void *cpm) 752 { 753 return static_cast<Cpm_jz4780_chip *>(cpm)->get_memory_divider(); 754 } 755 756 uint8_t 757 jz4780_cpm_get_pclock_divider(void *cpm) 758 { 759 return static_cast<Cpm_jz4780_chip *>(cpm)->get_pclock_divider(); 760 } 761 762 763 764 uint8_t 765 jz4780_cpm_get_hclock0_source(void *cpm) 766 { 767 return static_cast<Cpm_jz4780_chip *>(cpm)->get_hclock0_source(); 768 } 769 770 uint8_t 771 jz4780_cpm_get_hclock2_source(void *cpm) 772 { 773 return static_cast<Cpm_jz4780_chip *>(cpm)->get_hclock2_source(); 774 } 775 776 uint8_t 777 jz4780_cpm_get_lcd_source(void *cpm) 778 { 779 return static_cast<Cpm_jz4780_chip *>(cpm)->get_lcd_source(); 780 } 781 782 uint8_t 783 jz4780_cpm_get_memory_source(void *cpm) 784 { 785 return static_cast<Cpm_jz4780_chip *>(cpm)->get_memory_source(); 786 } 787 788 uint8_t 789 jz4780_cpm_get_pclock_source(void *cpm) 790 { 791 return static_cast<Cpm_jz4780_chip *>(cpm)->get_pclock_source(); 792 } 793 794 void 795 jz4780_cpm_set_pclock_source(void *cpm, uint8_t source) 796 { 797 static_cast<Cpm_jz4780_chip *>(cpm)->set_pclock_source(source); 798 } 799 800 801 802 uint32_t 803 jz4780_cpm_get_hclock0_source_frequency(void *cpm) 804 { 805 return static_cast<Cpm_jz4780_chip *>(cpm)->get_hclock0_source_frequency(); 806 } 807 808 uint32_t 809 jz4780_cpm_get_hclock2_source_frequency(void *cpm) 810 { 811 return static_cast<Cpm_jz4780_chip *>(cpm)->get_hclock2_source_frequency(); 812 } 813 814 uint32_t 815 jz4780_cpm_get_lcd_source_frequency(void *cpm) 816 { 817 return static_cast<Cpm_jz4780_chip *>(cpm)->get_lcd_source_frequency(); 818 } 819 820 uint32_t 821 jz4780_cpm_get_memory_source_frequency(void *cpm) 822 { 823 return static_cast<Cpm_jz4780_chip *>(cpm)->get_memory_source_frequency(); 824 } 825 826 uint32_t 827 jz4780_cpm_get_pclock_source_frequency(void *cpm) 828 { 829 return static_cast<Cpm_jz4780_chip *>(cpm)->get_pclock_source_frequency(); 830 } 831 832 833 834 uint8_t 835 jz4780_cpm_get_main_source(void *cpm) 836 { 837 return static_cast<Cpm_jz4780_chip *>(cpm)->get_main_source(); 838 } 839 840 uint32_t 841 jz4780_cpm_get_main_frequency(void *cpm) 842 { 843 return static_cast<Cpm_jz4780_chip *>(cpm)->get_main_frequency(); 844 } 845 846 uint32_t 847 jz4780_cpm_get_cpu_frequency(void *cpm) 848 { 849 return static_cast<Cpm_jz4780_chip *>(cpm)->get_cpu_frequency(); 850 } 851 852 uint32_t 853 jz4780_cpm_get_hclock0_frequency(void *cpm) 854 { 855 return static_cast<Cpm_jz4780_chip *>(cpm)->get_hclock0_frequency(); 856 } 857 858 uint32_t 859 jz4780_cpm_get_hclock2_frequency(void *cpm) 860 { 861 return static_cast<Cpm_jz4780_chip *>(cpm)->get_hclock2_frequency(); 862 } 863 864 uint32_t 865 jz4780_cpm_get_lcd_pixel_frequency(void *cpm) 866 { 867 return static_cast<Cpm_jz4780_chip *>(cpm)->get_lcd_pixel_frequency(); 868 } 869 870 uint32_t 871 jz4780_cpm_get_memory_frequency(void *cpm) 872 { 873 return static_cast<Cpm_jz4780_chip *>(cpm)->get_memory_frequency(); 874 } 875 876 uint32_t 877 jz4780_cpm_get_pclock_frequency(void *cpm) 878 { 879 return static_cast<Cpm_jz4780_chip *>(cpm)->get_pclock_frequency(); 880 } 881 882 uint32_t 883 jz4780_cpm_get_apll_frequency(void *cpm) 884 { 885 return static_cast<Cpm_jz4780_chip *>(cpm)->get_apll_frequency(); 886 } 887 888 uint32_t 889 jz4780_cpm_get_epll_frequency(void *cpm) 890 { 891 return static_cast<Cpm_jz4780_chip *>(cpm)->get_epll_frequency(); 892 } 893 894 uint32_t 895 jz4780_cpm_get_mpll_frequency(void *cpm) 896 { 897 return static_cast<Cpm_jz4780_chip *>(cpm)->get_mpll_frequency(); 898 } 899 900 uint32_t 901 jz4780_cpm_get_vpll_frequency(void *cpm) 902 { 903 return static_cast<Cpm_jz4780_chip *>(cpm)->get_vpll_frequency(); 904 } 905 906 907 908 void 909 jz4780_cpm_set_lcd_pixel_frequency(void *cpm, uint32_t pclk) 910 { 911 static_cast<Cpm_jz4780_chip *>(cpm)->set_lcd_pixel_frequency(pclk); 912 } 913 914 void 915 jz4780_cpm_set_mpll_parameters(void *cpm, uint16_t multiplier, uint8_t in_divider, uint8_t out_divider) 916 { 917 static_cast<Cpm_jz4780_chip *>(cpm)->set_pll_parameters(Pll_control_M, multiplier, in_divider, out_divider); 918 }