1 /* 2 * DMA support for the X1600. 3 * 4 * Copyright (C) 2021, 2023, 2024 Paul Boddie <paul@boddie.org.uk> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 19 * Boston, MA 02110-1301, USA 20 */ 21 22 #pragma once 23 24 #include <l4/sys/types.h> 25 #include <stdint.h> 26 27 28 29 /* Enumerated types for various transfer parameters. */ 30 31 enum Dma_x1600_request_type 32 { 33 Dma_request_auto = 8, 34 Dma_request_can0_out = 10, 35 Dma_request_can0_in = 11, 36 Dma_request_can1_out = 12, 37 Dma_request_can1_in = 13, 38 Dma_request_uart3_out = 14, 39 Dma_request_uart3_in = 15, 40 Dma_request_uart2_out = 16, 41 Dma_request_uart2_in = 17, 42 Dma_request_uart1_out = 18, 43 Dma_request_uart1_in = 19, 44 Dma_request_uart0_out = 20, 45 Dma_request_uart0_in = 21, 46 Dma_request_ssi0_out = 22, 47 Dma_request_ssi0_in = 23, 48 Dma_request_i2c0_out = 36, 49 Dma_request_i2c0_in = 37, 50 Dma_request_i2c1_out = 38, 51 Dma_request_i2c1_in = 39, 52 Dma_request_ssi_slv_out = 42, 53 Dma_request_ssi_slv_in = 43, 54 Dma_request_pwm0_out = 44, 55 Dma_request_pwm1_out = 45, 56 Dma_request_pwm2_out = 46, 57 Dma_request_pwm3_out = 47, 58 Dma_request_pwm4_out = 48, 59 Dma_request_pwm5_out = 49, 60 Dma_request_pwm6_out = 50, 61 Dma_request_pwm7_out = 51, 62 Dma_request_msc0_out = 52, 63 Dma_request_msc0_in = 53, 64 Dma_request_msc1_out = 54, 65 Dma_request_msc1_in = 55, 66 Dma_request_sadc_in = 56, 67 Dma_request_aic_loop_out = 61, 68 Dma_request_aic_out = 62, 69 Dma_request_aic_in = 63, 70 }; 71 72 /* Descriptor structure. */ 73 74 struct x1600_dma_descriptor 75 { 76 uint32_t command, source, destination, transfer_count, 77 stride, request_source, reserved0, reserved1; 78 }; 79 80 81 82 #ifdef __cplusplus 83 84 #include <l4/devices/dma-generic.h> 85 #include <l4/devices/hw_mmio_register_block.h> 86 87 // Forward declaration. 88 89 class Dma_x1600_chip; 90 91 92 93 // DMA channel. 94 95 class Dma_x1600_channel : public Dma_channel 96 { 97 private: 98 Hw::Register_block<32> _regs; 99 Dma_chip *_chip; 100 uint8_t _channel; 101 l4_cap_idx_t _irq = L4_INVALID_CAP; 102 103 public: 104 Dma_x1600_channel(Dma_chip *chip, uint8_t channel, l4_addr_t start, l4_cap_idx_t irq); 105 106 unsigned int transfer(uint32_t source, uint32_t destination, 107 unsigned int count, 108 bool source_increment, bool destination_increment, 109 uint8_t source_width, uint8_t destination_width, 110 uint8_t transfer_unit_size, 111 int type=Dma_request_auto, 112 l4_addr_t desc_vaddr = 0, 113 l4re_dma_space_dma_addr_t desc_paddr = 0); 114 115 unsigned int wait(); 116 117 protected: 118 // Transfer property configuration. 119 120 uint32_t encode_req_detect_int_length(uint8_t units); 121 122 uint32_t encode_source_port_width(uint8_t width); 123 124 uint32_t encode_destination_port_width(uint8_t width); 125 126 uint32_t encode_transfer_unit_size(uint8_t size); 127 128 // Transaction control. 129 130 void ack_irq(); 131 132 void clear_errors(); 133 134 bool completed(); 135 136 bool error(); 137 138 bool halted(); 139 140 bool wait_for_irq(); 141 142 bool wait_for_irq(unsigned int timeout); 143 }; 144 145 // DMA device control. 146 147 class Dma_x1600_chip : public Dma_chip 148 { 149 private: 150 Hw::Register_block<32> _regs; 151 l4_addr_t _start, _end; 152 Cpm_chip *_cpm; 153 154 public: 155 Dma_x1600_chip(l4_addr_t start, l4_addr_t end, Cpm_chip *cpm); 156 157 void disable(); 158 159 void enable(); 160 161 Dma_channel *get_channel(uint8_t channel, l4_cap_idx_t irq = L4_INVALID_CAP); 162 163 // Transaction control. 164 165 void ack_irq(uint8_t channel); 166 167 void clear_errors(); 168 169 bool error(); 170 171 bool halted(); 172 173 bool have_interrupt(uint8_t channel); 174 175 // Descriptor operations. 176 177 void commit_descriptor(uint8_t channel); 178 }; 179 180 Dma_chip *x1600_dma_chip(l4_addr_t start, l4_addr_t end, Cpm_chip *cpm); 181 182 #endif /* __cplusplus */ 183 184 185 186 /* C language interface. */ 187 188 EXTERN_C_BEGIN 189 190 void *x1600_dma_init(l4_addr_t start, l4_addr_t end, void *cpm); 191 192 void x1600_dma_disable(void *dma_chip); 193 194 void x1600_dma_enable(void *dma_chip); 195 196 void *x1600_dma_get_channel(void *dma, uint8_t channel, l4_cap_idx_t irq); 197 198 unsigned int x1600_dma_transfer(void *dma_channel, 199 uint32_t source, uint32_t destination, 200 unsigned int count, 201 int source_increment, int destination_increment, 202 uint8_t source_width, uint8_t destination_width, 203 uint8_t transfer_unit_size, 204 enum Dma_x1600_request_type type); 205 206 unsigned int x1600_dma_wait(void *dma_channel); 207 208 EXTERN_C_END