1 /* 2 * LCD peripheral support for the JZ4740 and related SoCs. 3 * 4 * Copyright (C) Xiangfu Liu <xiangfu@sharism.cc> 5 * Copyright (C) 2015, 2016, 2017, 2018, 6 * 2020 Paul Boddie <paul@boddie.org.uk> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 21 * Boston, MA 02110-1301, USA 22 */ 23 24 #pragma once 25 26 27 28 enum Regs : unsigned 29 { 30 Lcd_config = 0x000, // LCD_CFG 31 Lcd_vsync = 0x004, // LCD_VSYNC 32 Lcd_hsync = 0x008, // LCD_HSYNC 33 Virtual_area = 0x00c, // LCD_VAT 34 Display_hlimits = 0x010, // LCD_DAH 35 Display_vlimits = 0x014, // LCD_DAV 36 Lcd_ps = 0x018, // LCD_PS 37 Lcd_cls = 0x01c, // LCD_CLS 38 Lcd_spl = 0x020, // LCD_SPL 39 Lcd_rev = 0x024, // LCD_REV 40 Lcd_control = 0x030, // LCD_CTRL 41 Lcd_status = 0x034, // LCD_STATE 42 Lcd_irq_id = 0x038, // LCD_IID 43 Desc_address_0 = 0x040, // LCD_DA0 44 Source_address_0 = 0x044, // LCD_SA0 45 Frame_id_0 = 0x048, // LCD_FID0 46 Command_0 = 0x04c, // LCD_CMD0 47 Counter_position_0 = 0x068, // LCD_CPOS0 48 Foreground_size_0 = 0x06c, // LCD_DESSIZE0 49 Desc_address_1 = 0x050, // LCD_DA1 50 Source_address_1 = 0x054, // LCD_SA1 51 Frame_id_1 = 0x058, // LCD_FID1 52 Command_1 = 0x05c, // LCD_CMD1 53 Counter_position_1 = 0x078, // LCD_CPOS1 54 Foreground_size_1 = 0x07c, // LCD_DESSIZE1 55 Rgb_control = 0x090, // LCD_RGBC (JZ4780) 56 Alpha_levels = 0x118, // LCD_ALPHA (JZ4780) 57 Priority_level = 0x2c0, // LCD_PCFG 58 59 // OSD registers. 60 61 Osd_config = 0x100, // LCD_OSDC 62 Osd_control = 0x104, // LCD_OSDCTRL 63 Osd_status = 0x108, // LCD_OSDS 64 }; 65 66 // Lcd_config descriptions. 67 68 enum Config_values : unsigned 69 { 70 Config_stn_pins_mask = 0x3, 71 Config_mode_mask = 0xf, 72 }; 73 74 // Field positions for registers employing two values, with the first typically 75 // being the start value and the second being an end value. 76 77 enum Value_pair_bits : unsigned 78 { 79 Value_first = 16, 80 Value_second = 0, 81 }; 82 83 // Virtual area bits. 84 85 enum Virtual_area_values : unsigned 86 { 87 Virtual_area_horizontal_size = Value_first, // sum of display and blank regions (dot/pixel clock periods) 88 Virtual_area_vertical_size = Value_second, // sum of display and blank regions (line periods) 89 }; 90 91 // Lcd_control descriptions. 92 93 enum Control_bits : unsigned 94 { 95 Control_pin_modify = 31, // PINMD (change pin usage from 15..0 to 17..10, 8..1) 96 Control_burst_length = 28, // BST (burst length selection) 97 Control_rgb_mode = 27, // RGB (RGB mode) 98 Control_out_underrun = 26, // OFUP (output FIFO underrun protection) 99 Control_frc_algorithm = 24, // FRC (STN FRC algorithm selection) 100 Control_palette_delay = 16, // PDD (load palette delay counter) 101 Control_dac_loopback_test = 14, // DACTE (DAC loopback test) 102 Control_frame_end_irq_enable = 13, // EOFM (end of frame interrupt enable) 103 Control_frame_start_irq_enable = 12, // SOFM (start of frame interrupt enable) 104 Control_out_underrun_irq_enable = 11, // OFUM (output FIFO underrun interrupt enable) 105 Control_in0_underrun_irq_enable = 10, // IFUM0 (input FIFO 0 underrun interrupt enable) 106 Control_in1_underrun_irq_enable = 9, // IFUM1 (input FIFO 1 underrun interrupt enable) 107 Control_disabled_irq_enable = 8, // LDDM (LCD disable done interrupt enable) 108 Control_quick_disabled_irq_enable = 7, // QDM (LCD quick disable done interrupt enable) 109 Control_endian_select = 6, // BEDN (endian selection) 110 Control_bit_order = 5, // PEDN (bit order in bytes) 111 Control_disable = 4, // DIS (disable controller) 112 Control_enable = 3, // ENA (enable controller) 113 Control_bpp = 0, // BPP (bits per pixel) 114 }; 115 116 enum Burst_length_values : unsigned 117 { 118 Burst_length_4 = 0, // 4 word 119 Burst_length_8 = 1, // 8 word 120 Burst_length_16 = 2, // 16 word 121 122 // JZ4780 extensions. 123 124 Burst_length_32 = 3, // 32 word 125 Burst_length_64 = 4, // 64 word 126 Burst_length_mask = 0x7, 127 }; 128 129 enum Rgb_mode_values : unsigned 130 { 131 Rgb_mode_565 = 0, 132 Rgb_mode_555 = 1, 133 Rgb_mode_mask = 0x1, 134 }; 135 136 enum Frc_algorithm_values : unsigned 137 { 138 Frc_greyscales_16 = 0, 139 Frc_greyscales_4 = 1, 140 Frc_greyscales_2 = 2, 141 Frc_greyscales_mask = 0x3, 142 }; 143 144 enum Control_bpp_values : unsigned 145 { 146 Control_bpp_1bpp = 0, 147 Control_bpp_2bpp = 1, 148 Control_bpp_4bpp = 2, 149 Control_bpp_8bpp = 3, 150 Control_bpp_15bpp = 4, 151 Control_bpp_16bpp = 4, 152 Control_bpp_18bpp = 5, 153 Control_bpp_24bpp = 5, 154 Control_bpp_24bpp_comp = 6, 155 Control_bpp_30bpp = 7, 156 Control_bpp_32bpp = 7, 157 Control_bpp_mask = 0x7, 158 }; 159 160 // Command descriptions. 161 162 enum Command_bits : unsigned 163 { 164 Command_frame_start_irq = 31, // SOFINT (start of frame interrupt) 165 Command_frame_end_irq = 30, // EOFINT (end of frame interrupt) 166 Command_lcm_command = 29, // JZ4780: CMD (LCM command/data via DMA0) 167 Command_palette_buffer = 28, // PAL (descriptor references palette, not display data) 168 Command_frame_compressed = 27, // JZ4780: COMPEN (16/24bpp compression enabled) 169 Command_frame_enable = 26, // JZ4780: FRM_EN 170 Command_field_even = 25, // JZ4780: FIELD_SEL (interlace even field) 171 Command_16x16_block = 24, // JZ4780: 16x16BLOCK (fetch data by 16x16 block) 172 Command_buffer_length = 0, // LEN 173 }; 174 175 enum Command_values : unsigned 176 { 177 Command_buffer_length_mask = 0x00ffffff, 178 }; 179 180 // Status descriptions. 181 182 enum Status_bits : unsigned 183 { 184 Status_frame_end_irq = 5, 185 Status_frame_start_irq = 4, 186 Status_out_underrun_irq = 3, 187 Status_in0_underrun_irq = 2, 188 Status_in1_underrun_irq = 1, 189 Status_disabled = 0, 190 }; 191 192 // OSD configuration bits (JZ4780). 193 194 enum Osd_config_bits : unsigned 195 { 196 Osd_config_fg1_pixel_alpha_enable = 17, 197 Osd_config_fg1_frame_start_irq_enable = 15, 198 Osd_config_fg1_frame_end_irq_enable = 14, 199 Osd_config_fg0_frame_start_irq_enable = 11, 200 Osd_config_fg0_frame_end_irq_enable = 10, 201 Osd_config_fg1_enable = 4, 202 Osd_config_fg0_enable = 3, 203 Osd_config_alpha_enable = 2, 204 Osd_config_fg0_pixel_alpha_enable = 1, 205 Osd_config_enable = 0, 206 }; 207 208 enum Osd_control_bits : unsigned 209 { 210 Osd_control_ipu_clock_enable = 15, 211 }; 212 213 // RGB control (JZ4780). 214 215 enum Rgb_control_bits : unsigned 216 { 217 Rgb_data_padded = 15, // RGBDM 218 Rgb_padding_mode = 14, // DMM 219 Rgb_422 = 8, // 422 220 Rgb_format_enable = 7, // RGBFMT 221 Rgb_odd_line = 4, // OddRGB 222 Rgb_even_line = 0, // EvenRGB 223 }; 224 225 enum Rgb_control_values : unsigned 226 { 227 Rgb_padding_end = 0U << Rgb_padding_mode, 228 Rgb_padding_start = 1U << Rgb_padding_mode, 229 Rgb_odd_line_rgb = 0U << Rgb_odd_line, 230 Rgb_odd_line_rbg = 1U << Rgb_odd_line, 231 Rgb_odd_line_grb = 2U << Rgb_odd_line, 232 Rgb_odd_line_gbr = 3U << Rgb_odd_line, 233 Rgb_odd_line_brg = 4U << Rgb_odd_line, 234 Rgb_odd_line_bgr = 5U << Rgb_odd_line, 235 Rgb_even_line_rgb = 0U << Rgb_even_line, 236 Rgb_even_line_rbg = 1U << Rgb_even_line, 237 Rgb_even_line_grb = 2U << Rgb_even_line, 238 Rgb_even_line_gbr = 3U << Rgb_even_line, 239 Rgb_even_line_brg = 4U << Rgb_even_line, 240 Rgb_even_line_bgr = 5U << Rgb_even_line, 241 }; 242 243 // Alpha levels (JZ4780). 244 245 enum Alpha_levels_bits : unsigned 246 { 247 Alpha_level_fg1 = 8, 248 Alpha_level_fg0 = 0, 249 }; 250 251 enum Alpha_levels_values : unsigned 252 { 253 Alpha_level_fg1_mask = 0x0000ff00, 254 Alpha_level_fg0_mask = 0x000000ff, 255 }; 256 257 // Priority level. 258 259 enum Priority_level_bits : unsigned 260 { 261 Priority_mode = 31, 262 Priority_highest_burst = 28, 263 Priority_threshold2 = 18, 264 Priority_threshold1 = 9, 265 Priority_threshold0 = 0, 266 }; 267 268 enum Priority_level_values : unsigned 269 { 270 Priority_mode_dynamic = 0U << Priority_mode, 271 Priority_mode_arbiter = 1U << Priority_mode, 272 }; 273 274 enum Priority_burst_values : unsigned 275 { 276 Priority_burst_4 = 0, 277 Priority_burst_8 = 1, 278 Priority_burst_16 = 2, 279 Priority_burst_32 = 3, 280 Priority_burst_64 = 4, 281 Priority_burst_16_cont = 5, 282 Priority_burst_disable = 7, 283 }; 284 285 // Position descriptor member. 286 287 enum Position_bits : unsigned 288 { 289 Position_bpp = 27, 290 Position_premultiply_lcd = 26, 291 Position_coefficient = 24, 292 Position_y_position = 12, 293 Position_x_position = 0, 294 }; 295 296 enum Position_values : unsigned 297 { 298 Position_bpp_15_16bpp = 4, 299 Position_bpp_18_24bpp = 5, 300 Position_bpp_30bpp = 7, 301 };