1 /* 2 * DMA support for the JZ4780. 3 * 4 * Copyright (C) 2021, 2023 Paul Boddie <paul@boddie.org.uk> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 19 * Boston, MA 02110-1301, USA 20 */ 21 22 #pragma once 23 24 #include <l4/sys/types.h> 25 #include <stdint.h> 26 27 28 29 /* Enumerated types for various transfer parameters. */ 30 31 enum Dma_jz4780_request_type 32 { 33 Dma_request_i2s1_out = 4, 34 Dma_request_i2s1_in = 5, 35 Dma_request_i2s0_out = 6, 36 Dma_request_i2s0_in = 7, 37 Dma_request_auto = 8, 38 Dma_request_sadc_in = 9, 39 Dma_request_uart4_out = 12, 40 Dma_request_uart4_in = 13, 41 Dma_request_uart3_out = 14, 42 Dma_request_uart3_in = 15, 43 Dma_request_uart2_out = 16, 44 Dma_request_uart2_in = 17, 45 Dma_request_uart1_out = 18, 46 Dma_request_uart1_in = 19, 47 Dma_request_uart0_out = 20, 48 Dma_request_uart0_in = 21, 49 Dma_request_ssi0_out = 22, 50 Dma_request_ssi0_in = 23, 51 Dma_request_ssi1_out = 24, 52 Dma_request_ssi1_in = 25, 53 Dma_request_msc0_out = 26, 54 Dma_request_msc0_in = 27, 55 Dma_request_msc1_out = 28, 56 Dma_request_msc1_in = 29, 57 Dma_request_msc2_out = 30, 58 Dma_request_msc2_in = 31, 59 Dma_request_pcm0_out = 32, 60 Dma_request_pcm0_in = 33, 61 Dma_request_i2c0_out = 36, 62 Dma_request_i2c0_in = 37, 63 Dma_request_i2c1_out = 38, 64 Dma_request_i2c1_in = 39, 65 Dma_request_i2c2_out = 40, 66 Dma_request_i2c2_in = 41, 67 Dma_request_i2c3_out = 42, 68 Dma_request_i2c3_in = 43, 69 Dma_request_i2c4_out = 44, 70 Dma_request_i2c4_in = 45, 71 Dma_request_des_out = 46, 72 Dma_request_des_in = 47, 73 }; 74 75 /* Descriptor structure. */ 76 77 struct jz4780_dma_descriptor 78 { 79 uint32_t command, source, destination, transfer_count, 80 stride, request_source, reserved0, reserved1; 81 }; 82 83 84 85 #ifdef __cplusplus 86 87 #include <l4/devices/dma-generic.h> 88 #include <l4/devices/hw_mmio_register_block.h> 89 90 // Forward declaration. 91 92 class Dma_jz4780_chip; 93 94 95 96 // DMA channel. 97 98 class Dma_jz4780_channel : public Dma_channel 99 { 100 private: 101 Hw::Register_block<32> _regs; 102 Dma_chip *_chip; 103 uint8_t _channel; 104 l4_cap_idx_t _irq = L4_INVALID_CAP; 105 106 public: 107 Dma_jz4780_channel(Dma_chip *chip, uint8_t channel, l4_addr_t start, 108 l4_cap_idx_t irq = L4_INVALID_CAP); 109 110 unsigned int transfer(uint32_t source, uint32_t destination, 111 unsigned int count, 112 bool source_increment, bool destination_increment, 113 uint8_t source_width, uint8_t destination_width, 114 uint8_t transfer_unit_size, 115 int type=Dma_request_auto, 116 l4_addr_t desc_vaddr = 0, 117 l4re_dma_space_dma_addr_t desc_paddr = 0); 118 119 unsigned int wait(); 120 121 protected: 122 // Transfer property configuration. 123 124 uint32_t encode_req_detect_int_length(uint8_t units); 125 126 uint32_t encode_source_port_width(uint8_t width); 127 128 uint32_t encode_destination_port_width(uint8_t width); 129 130 uint32_t encode_transfer_unit_size(uint8_t size); 131 132 // Transaction control. 133 134 void ack_irq(); 135 136 bool completed(); 137 138 bool error(); 139 140 bool halted(); 141 142 bool wait_for_irq(); 143 144 bool wait_for_irq(unsigned int timeout); 145 }; 146 147 // DMA device control. 148 149 class Dma_jz4780_chip : public Dma_chip 150 { 151 private: 152 Hw::Register_block<32> _regs; 153 l4_addr_t _start, _end; 154 Cpm_chip *_cpm; 155 156 public: 157 Dma_jz4780_chip(l4_addr_t start, l4_addr_t end, Cpm_chip *cpm); 158 159 void disable(); 160 161 void enable(); 162 163 Dma_channel *get_channel(uint8_t channel, 164 l4_cap_idx_t irq = L4_INVALID_CAP); 165 166 // Transaction control. 167 168 void ack_irq(uint8_t channel); 169 170 bool error(); 171 172 bool halted(); 173 174 bool have_interrupt(uint8_t channel); 175 176 // Descriptor operations. 177 178 void commit_descriptor(uint8_t channel); 179 }; 180 181 Dma_chip *jz4780_dma_chip(l4_addr_t start, l4_addr_t end, Cpm_chip *cpm); 182 183 #endif /* __cplusplus */ 184 185 186 187 /* C language interface. */ 188 189 EXTERN_C_BEGIN 190 191 void *jz4780_dma_init(l4_addr_t start, l4_addr_t end, void *cpm); 192 193 void jz4780_dma_disable(void *dma_chip); 194 195 void jz4780_dma_enable(void *dma_chip); 196 197 void *jz4780_dma_get_channel(void *dma, uint8_t channel, l4_cap_idx_t irq); 198 199 unsigned int jz4780_dma_transfer(void *dma_channel, 200 uint32_t source, uint32_t destination, 201 unsigned int count, 202 int source_increment, int destination_increment, 203 uint8_t source_width, uint8_t destination_width, 204 uint8_t transfer_unit_size, 205 enum Dma_jz4780_request_type type); 206 207 unsigned int jz4780_dma_transfer_descriptor(void *dma_channel, 208 uint32_t source, uint32_t destination, 209 unsigned int count, 210 int source_increment, int destination_increment, 211 uint8_t source_width, uint8_t destination_width, 212 uint8_t transfer_unit_size, 213 enum Dma_jz4780_request_type type, 214 l4_addr_t desc_vaddr, 215 l4re_dma_space_dma_addr_t desc_paddr); 216 217 unsigned int jz4780_dma_wait(void *dma_channel); 218 219 EXTERN_C_END