# HG changeset patch # User Paul Boddie # Date 1591018658 -7200 # Node ID 06245dc45ea3727e44e5f945f5fcb21f5bde804b # Parent 5401b7ef73afacc71905ed9a8234ee790ac67086 Added tentative and untidy support for DVI mode signal generation. diff -r 5401b7ef73af -r 06245dc45ea3 pkg/devices/lib/hdmi/include/hdmi-jz4780.h --- a/pkg/devices/lib/hdmi/include/hdmi-jz4780.h Sat May 23 22:34:17 2020 +0200 +++ b/pkg/devices/lib/hdmi/include/hdmi-jz4780.h Mon Jun 01 15:37:38 2020 +0200 @@ -3,6 +3,11 @@ * * Copyright (C) 2020 Paul Boddie * + * Some structures have been adopted from the Linux DRM bridge driver for + * Synopsys DW-HDMI with the following attribution: + * + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of @@ -21,11 +26,60 @@ #pragma once +#include #include #include +// PHY capability definition type. + +struct Phy_capabilities +{ + uint8_t type; + const char *name; + int gen; + int svsret; + int configure; +}; + + + +// PHY configuration types. + +enum Phy_resolutions +{ + Phy_resolution_8bpc = 0, + Phy_resolution_10bpc = 1, + Phy_resolution_12bpc = 2, + Phy_resolution_count = 3, +}; + +struct Phy_mpll_config +{ + unsigned long pixelclock; // frequency (Hz) + struct { + uint16_t cpce; + uint16_t gmp; + } res[Phy_resolution_count]; +}; + +struct Phy_curr_ctrl +{ + unsigned long pixelclock; // frequency (Hz) + uint16_t curr[Phy_resolution_count]; +}; + +struct Phy_config +{ + unsigned long pixelclock; // frequency (Hz) + uint16_t symbol; // clock symbol and transmitter control + uint16_t term; // transmission termination value + uint16_t vlevel; // voltage level control +}; + + + #ifdef __cplusplus #include @@ -42,34 +96,101 @@ // Identification. uint16_t _version; + uint8_t _phy_type; + const struct Phy_capabilities *_phy_def; + + // Input/output properties. + + struct Jz4740_lcd_panel *_panel; + unsigned long _pixelclock; // Transfer properties. bool _segment_read; - uint8_t _device_register; + uint8_t _device_register, _phy_device_register; + + // Convenience methods for register access. + + void reg_update(uint32_t reg, uint32_t bits, bool enable); + void reg_update_field(uint32_t reg, uint32_t mask, uint32_t bits); + void reg_fill_field(uint32_t reg, uint32_t mask); protected: + unsigned long get_pixelclock(); + void get_identification(); void irq_init(); - void i2c_init(); - long i2c_wait(); + void i2c_init(uint32_t reset, uint32_t divider, uint32_t config0, + uint32_t config1, uint32_t status, uint32_t mask); - void hotplug_init(); + long i2c_wait(uint32_t status); + + void phy_irq_init(); public: - Hdmi_jz4780_chip(l4_addr_t start, l4_addr_t end, l4_cap_idx_t irq); + Hdmi_jz4780_chip(l4_addr_t start, l4_addr_t end, l4_cap_idx_t irq, + struct Jz4740_lcd_panel *panel); + + // Chipset querying. void get_version(uint8_t *major, uint16_t *minor); + void get_phy_capabilities(const struct Phy_capabilities **phy_def); + + // I2C operations. int i2c_read(uint8_t *buf, unsigned int length); + void i2c_set_address(uint8_t address); void i2c_set_segment(uint8_t segment); void i2c_set_register(uint8_t device_register); + int i2c_phy_write(uint8_t address, uint16_t value); + int i2c_phy_write(uint16_t *buf, unsigned int length); + + void i2c_phy_set_address(uint8_t address); + void i2c_phy_set_register(uint8_t device_register); + + // PHY configuration operations. + + void phy_enable_powerdown(bool enable); + void phy_enable_tmds(bool enable); + void phy_enable_svsret(bool enable); + void phy_enable_gen2_powerdown(bool enable); + void phy_enable_gen2_tx_power(bool enable); + void phy_enable_interface(bool enable); + + // PHY operations. + + long phy_configure(); + long phy_configure_specific(); + long phy_init(); + void phy_power_off(); + void phy_power_on(); + void phy_reset(); + + // Hotplug and signalling support. + bool connected(); long wait_for_connection(); + long wait_for_tx_phy_lock(int level); + long wait_for_phy_irq(uint32_t int_status_flags, uint32_t status_flags, + uint32_t polarity_flags); + + // Video output initialisation. + + void enable_overflow_irq(bool enable); + void frame_init(); + void data_path_init(); + void packet_init(); + void csc_init(); + void sample_init(); + void hdcp_init(); + + // Enable the video output. + + long enable(unsigned long pixelclock); }; #endif /* __cplusplus */ @@ -80,10 +201,13 @@ EXTERN_C_BEGIN -void *jz4780_hdmi_init(l4_addr_t start, l4_addr_t end, l4_cap_idx_t irq); +void *jz4780_hdmi_init(l4_addr_t start, l4_addr_t end, l4_cap_idx_t irq, + struct Jz4740_lcd_panel *panel); void jz4780_hdmi_get_version(void *hdmi, uint8_t *major, uint16_t *minor); +void jz4780_hdmi_get_phy_capabilities(void *hdmi, const struct Phy_capabilities **phy_def); + int jz4780_hdmi_i2c_read(void *hdmi, uint8_t *buf, unsigned int length); void jz4780_hdmi_i2c_set_address(void *hdmi, uint8_t address); @@ -92,8 +216,16 @@ void jz4780_hdmi_i2c_set_register(void *hdmi, uint8_t device_register); +int jz4780_hdmi_phy_i2c_write(void *hdmi, uint16_t *buf, unsigned int length); + +void jz4780_hdmi_i2c_phy_set_address(void *hdmi, uint8_t address); + +void jz4780_hdmi_i2c_phy_set_register(void *hdmi, uint8_t device_register); + int jz4780_hdmi_connected(void *hdmi); long jz4780_hdmi_wait_for_connection(void *hdmi); +long jz4780_hdmi_enable(void *hdmi, unsigned long pixelclock); + EXTERN_C_END diff -r 5401b7ef73af -r 06245dc45ea3 pkg/devices/lib/hdmi/src/jz4780.cc --- a/pkg/devices/lib/hdmi/src/jz4780.cc Sat May 23 22:34:17 2020 +0200 +++ b/pkg/devices/lib/hdmi/src/jz4780.cc Mon Jun 01 15:37:38 2020 +0200 @@ -3,6 +3,13 @@ * * Copyright (C) 2020 Paul Boddie * + * Techniques and operations introduced from the Linux DRM bridge driver for + * Synopsys DW-HDMI whose authors are as follows: + * + * Copyright (C) 2013-2015 Mentor Graphics Inc. + * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. + * Copyright (C) 2010, Guennadi Liakhovetski + * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of @@ -17,10 +24,31 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, * Boston, MA 02110-1301, USA + * + * ---- + * + * Some acronyms: + * + * CEC (Consumer Electronics Control) is a HDMI device control interface for up + * to 15 devices. + * + * CSC (Colour Space Conversion) is the processing needed to convert from one + * representation of colours to another. + * + * HEAC (HDMI Ethernet and Audio Return Channel) is a combination of HEC (HDMI + * Ethernet Channel) which provides a 100Mb/s bidirectional link and ARC (Audio + * Return Channel) which permits the consumption of audio data from the device. + * + * MHL (Mobile High-Definition Link) is an adaptation of HDMI for mobile + * devices. + * + * TMDS (Transition-Minimized Differential Signaling) is the method by which + * audio, control and video data are all sent to the device. */ #include #include +#include #include #include @@ -39,74 +67,150 @@ { // Identification. - Design_id = 0x000, // DESIGN_ID - Revision_id = 0x001, // REVISION_ID - Product_id0 = 0x002, // PRODUCT_ID0 - Product_id1 = 0x003, // PRODUCT_ID1 - Config_id0 = 0x004, // CONFIG_ID0 - Config_id1 = 0x005, // CONFIG_ID1 - Config_id2 = 0x006, // CONFIG_ID2 - Config_id3 = 0x007, // CONFIG_ID3 + Design_id = 0x000, // DESIGN_ID + Revision_id = 0x001, // REVISION_ID + Product_id0 = 0x002, // PRODUCT_ID0 + Product_id1 = 0x003, // PRODUCT_ID1 + Config_id0 = 0x004, // CONFIG_ID0 + Config_id1 = 0x005, // CONFIG_ID1 + Config_id2 = 0x006, // CONFIG_ID2 + Config_id3 = 0x007, // CONFIG_ID3 // Top-level interrupt control. - Int_mask = 0x1ff, // MUTE + Int_mask = 0x1ff, // MUTE // Interrupt status and mask for various functions. - Fc_int_status0 = 0x100, // FC_STAT0 - Fc_int_status1 = 0x101, // FC_STAT1 - Fc_int_status2 = 0x102, // FC_STAT2 - As_int_status = 0x103, // AS_STAT0 - Phy_int_status = 0x104, // PHY_STAT0 - Cec_int_status = 0x106, // CEC_STAT0 - Vp_int_status = 0x107, // VP_STAT0 - Ahb_dma_audio_int_status = 0x109, // AHBDMAAUD_STAT0 + Fc_int_status0 = 0x100, // FC_STAT0 + Fc_int_status1 = 0x101, // FC_STAT1 + Fc_int_status2 = 0x102, // FC_STAT2 + As_int_status = 0x103, // AS_STAT0 + Phy_int_status = 0x104, // PHY_STAT0 + Cec_int_status = 0x106, // CEC_STAT0 + Vp_int_status = 0x107, // VP_STAT0 + Ahb_dma_audio_int_status = 0x109, // AHBDMAAUD_STAT0 - Fc_int_mask0 = 0x180, // MUTE_FC_STAT0 - Fc_int_mask1 = 0x181, // MUTE_FC_STAT1 - Fc_int_mask2 = 0x182, // MUTE_FC_STAT2 - As_int_mask = 0x183, // MUTE_AS_STAT0 - Phy_int_mask = 0x184, // MUTE_PHY_STAT0 - Cec_int_mask = 0x186, // MUTE_CEC_STAT0 - Vp_int_mask = 0x187, // MUTE_VP_STAT0 - Ahb_dma_audio_int_mask = 0x189, // MUTE_AHBDMAAUD_STAT0 + Fc_int_mask0 = 0x180, // MUTE_FC_STAT0 + Fc_int_mask1 = 0x181, // MUTE_FC_STAT1 + Fc_int_mask2 = 0x182, // MUTE_FC_STAT2 + As_int_mask = 0x183, // MUTE_AS_STAT0 + Phy_int_mask = 0x184, // MUTE_PHY_STAT0 + Cec_int_mask = 0x186, // MUTE_CEC_STAT0 + Vp_int_mask = 0x187, // MUTE_VP_STAT0 + Ahb_dma_audio_int_mask = 0x189, // MUTE_AHBDMAAUD_STAT0 // I2C for E-DDC. - I2c_int_status = 0x105, // I2CM_STAT0 - I2c_int_mask = 0x185, // MUTE_I2CM_STAT0 + I2c_int_status = 0x105, // I2CM_STAT0 + I2c_int_mask = 0x185, // MUTE_I2CM_STAT0 - I2c_device_address = 0x7e00, // I2CM_SLAVE - I2c_register = 0x7e01, // I2CM_ADDRESS - I2c_data_out = 0x7e02, // I2CM_DATAO - I2c_data_in = 0x7e03, // I2CM_DATAI - I2c_operation = 0x7e04, // I2CM_OPERATION - I2c_int_config0 = 0x7e05, // I2CM_INT - I2c_int_config1 = 0x7e06, // I2CM_CTLINT - I2c_divider = 0x7e07, // I2CM_DIV - I2c_segment_address = 0x7e08, // I2CM_SEGADDR - I2c_software_reset = 0x7e09, // I2CM_SOFTRSTZ - I2c_segment_pointer = 0x7e0a, // I2CM_SEGPTR + I2c_device_address = 0x7e00, // I2CM_SLAVE + I2c_register = 0x7e01, // I2CM_ADDRESS + I2c_data_out = 0x7e02, // I2CM_DATAO + I2c_data_in = 0x7e03, // I2CM_DATAI + I2c_operation = 0x7e04, // I2CM_OPERATION + I2c_int_config0 = 0x7e05, // I2CM_INT + I2c_int_config1 = 0x7e06, // I2CM_CTLINT + I2c_divider = 0x7e07, // I2CM_DIV + I2c_segment_address = 0x7e08, // I2CM_SEGADDR + I2c_software_reset = 0x7e09, // I2CM_SOFTRSTZ + I2c_segment_pointer = 0x7e0a, // I2CM_SEGPTR // I2C for PHY. - I2c_phy_int_status = 0x108, // I2CMPHY_STAT0 - I2c_phy_int_mask = 0x188, // MUTE_I2CMPHY_STAT0 + I2c_phy_int_status = 0x108, // I2CMPHY_STAT0 + I2c_phy_int_mask = 0x188, // MUTE_I2CMPHY_STAT0 - I2c_phy_int_config0 = 0x3027, // PHY_I2CM_INT_ADDR - I2c_phy_int_config1 = 0x3028, // PHY_I2CM_CTLINT_ADDR + I2c_phy_device_address = 0x3020, // PHY_I2CM_SLAVE_ADDR + I2c_phy_register = 0x3021, // PHY_I2CM_ADDRESS_ADDR + I2c_phy_data_out1 = 0x3022, // PHY_I2CM_DATAO_1_ADDR + I2c_phy_data_out0 = 0x3023, // PHY_I2CM_DATAO_0_ADDR + I2c_phy_data_in1 = 0x3024, // PHY_I2CM_DATAI_1_ADDR + I2c_phy_data_in0 = 0x3025, // PHY_I2CM_DATAI_0_ADDR + I2c_phy_operation = 0x3026, // PHY_I2CM_OPERATION_ADDR + I2c_phy_int_config0 = 0x3027, // PHY_I2CM_INT_ADDR + I2c_phy_int_config1 = 0x3028, // PHY_I2CM_CTLINT_ADDR + I2c_phy_divider = 0x3029, // PHY_I2CM_DIV_ADDR + I2c_phy_software_reset = 0x302a, // PHY_I2CM_SOFTRSTZ_ADDR // PHY registers. - Phy_config = 0x3000, // PHY_CONF0 - Phy_test0 = 0x3001, // PHY_TST0 - Phy_test1 = 0x3002, // PHY_TST1 - Phy_test2 = 0x3003, // PHY_TST2 - Phy_status = 0x3004, // PHY_STAT0 - Phy_int_config = 0x3005, // PHY_INT0 - Phy_mask = 0x3006, // PHY_MASK0 - Phy_polarity = 0x3007, // PHY_POL0 + Phy_config = 0x3000, // PHY_CONF0 + Phy_test0 = 0x3001, // PHY_TST0 + Phy_test1 = 0x3002, // PHY_TST1 + Phy_test2 = 0x3003, // PHY_TST2 + Phy_status = 0x3004, // PHY_STAT0 + Phy_int_config = 0x3005, // PHY_INT0 + Phy_mask = 0x3006, // PHY_MASK0 + Phy_polarity = 0x3007, // PHY_POL0 + + // Main controller registers. + + Main_clock_disable = 0x4001, // MC_CLKDIS + Main_software_reset = 0x4002, // MC_SWRSTZ + Main_flow_control = 0x4004, // MC_FLOWCTRL + Main_reset = 0x4005, // MC_PHYRSTZ + Main_heac_phy_reset = 0x4007, // MC_HEACPHY_RST + + // Frame composer registers for input video. + + Fc_video_config = 0x1000, // FC_INVIDCONF + Fc_horizontal_active_width0 = 0x1001, // FC_INHACTV0 + Fc_horizontal_active_width1 = 0x1002, // FC_INHACTV1 + Fc_horizontal_blank_width0 = 0x1003, // FC_INHBLANK0 + Fc_horizontal_blank_width1 = 0x1004, // FC_INHBLANK1 + Fc_vertical_active_height0 = 0x1005, // FC_INVACTV0 + Fc_vertical_active_height1 = 0x1006, // FC_INVACTV1 + Fc_vertical_blank_height = 0x1007, // FC_INVBLANK + + // Frame composer registers for sync pulses. + + Fc_hsync_delay0 = 0x1008, // FC_HSYNCINDELAY0 + Fc_hsync_delay1 = 0x1009, // FC_HSYNCINDELAY1 + Fc_hsync_width0 = 0x100A, // FC_HSYNCINWIDTH0 + Fc_hsync_width1 = 0x100B, // FC_HSYNCINWIDTH1 + Fc_vsync_delay = 0x100C, // FC_VSYNCINDELAY + Fc_vsync_height = 0x100D, // FC_VSYNCINWIDTH + + // Frame composer registers for video path configuration. + + Fc_control_duration = 0x1011, // FC_CTRLDUR + Fc_ex_control_duration = 0x1012, // FC_EXCTRLDUR + Fc_ex_control_space = 0x1013, // FC_EXCTRLSPAC + Fc_channel0_preamble = 0x1014, // FC_CH0PREAM + Fc_channel1_preamble = 0x1015, // FC_CH1PREAM + Fc_channel2_preamble = 0x1016, // FC_CH2PREAM + + // Colour space conversion registers. + + Csc_config = 0x4100, // CSC_CFG + Csc_scale = 0x4101, // CSC_SCALE + + // HDCP registers. + + Hdcp_config0 = 0x5000, // A_HDCPCFG0 + Hdcp_config1 = 0x5001, // A_HDCPCFG1 + Hdcp_video_polarity = 0x5009, // A_VIDPOLCFG + + // Video sample registers. + + Sample_video_config = 0x0200, // TX_INVID0 + Sample_video_stuffing = 0x0201, // TX_INSTUFFING + Sample_gy_data0 = 0x0202, // TX_GYDATA0 + Sample_gy_data1 = 0x0203, // TX_GYDATA1 + Sample_rcr_data0 = 0x0204, // TX_RCRDATA0 + Sample_rcr_data1 = 0x0205, // TX_RCRDATA1 + Sample_bcb_data0 = 0x0206, // TX_BCBDATA0 + Sample_bcb_data1 = 0x0207, // TX_BCBDATA1 + + // Video packetizer registers. + + Packet_status = 0x0800, // VP_STATUS + Packet_pixel_repeater = 0x0801, // VP_PR_CD + Packet_stuffing = 0x0802, // VP_STUFF + Packet_remap = 0x0803, // VP_REMAP + Packet_config = 0x0804, // VP_CONF }; // Identification values. @@ -149,6 +253,8 @@ Int_mask_all = 0x01, }; +// I2C status and mask bits, also for PHY I2C. + enum I2c_int_status_bits : unsigned { I2c_int_status_done = 0x02, @@ -160,38 +266,73 @@ enum I2c_operation_bits : unsigned { I2c_operation_write = 0x10, - I2c_operation_segment_read = 0x02, + I2c_operation_segment_read = 0x02, // not PHY I2C I2c_operation_read = 0x01, }; -// Interrupt configuration bits. +// Device addresses. + +enum I2c_phy_device_addresses : unsigned +{ + I2c_phy_device_phy_gen2 = 0x69, // PHY_I2CM_SLAVE_ADDR_PHY_GEN2 + I2c_phy_device_phy_heac = 0x49, // PHY_I2CM_SLAVE_ADDR_HEAC_PHY +}; + +// Device registers. + +enum I2c_phy_device_registers : unsigned +{ + I2c_phy_3d_tx_clock_cal_ctrl = 0x05, // 3D_TX_PHY_CKCALCTRL + I2c_phy_3d_tx_cpce_ctrl = 0x06, // 3D_TX_PHY_CPCE_CTRL + I2c_phy_3d_tx_clock_symbol_ctrl = 0x09, // 3D_TX_PHY_CKSYMTXCTRL + I2c_phy_3d_tx_vlevel_ctrl = 0x0e, // 3D_TX_PHY_VLEVCTRL + I2c_phy_3d_tx_curr_ctrl = 0x10, // 3D_TX_PHY_CURRCTRL + I2c_phy_3d_tx_pll_phby_ctrl = 0x13, // 3D_TX_PHY_PLLPHBYCTRL + I2c_phy_3d_tx_gmp_ctrl = 0x15, // 3D_TX_PHY_GMPCTRL + I2c_phy_3d_tx_msm_ctrl = 0x17, // 3D_TX_PHY_MSM_CTRL + I2c_phy_3d_tx_term = 0x19, // 3D_TX_PHY_TXTERM +}; + +// PHY I2C register values. + +enum Msm_ctrl_bits : unsigned +{ + Msm_ctrl_clock_output_select_fb = 1 << 3, // 3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK +}; + +enum Clock_cal_ctrl_bits : unsigned +{ + Clock_cal_ctrl_override = 1 << 15, // 3D_TX_PHY_CKCALCTRL_OVERRIDE +}; + +// Interrupt configuration bits, also for PHY I2C. enum I2c_int_config0_bits : unsigned { - I2c_int_config0_done_polarity = 0x08, - I2c_int_config0_done_mask = 0x04, + I2c_int_config0_done_polarity = 0x08, + I2c_int_config0_done_mask = 0x04, }; enum I2c_int_config1_bits : unsigned { - I2c_int_config1_nack_polarity = 0x80, - I2c_int_config1_nack_mask = 0x40, - I2c_int_config1_arb_polarity = 0x08, - I2c_int_config1_arb_mask = 0x04, + I2c_int_config1_nack_polarity = 0x80, + I2c_int_config1_nack_mask = 0x40, + I2c_int_config1_arb_polarity = 0x08, + I2c_int_config1_arb_mask = 0x04, }; // PHY configuration values. enum Phy_config_bits : unsigned { - Phy_config_pdz_mask = 0x80, // PHY_CONF0_PDZ_MASK - Phy_config_enable_tmds_mask = 0x40, // PHY_CONF0_ENTMDS_MASK - Phy_config_svsret_mask = 0x20, // PHY_CONF0_SVSRET_MASK - Phy_config_gen2_pddq_mask = 0x10, // PHY_CONF0_GEN2_PDDQ_MASK - Phy_config_gen2_tx_power_on_mask = 0x08, // PHY_CONF0_GEN2_TXPWRON_MASK - Phy_config_gen2_enable_hotplug_detect_rx_sense_mask = 0x04, // PHY_CONF0_GEN2_ENHPDRXSENSE_MASK - Phy_config_select_data_enable_polarity_mask = 0x02, // PHY_CONF0_SELDATAENPOL_MASK - Phy_config_select_interface_control_mask = 0x01, // PHY_CONF0_SELDIPIF_MASK + Phy_config_powerdown_disable = 0x80, // PHY_CONF0_PDZ_MASK + Phy_config_tmds = 0x40, // PHY_CONF0_ENTMDS_MASK + Phy_config_svsret = 0x20, // PHY_CONF0_SVSRET_MASK + Phy_config_gen2_powerdown = 0x10, // PHY_CONF0_GEN2_PDDQ_MASK + Phy_config_gen2_tx_power = 0x08, // PHY_CONF0_GEN2_TXPWRON_MASK + Phy_config_gen2_hotplug_detect_rx_sense = 0x04, // PHY_CONF0_GEN2_ENHPDRXSENSE_MASK + Phy_config_select_data_enable_polarity = 0x02, // PHY_CONF0_SELDATAENPOL_MASK + Phy_config_select_interface_control = 0x01, // PHY_CONF0_SELDIPIF_MASK }; enum Phy_test_bits : unsigned @@ -205,6 +346,7 @@ enum Phy_status_bits : unsigned { + Phy_status_all = 0xf3, Phy_status_rx_sense_all = 0xf0, Phy_status_rx_sense3 = 0x80, // PHY_RX_SENSE3 Phy_status_rx_sense2 = 0x40, // PHY_RX_SENSE2 @@ -212,12 +354,14 @@ Phy_status_rx_sense0 = 0x10, // PHY_RX_SENSE0 Phy_status_hotplug_detect = 0x02, // PHY_HPD Phy_status_tx_phy_lock = 0x01, // PHY_TX_PHY_LOCK + Phy_status_none = 0, }; -// PHY interrupt status and mask bits. +// PHY interrupt status and mask values. enum Phy_int_status_bits : unsigned { + Phy_int_status_all = 0x3f, Phy_int_status_rx_sense_all = 0x3c, Phy_int_status_rx_sense3 = 0x20, // IH_PHY_STAT0_RX_SENSE3 Phy_int_status_rx_sense2 = 0x10, // IH_PHY_STAT0_RX_SENSE2 @@ -225,6 +369,202 @@ Phy_int_status_rx_sense0 = 0x04, // IH_PHY_STAT0_RX_SENSE0 Phy_int_status_tx_phy_lock = 0x02, // IH_PHY_STAT0_TX_PHY_LOCK Phy_int_status_hotplug_detect = 0x01, // IH_PHY_STAT0_HPD + Phy_int_status_none = 0, +}; + +// PHY main register values. + +enum Main_heac_phy_reset_bits : unsigned +{ + Main_heac_phy_reset_assert = 0x01, // MC_HEACPHY_RST_ASSERT +}; + +enum Main_flow_control_bits : unsigned +{ + Main_flow_control_csc_active = 0x01, // MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH + Main_flow_control_csc_inactive = 0x00, // MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS +}; + +enum Main_clock_disable_bits : unsigned +{ + Main_clock_disable_hdcp = 0x40, // MC_CLKDIS_HDCPCLK_DISABLE + Main_clock_disable_cec = 0x20, // MC_CLKDIS_CECCLK_DISABLE + Main_clock_disable_csc = 0x10, // MC_CLKDIS_CSCCLK_DISABLE + Main_clock_disable_audio = 0x08, // MC_CLKDIS_AUDCLK_DISABLE + Main_clock_disable_prep = 0x04, // MC_CLKDIS_PREPCLK_DISABLE + Main_clock_disable_tmds = 0x02, // MC_CLKDIS_TMDSCLK_DISABLE + Main_clock_disable_pixel = 0x01, // MC_CLKDIS_PIXELCLK_DISABLE +}; + +// Frame composer values. + +enum Fc_video_config_bits : unsigned +{ + Fc_video_config_hdcp_keepout_active = 0x80, // FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE + Fc_video_config_hdcp_keepout_inactive = 0x00, // FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE + Fc_video_config_vsync_active_high = 0x40, // FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH + Fc_video_config_vsync_active_low = 0x00, // FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW + Fc_video_config_hsync_active_high = 0x20, // FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH + Fc_video_config_hsync_active_low = 0x00, // FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW + Fc_video_config_data_enable_active_high = 0x10, // FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH + Fc_video_config_data_enable_active_low = 0x00, // FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW + Fc_video_config_hdmi_mode = 0x08, // FC_INVIDCONF_DVI_MODEZ_HDMI_MODE + Fc_video_config_dvi_mode = 0x00, // FC_INVIDCONF_DVI_MODEZ_DVI_MODE + Fc_video_config_osc_active_high = 0x02, // FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH + Fc_video_config_osc_active_low = 0x00, // FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW + Fc_video_config_interlaced = 0x01, // FC_INVIDCONF_IN_I_P_INTERLACED + Fc_video_config_progressive = 0x00, // FC_INVIDCONF_IN_I_P_PROGRESSIVE +}; + +enum Fc_int_status2_bits : unsigned +{ + Fc_int_status2_overflow = 0x03, // FC_STAT2_OVERFLOW_MASK + Fc_int_status2_overflow_low = 0x02, // FC_STAT2_LOW_PRIORITY_OVERFLOW + Fc_int_status2_overflow_high = 0x01 // FC_STAT2_HIGH_PRIORITY_OVERFLOW, +}; + +// Colour space conversion values. + +enum Csc_config_bits : unsigned +{ + Csc_config_interpolation_mask = 0x30, // CSC_CFG_INTMODE_MASK + Csc_config_interpolation_disable = 0x00, // CSC_CFG_INTMODE_DISABLE + Csc_config_interpolation_form1 = 0x10, // CSC_CFG_INTMODE_CHROMA_INT_FORMULA1 + Csc_config_interpolation_form2 = 0x20, // CSC_CFG_INTMODE_CHROMA_INT_FORMULA2 + Csc_config_decimation_mask = 0x3, // CSC_CFG_DECMODE_MASK + Csc_config_decimation_disable = 0x0, // CSC_CFG_DECMODE_DISABLE + Csc_config_decimation_form1 = 0x1, // CSC_CFG_DECMODE_CHROMA_INT_FORMULA1 + Csc_config_decimation_form2 = 0x2, // CSC_CFG_DECMODE_CHROMA_INT_FORMULA2 + Csc_config_decimation_form3 = 0x3, // CSC_CFG_DECMODE_CHROMA_INT_FORMULA3 +}; + +enum Csc_scale_bits : unsigned +{ + Csc_scale_colour_depth_mask = 0xf0, // CSC_SCALE_CSC_COLORDE_PTH_MASK + Csc_scale_colour_depth_24bpp = 0x00, // CSC_SCALE_CSC_COLORDE_PTH_24BPP + Csc_scale_colour_depth_30bpp = 0x50, // CSC_SCALE_CSC_COLORDE_PTH_30BPP + Csc_scale_colour_depth_36bpp = 0x60, // CSC_SCALE_CSC_COLORDE_PTH_36BPP + Csc_scale_colour_depth_48bpp = 0x70, // CSC_SCALE_CSC_COLORDE_PTH_48BPP + Csc_scale_mask = 0x03, // CSC_SCALE_CSCSCALE_MASK +}; + +// HDCP register values. + +enum Hdcp_config0_bits : unsigned +{ + Hdcp_config0_rxdetect_enable = 0x4, // A_HDCPCFG0_RXDETECT_ENABLE +}; + +enum Hdcp_config1_bits : unsigned +{ + Hdcp_config1_encryption_disable = 0x2, // A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE +}; + +enum Hdcp_video_polarity_bits : unsigned +{ + Hdcp_video_polarity_data_enable_active_high = 0x10, // A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH +}; + +// Video sample register values. + +enum Sample_video_config_bits : unsigned +{ + Sample_video_config_data_enable_active = 0x80, // TX_INVID0_INTERNAL_DE_GENERATOR_ENABLE + Sample_video_config_mapping_mask = 0x1f, // TX_INVID0_VIDEO_MAPPING_MASK +}; + +enum Sample_video_stuffing_bits : unsigned +{ + Sample_video_stuffing_bdb_data = 0x04, // TX_INSTUFFING_BDBDATA_STUFFING_ENABLE + Sample_video_stuffing_rcr_data = 0x02, // TX_INSTUFFING_RCRDATA_STUFFING_ENABLE + Sample_video_stuffing_gy_data = 0x01, // TX_INSTUFFING_GYDATA_STUFFING_ENABLE +}; + +// Video packetizer register values. + +enum Packet_stuffing_bits : unsigned +{ + Packet_stuffing_default_phase = 0x20, // VP_STUFF_IDEFAULT_PHASE_MASK + Packet_stuffing_ifix_pp_to_last = 0x10, // VP_STUFF_IFIX_PP_TO_LAST_MASK + Packet_stuffing_icx = 0x08, // VP_STUFF_ICX_GOTO_P0_ST_MASK + Packet_stuffing_ycc422 = 0x04, // VP_STUFF_YCC422_STUFFING_STUFFING_MODE + Packet_stuffing_pp = 0x02, // VP_STUFF_PP_STUFFING_STUFFING_MODE + Packet_stuffing_pr = 0x01, // VP_STUFF_PR_STUFFING_STUFFING_MODE +}; + +enum Packet_config_bits : unsigned +{ + Packet_config_bypass_enable = 0x40, // VP_CONF_BYPASS_EN_ENABLE + Packet_config_pp_enable = 0x20, // VP_CONF_PP_EN_ENABLE + Packet_config_pr_enable = 0x10, // VP_CONF_PR_EN_ENABLE + Packet_config_ycc422_enable = 0x8, // VP_CONF_YCC422_EN_ENABLE + Packet_config_bypass_select_packetizer = 0x4, // VP_CONF_BYPASS_SELECT_VID_PACKETIZER + Packet_config_output_selector_mask = 0x3, // VP_CONF_OUTPUT_SELECTOR_MASK + Packet_config_output_selector_bypass = 0x3, // VP_CONF_OUTPUT_SELECTOR_BYPASS + Packet_config_output_selector_ycc422 = 0x1, // VP_CONF_OUTPUT_SELECTOR_YCC422 + Packet_config_output_selector_pp = 0x0, // VP_CONF_OUTPUT_SELECTOR_PP +}; + +enum Packet_remap_bits : unsigned +{ + Packet_remap_mask = 0x3, // VP_REMAP_MASK + Packet_remap_ycc422_24bit = 0x2, // VP_REMAP_YCC422_24bit + Packet_remap_ycc422_20bit = 0x1, // VP_REMAP_YCC422_20bit + Packet_remap_ycc422_16bit = 0x0, // VP_REMAP_YCC422_16bit +}; + +enum Packet_pixel_repeater_bits : unsigned +{ + Packet_pixel_repeater_depth_mask = 0xf0, // VP_PR_CD_COLOR_DEPTH_MASK + Packet_pixel_repeater_depth_offset = 4, // VP_PR_CD_COLOR_DEPTH_OFFSET + Packet_pixel_repeater_factor_mask = 0x0f, // VP_PR_CD_DESIRED_PR_FACTOR_MASK + Packet_pixel_repeater_factor_offset = 0, // VP_PR_CD_DESIRED_PR_FACTOR_OFFSET +}; + + + +// PHY capabilities. + +static const Phy_capabilities phy_capabilities[] = { + // name gen svsret configure + {Config2_dwc_hdmi_tx_phy, "DWC_HDMI_TX_PHY", 1, false, false}, + {Config2_dwc_mhl_phy_heac, "DWC_MHL_PHY_HEAC", 2, true, true}, + {Config2_dwc_mhl_phy, "DWC_MHL_PHY", 2, true, true}, + {Config2_dwc_hdmi_3d_tx_phy_heac, "DWC_HDMI_3D_TX_PHY_HEAC", 2, false, true}, + {Config2_dwc_hdmi_3d_tx_phy, "DWC_HDMI_3D_TX_PHY", 2, false, true}, + {Config2_dwc_hdmi20_tx_phy, "DWC_HDMI20_TX_PHY", 2, true, true}, + {0, "Vendor PHY", 0, false, false}, + }; + + + +// PHY configuration, adopting the Linux driver's tables of values. + +static const struct Phy_mpll_config phy_mpll_config[] = { + // 8bpc 10bpc 12bpc + // pixelclock cpce gmp cpce gmp cpce gmp + { 45250000, { {0x01e0, 0x0000}, {0x21e1, 0x0000}, {0x41e2, 0x0000} } }, + { 92500000, { {0x0140, 0x0005}, {0x2141, 0x0005}, {0x4142, 0x0005} } }, + { 148500000, { {0x00a0, 0x000a}, {0x20a1, 0x000a}, {0x40a2, 0x000a} } }, + { 216000000, { {0x00a0, 0x000a}, {0x2001, 0x000f}, {0x4002, 0x000f} } }, + { ~0UL, { {0x0000, 0x0000}, {0x0000, 0x0000}, {0x0000, 0x0000} } } +}; + +static const struct Phy_curr_ctrl phy_curr_ctrl[] = { + // pixelclock 8bpc 10bpc 12bpc + { 54000000, {0x091c, 0x091c, 0x06dc} }, + { 58400000, {0x091c, 0x06dc, 0x06dc} }, + { 72000000, {0x06dc, 0x06dc, 0x091c} }, + { 74250000, {0x06dc, 0x0b5c, 0x091c} }, + { 118800000, {0x091c, 0x091c, 0x06dc} }, + { 216000000, {0x06dc, 0x0b5c, 0x091c} }, + { ~0UL, {0x0000, 0x0000, 0x0000} } +}; + +static const struct Phy_config phy_config[] = { + // pixelclock symbol term vlevel + { 216000000, 0x800d, 0x0005, 0x01ad}, + { ~0UL, 0x0000, 0x0000, 0x0000} }; @@ -232,33 +572,114 @@ // Initialise the HDMI peripheral. Hdmi_jz4780_chip::Hdmi_jz4780_chip(l4_addr_t start, l4_addr_t end, - l4_cap_idx_t irq) -: _start(start), _end(end), _irq(irq) + l4_cap_idx_t irq, + struct Jz4740_lcd_panel *panel) +: _start(start), _end(end), _irq(irq), _panel(panel) { // 8-bit registers with 2-bit address shifting. _regs = new Hw::Mmio_register_block<8>(start, 2); + // Initialise I2C state for DDC. + _segment_read = false; _device_register = 0; + // Initialise I2C state for PHY initialisation. + + _phy_device_register = 0; + + // Initialise identifying details and capabilities of the hardware. + get_identification(); + + // Reset interrupts to a minimal, enabled state. + irq_init(); - i2c_init(); - hotplug_init(); + + // Set up DDC and PHY communication. + + i2c_init(I2c_software_reset, I2c_divider, I2c_int_config0, I2c_int_config1, + I2c_int_status, I2c_int_mask); + i2c_init(I2c_phy_software_reset, I2c_phy_divider, I2c_phy_int_config0, I2c_phy_int_config1, + I2c_phy_int_status, I2c_phy_int_mask); + + // Enable PHY interrupts. + + phy_irq_init(); +} + +// Pixel clock frequency calculation. + +unsigned long Hdmi_jz4780_chip::get_pixelclock() +{ + return _pixelclock; + +/* Calculated frequency, which may not be the actual pixelclock frequency... + + return (_panel->line_start + _panel->width + _panel->line_end + _panel->hsync) * + (_panel->frame_start + _panel->height + _panel->frame_end + _panel->vsync) * + _panel->frame_rate; +*/ } + + +// Update a register by enabling/setting or disabling/clearing the given bits. + +void Hdmi_jz4780_chip::reg_update(uint32_t reg, uint32_t bits, bool enable) +{ + if (enable) + _regs[reg] = _regs[reg] | bits; + else + _regs[reg] = _regs[reg] & ~bits; +} + +// Update a field. The bits must be shifted to coincide with the mask. + +void Hdmi_jz4780_chip::reg_update_field(uint32_t reg, uint32_t mask, uint32_t bits) +{ + _regs[reg] = (_regs[reg] & ~(mask)) | (bits & mask); +} + +void Hdmi_jz4780_chip::reg_fill_field(uint32_t reg, uint32_t mask) +{ + _regs[reg] = _regs[reg] | mask; +} + + + +// Chipset querying. + void Hdmi_jz4780_chip::get_identification() { _version = (_regs[Design_id] << 8) | _regs[Revision_id]; + _phy_type = _regs[Config_id2]; + + // Initialise a member to any matching capabilities or leave it as the "null" + // entry. + + _phy_def = phy_capabilities; + + while (_phy_def->gen && (_phy_def->type != _phy_type)) + _phy_def++; } void Hdmi_jz4780_chip::get_version(uint8_t *major, uint16_t *minor) { - *major = _version >> 12; + *major = (_version >> 12) & 0xfff; *minor = _version & 0xfff; } +void Hdmi_jz4780_chip::get_phy_capabilities(const struct Phy_capabilities **phy_def) +{ + *phy_def = _phy_def; +} + + + +// Initialisation. + void Hdmi_jz4780_chip::irq_init() { // Disable interrupts. @@ -273,9 +694,9 @@ _regs[As_int_mask] = 0xff; _regs[Phy_int_mask] = 0xff; _regs[I2c_int_mask] = 0xff; + _regs[I2c_phy_int_mask] = 0xff; _regs[Cec_int_mask] = 0xff; _regs[Vp_int_mask] = 0xff; - _regs[I2c_phy_int_mask] = 0xff; _regs[Ahb_dma_audio_int_mask] = 0xff; // Enable interrupts. @@ -283,35 +704,53 @@ _regs[Int_mask] = _regs[Int_mask] & ~(Int_mask_wakeup | Int_mask_all); } -void Hdmi_jz4780_chip::i2c_init() +void Hdmi_jz4780_chip::phy_irq_init() { // Set PHY interrupt polarities. - _regs[I2c_phy_int_config0] = I2c_int_config0_done_polarity; - _regs[I2c_phy_int_config1] = I2c_int_config1_nack_polarity | - I2c_int_config1_arb_polarity; + _regs[Phy_polarity] = Phy_status_all; + + // Enable/unmask second-level interrupts. + + _regs[Phy_mask] = _regs[Phy_mask] & ~(Phy_status_all); + + // Clear pending interrupts. + + _regs[Phy_int_status] = Phy_int_status_all; + + // Enable/unmask interrupts. + _regs[Phy_int_mask] = _regs[Phy_int_mask] & ~(Phy_int_status_all); +} + + + +// I2C support. + +void Hdmi_jz4780_chip::i2c_init(uint32_t reset, uint32_t divider, + uint32_t config0, uint32_t config1, + uint32_t status, uint32_t mask) +{ // Software reset. - _regs[I2c_software_reset] = 0; + _regs[reset] = 0; // Standard mode (100kHz). - _regs[I2c_divider] = 0; + _regs[divider] = 0; // Set interrupt polarities. - _regs[I2c_int_config0] = I2c_int_config0_done_polarity; - _regs[I2c_int_config1] = I2c_int_config1_nack_polarity | - I2c_int_config1_arb_polarity; + _regs[config0] = I2c_int_config0_done_polarity; + _regs[config1] = I2c_int_config1_nack_polarity | I2c_int_config1_arb_polarity; // Clear and mask/mute interrupts. - _regs[I2c_int_status] = I2c_int_status_done | I2c_int_status_error; - _regs[I2c_int_mask] = I2c_int_status_done | I2c_int_status_error; + _regs[status] = I2c_int_status_done | I2c_int_status_error; + _regs[mask] = I2c_int_status_done | I2c_int_status_error; } -long Hdmi_jz4780_chip::i2c_wait() +long Hdmi_jz4780_chip::i2c_wait(uint32_t status) { long err; uint8_t int_status; @@ -325,7 +764,7 @@ if (err) return err; - int_status = _regs[I2c_int_status]; + int_status = _regs[status]; // Test for an error condition. @@ -334,7 +773,7 @@ // Acknowledge the interrupt. - _regs[I2c_int_status] = int_status; + _regs[status] = int_status; } while (!(int_status & I2c_int_status_done)); @@ -360,7 +799,7 @@ // Wait and then read. - err = i2c_wait(); + err = i2c_wait(I2c_int_status); if (err) break; @@ -374,6 +813,45 @@ return i; } +int Hdmi_jz4780_chip::i2c_phy_write(uint8_t address, uint16_t value) +{ + i2c_phy_set_address(address); + return i2c_phy_write(&value, 1); +} + +int Hdmi_jz4780_chip::i2c_phy_write(uint16_t *buf, unsigned int length) +{ + unsigned int i; + long err; + + // Unmask interrupts. + + _regs[I2c_phy_int_mask] = 0; + + for (i = 0; i < length; i++) + { + // Increment the device register. + + _regs[I2c_phy_register] = _device_register++; + _regs[I2c_phy_operation] = I2c_operation_write; + + // Write and then wait. + + _regs[I2c_phy_data_out1] = (buf[i] >> 8) & 0xff; + _regs[I2c_phy_data_out0] = buf[i] & 0xff; + + err = i2c_wait(I2c_phy_int_status); + if (err) + break; + } + + // Mask interrupts again. + + _regs[I2c_phy_int_mask] = I2c_int_status_done | I2c_int_status_error; + + return i; +} + void Hdmi_jz4780_chip::i2c_set_address(uint8_t address) { _regs[I2c_device_address] = address; @@ -381,6 +859,18 @@ i2c_set_register(0); } +void Hdmi_jz4780_chip::i2c_phy_set_address(uint8_t address) +{ + // The Linux drivers seem to set the clear field when changing the PHY device + // address, presumably because some manual says so. + + _regs[Phy_test0] = _regs[Phy_test0] | Phy_test0_clear_mask; + _regs[I2c_phy_device_address] = address; + _regs[Phy_test0] = _regs[Phy_test0] & ~Phy_test0_clear_mask; + + i2c_phy_set_register(0); +} + void Hdmi_jz4780_chip::i2c_set_segment(uint8_t segment) { _regs[I2c_segment_address] = 0x30; @@ -394,25 +884,197 @@ _device_register = device_register; } -void Hdmi_jz4780_chip::hotplug_init() +void Hdmi_jz4780_chip::i2c_phy_set_register(uint8_t device_register) +{ + _phy_device_register = device_register; +} + + + +// PHY operations. + +void Hdmi_jz4780_chip::phy_enable_powerdown(bool enable) +{ + reg_update(Phy_config, Phy_config_powerdown_disable, !enable); +} + +void Hdmi_jz4780_chip::phy_enable_tmds(bool enable) +{ + reg_update(Phy_config, Phy_config_tmds, enable); +} + +void Hdmi_jz4780_chip::phy_enable_svsret(bool enable) { - // Set PHY interrupt polarities. + reg_update(Phy_config, Phy_config_svsret, enable); +} + +void Hdmi_jz4780_chip::phy_enable_gen2_powerdown(bool enable) +{ + reg_update(Phy_config, Phy_config_gen2_powerdown, enable); +} + +void Hdmi_jz4780_chip::phy_enable_gen2_tx_power(bool enable) +{ + reg_update(Phy_config, Phy_config_gen2_tx_power, enable); +} + +void Hdmi_jz4780_chip::phy_enable_interface(bool enable) +{ + reg_update(Phy_config, Phy_config_select_data_enable_polarity, enable); + reg_update(Phy_config, Phy_config_select_interface_control, !enable); +} + +// Configure the PHY. Various things not supported by the JZ4780 PHY are ignored +// such as the TDMS clock ratio (dependent on HDMI 2 and content scrambling). + +long Hdmi_jz4780_chip::phy_configure() +{ + long err; - _regs[Phy_polarity] = Phy_status_hotplug_detect | Phy_status_rx_sense_all; + phy_power_off(); + + if (_phy_def->svsret) + phy_enable_svsret(true); + + phy_reset(); + + _regs[Main_heac_phy_reset] = Main_heac_phy_reset_assert; + + i2c_phy_set_address(I2c_phy_device_phy_gen2); + + if (_phy_def->configure) + { + err = phy_configure_specific(); + if (err) + return err; + } + + // NOTE: TMDS clock delay here in Linux driver. + + phy_power_on(); - // Enable/unmask second-level interrupts. + return L4_EOK; +} + +// Configure for the JZ4780 specifically. + +long Hdmi_jz4780_chip::phy_configure_specific() +{ + const struct Phy_mpll_config *m = phy_mpll_config; + const struct Phy_curr_ctrl *c = phy_curr_ctrl; + const struct Phy_config *p = phy_config; + unsigned long pixelclock = get_pixelclock(); + + // Find MPLL, CURR_CTRL and PHY configuration settings appropriate for the + // pixel clock frequency. + + while (m->pixelclock && (pixelclock > m->pixelclock)) + m++; + + while (c->pixelclock && (pixelclock > c->pixelclock)) + c++; + + while (p->pixelclock && (pixelclock > p->pixelclock)) + p++; + + printf("MPLL for %ld; CURR_CTRL for %ld; PHY for %ld\n", m->pixelclock, c->pixelclock, p->pixelclock); - _regs[Phy_mask] = _regs[Phy_mask] & ~(Phy_status_hotplug_detect | Phy_status_rx_sense_all); + if (!m->pixelclock || !c->pixelclock || !p->pixelclock) + return -L4_EINVAL; + + // Using values for 8bpc from the tables. + + // Initialise MPLL. + + i2c_phy_write(I2c_phy_3d_tx_cpce_ctrl, m->res[Phy_resolution_8bpc].cpce); + i2c_phy_write(I2c_phy_3d_tx_gmp_ctrl, m->res[Phy_resolution_8bpc].gmp); + + // Initialise CURRCTRL. + + i2c_phy_write(I2c_phy_3d_tx_cpce_ctrl, c->curr[Phy_resolution_8bpc]); + + // Initialise PHY_CONFIG. + + i2c_phy_write(I2c_phy_3d_tx_pll_phby_ctrl, 0); + i2c_phy_write(I2c_phy_3d_tx_msm_ctrl, Msm_ctrl_clock_output_select_fb); + + i2c_phy_write(I2c_phy_3d_tx_term, p->term); + i2c_phy_write(I2c_phy_3d_tx_clock_symbol_ctrl, p->symbol); + i2c_phy_write(I2c_phy_3d_tx_vlevel_ctrl, p->vlevel); - // Clear pending interrupts. + // Override and disable clock termination. + + i2c_phy_write(I2c_phy_3d_tx_clock_cal_ctrl, Clock_cal_ctrl_override); + + return L4_EOK; +} + +long Hdmi_jz4780_chip::phy_init() +{ + printf("phy_init...\n"); + + long err; + int i; + + // Initialisation repeated for HDMI PHY specification reasons. + + for (i = 0; i < 2; i++) + { + phy_enable_interface(true); + err = phy_configure(); + if (err) + return err; + } - _regs[Phy_int_status] = Phy_int_status_hotplug_detect | Phy_int_status_rx_sense_all; + return L4_EOK; +} + +void Hdmi_jz4780_chip::phy_reset() +{ + _regs[Main_reset] = 1; + _regs[Main_reset] = 0; +} + +void Hdmi_jz4780_chip::phy_power_off() +{ + printf("phy_power_off...\n"); + + if (_phy_def && (_phy_def->gen == 1)) + { + phy_enable_tmds(false); + phy_enable_powerdown(true); + return; + } + + phy_enable_gen2_tx_power(false); + + wait_for_tx_phy_lock(0); - // Enable/unmask interrupts. + phy_enable_gen2_powerdown(true); +} + +void Hdmi_jz4780_chip::phy_power_on() +{ + printf("phy_power_on...\n"); - _regs[Phy_int_mask] = _regs[Phy_int_mask] & ~(Phy_int_status_hotplug_detect | Phy_int_status_rx_sense_all); + if (_phy_def && (_phy_def->gen == 1)) + { + phy_enable_powerdown(false); + phy_enable_tmds(false); + phy_enable_tmds(true); + return; + } + + phy_enable_gen2_tx_power(true); + phy_enable_gen2_powerdown(false); + + wait_for_tx_phy_lock(1); } + + +// Hotplug detection. + bool Hdmi_jz4780_chip::connected() { return (_regs[Phy_status] & Phy_status_hotplug_detect) != 0; @@ -420,8 +1082,19 @@ long Hdmi_jz4780_chip::wait_for_connection() { + return wait_for_phy_irq(Phy_int_status_hotplug_detect, Phy_status_hotplug_detect, + Phy_status_hotplug_detect); +} + +// General PHY interrupt handling. + +long Hdmi_jz4780_chip::wait_for_phy_irq(uint32_t int_status_flags, + uint32_t status_flags, + uint32_t status_values) +{ long err; - uint8_t int_status, polarity; + uint8_t int_status, status; + uint8_t status_unchanged = ~(status_values) & status_flags; l4_msgtag_t tag; do @@ -435,27 +1108,310 @@ // Obtain the details. int_status = _regs[Phy_int_status]; - polarity = _regs[Phy_polarity]; + status = _regs[Phy_status]; // Acknowledge the interrupt. - _regs[Phy_int_status] = int_status; + _regs[Phy_int_status] = int_status_flags; + + // Continue without a handled event. + // An event is handled when detected and when the status differs from + // the unchanged state. + + printf("Status: %x versus %x\n", status & status_flags, status_unchanged); + + } while (!((int_status & int_status_flags) && + ((status & status_flags) ^ status_unchanged))); + + return L4_EOK; +} + +// Wait for TX_PHY_LOCK to become high or low. + +long Hdmi_jz4780_chip::wait_for_tx_phy_lock(int level) +{ + if (!!(_regs[Phy_status] & Phy_status_tx_phy_lock) == level) + return L4_EOK; + + return wait_for_phy_irq(Phy_int_status_tx_phy_lock, Phy_status_tx_phy_lock, + level ? Phy_status_tx_phy_lock : Phy_status_none); +} + + + +// Output setup operations. + +long Hdmi_jz4780_chip::enable(unsigned long pixelclock) +{ + _pixelclock = pixelclock; + + // Disable frame composer overflow interrupts. + + enable_overflow_irq(false); - // Continue without a hotplug event indicating connection. + // NOTE: Here, CEA modes are normally detected and thus the output encoding. + // NOTE: Instead, a fixed RGB output encoding and format is used. + // NOTE: Meanwhile, the input encoding and format will also be fixed to a RGB + // NOTE: representation. + + // _bits_per_channel = 8; + // _data_enable_polarity = true; + + // HDMI initialisation "step B.1": video frame initialisation. + + frame_init(); + + // HDMI initialisation "step B.2": PHY initialisation. + + long err = phy_init(); + if (err) + return err; - } while (!((int_status & Phy_int_status_hotplug_detect) && - (polarity & Phy_status_hotplug_detect))); + // HDMI initialisation "step B.3": video signal initialisation. + + data_path_init(); + + // With audio, various clock updates are needed. + + // NOTE: DVI mode is being assumed for now, for simplicity. + + // In non-DVI mode, the AVI, vendor-specific infoframe and regular infoframe + // are set up. + + packet_init(); + csc_init(); + sample_init(); + hdcp_init(); + + // Enable frame composer overflow interrupts. + + enable_overflow_irq(true); return L4_EOK; } +void Hdmi_jz4780_chip::enable_overflow_irq(bool enable) +{ + reg_update(Fc_int_mask2, Fc_int_status2_overflow, !enable); +} + +void Hdmi_jz4780_chip::frame_init() +{ + printf("frame_init...\n"); + + // Initialise the video configuration. This is rather like the initialisation + // of the LCD controller. The sync and data enable polarities are set up, plus + // extras like HDCP, DVI mode, progressive/interlace. + // NOTE: Here, the JZ4740-specific configuration is used to store the picture + // NOTE: properties, but a neutral structure should be adopted. + + uint8_t config = 0; + + config |= (_panel->config & Jz4740_lcd_hsync_negative) + ? Fc_video_config_hsync_active_low + : Fc_video_config_hsync_active_high; + + config |= (_panel->config & Jz4740_lcd_vsync_negative) + ? Fc_video_config_vsync_active_low + : Fc_video_config_vsync_active_high; + + config |= (_panel->config & Jz4740_lcd_de_negative) + ? Fc_video_config_data_enable_active_low + : Fc_video_config_data_enable_active_high; + + // NOTE: Only supporting DVI mode so far. + + config |= Fc_video_config_dvi_mode; + + // NOTE: Not supporting HDCP. + + config |= Fc_video_config_hdcp_keepout_inactive; + + // NOTE: Only supporting progressive scan so far. + + config |= Fc_video_config_progressive; + config |= Fc_video_config_osc_active_low; + + _regs[Fc_video_config] = config; + + printf("Fc_video_config (%x) = %x\n", Fc_video_config, (uint8_t) _regs[Fc_video_config]); + + // Then, the frame characteristics (visible area, sync pulse) are set. Indeed, + // the frame area details should be practically the same as those used by the + // LCD controller. + + uint16_t hblank = _panel->line_start + _panel->line_end + _panel->hsync, + vblank = _panel->frame_start + _panel->frame_end + _panel->vsync, + hsync_delay = _panel->line_end, + vsync_delay = _panel->frame_end, + hsync_width = _panel->hsync, + vsync_height = _panel->vsync; + + _regs[Fc_horizontal_active_width1] = (_panel->width >> 8) & 0xff; + _regs[Fc_horizontal_active_width0] = _panel->width & 0xff; + + _regs[Fc_horizontal_blank_width1] = (hblank >> 8) & 0xff; + _regs[Fc_horizontal_blank_width0] = hblank & 0xff; + + _regs[Fc_vertical_active_height1] = (_panel->height >> 8) & 0xff; + _regs[Fc_vertical_active_height0] = _panel->height & 0xff; + + _regs[Fc_vertical_blank_height] = vblank & 0xff; + + _regs[Fc_hsync_delay1] = (hsync_delay >> 8) & 0xff; + _regs[Fc_hsync_delay0] = hsync_delay & 0xff; + + _regs[Fc_vsync_delay] = vsync_delay & 0xff; + + _regs[Fc_hsync_width1] = (hsync_width >> 8) & 0xff; + _regs[Fc_hsync_width0] = hsync_width & 0xff; + + _regs[Fc_vsync_height] = vsync_height & 0xff; +} + +void Hdmi_jz4780_chip::data_path_init() +{ + printf("data_path_init...\n"); + + // Initialise the path of the video data. Here, the elements of the data + // stream are defined such as the control period duration, data channel + // characteristics, pixel and TMDS clocks, and the involvement of colour space + // conversion. + + // Control period minimum duration. + + _regs[Fc_control_duration] = 12; + _regs[Fc_ex_control_duration] = 32; + _regs[Fc_ex_control_space] = 1; + + // Set to fill TMDS data channels. + + _regs[Fc_channel0_preamble] = 0x0b; + _regs[Fc_channel1_preamble] = 0x16; + _regs[Fc_channel2_preamble] = 0x21; + + // Apparent two-stage clock activation. + + uint8_t clock_disable = Main_clock_disable_hdcp | + Main_clock_disable_csc | + Main_clock_disable_audio | + Main_clock_disable_prep | + Main_clock_disable_tmds; + + // Activate the pixel clock. + + _regs[Main_clock_disable] = clock_disable; + + // Then activate the TMDS clock. + + clock_disable &= ~(Main_clock_disable_tmds); + _regs[Main_clock_disable] = clock_disable; + + // NOTE: Bypass colour space conversion for now. + + _regs[Main_flow_control] = Main_flow_control_csc_inactive; +} + +void Hdmi_jz4780_chip::packet_init() +{ + printf("packet_init...\n"); + + // Initialise the video packet details. + // NOTE: With 24bpp RGB output only for now, no pixel repetition. + + int colour_depth = 4; + + _regs[Packet_pixel_repeater] = + ((colour_depth << Packet_pixel_repeater_depth_offset) & + Packet_pixel_repeater_depth_mask); + + _regs[Packet_remap] = Packet_remap_ycc422_16bit; + + reg_fill_field(Packet_stuffing, Packet_stuffing_pr | + Packet_stuffing_default_phase | + Packet_stuffing_pp | + Packet_stuffing_ycc422); + + // Disable pixel repeater. + + reg_update_field(Packet_config, Packet_config_pr_enable | + Packet_config_bypass_select_packetizer | + Packet_config_bypass_enable | + Packet_config_pp_enable | + Packet_config_ycc422_enable | + Packet_config_output_selector_mask, + Packet_config_bypass_select_packetizer | + Packet_config_bypass_enable | + Packet_config_output_selector_bypass); +} + +void Hdmi_jz4780_chip::csc_init() +{ + printf("csc_init...\n"); + + // Initialise the colour space conversion details. + // NOTE: No conversion will be done yet (see data_path_init). + + _regs[Csc_config] = Csc_config_interpolation_disable | + Csc_config_decimation_disable; + + // NOTE: Use 8bpc (24bpp) for now. + + reg_update_field(Csc_scale, Csc_scale_colour_depth_mask, Csc_scale_colour_depth_24bpp); + + // NOTE: Coefficients should be set here. +} + +void Hdmi_jz4780_chip::sample_init() +{ + printf("sample_init...\n"); + + // Initialise the mapping of video input data. + // NOTE: With 24bpp RGB input only for now. + + int colour_format = 0x01; + + // Data enable inactive. + + _regs[Sample_video_config] = (colour_format & Sample_video_config_mapping_mask); + + // Transmission stuffing when data enable is inactive. + + _regs[Sample_video_stuffing] = Sample_video_stuffing_bdb_data | + Sample_video_stuffing_rcr_data | + Sample_video_stuffing_gy_data; + + _regs[Sample_gy_data0] = 0; + _regs[Sample_gy_data1] = 0; + _regs[Sample_rcr_data0] = 0; + _regs[Sample_rcr_data1] = 0; + _regs[Sample_bcb_data0] = 0; + _regs[Sample_bcb_data1] = 0; +} + +void Hdmi_jz4780_chip::hdcp_init() +{ + printf("hdcp_init...\n"); + + // Initialise HDCP registers, mostly turning things off. + + reg_update(Hdcp_config0, Hdcp_config0_rxdetect_enable, false); + + reg_update(Hdcp_video_polarity, + Hdcp_video_polarity_data_enable_active_high, + !(_panel->config & Jz4740_lcd_de_negative)); + + reg_update(Hdcp_config1, Hdcp_config1_encryption_disable, true); +} + // C language interface functions. -void *jz4780_hdmi_init(l4_addr_t start, l4_addr_t end, l4_cap_idx_t irq) +void *jz4780_hdmi_init(l4_addr_t start, l4_addr_t end, l4_cap_idx_t irq, + struct Jz4740_lcd_panel *panel) { - return (void *) new Hdmi_jz4780_chip(start, end, irq); + return (void *) new Hdmi_jz4780_chip(start, end, irq, panel); } void jz4780_hdmi_get_version(void *hdmi, uint8_t *major, uint16_t *minor) @@ -463,6 +1419,11 @@ static_cast(hdmi)->get_version(major, minor); } +void jz4780_hdmi_get_phy_capabilities(void *hdmi, const struct Phy_capabilities **phy_def) +{ + static_cast(hdmi)->get_phy_capabilities(phy_def); +} + int jz4780_hdmi_i2c_read(void *hdmi, uint8_t *buf, unsigned int length) { return static_cast(hdmi)->i2c_read(buf, length); @@ -492,3 +1453,8 @@ { return static_cast(hdmi)->wait_for_connection(); } + +long jz4780_hdmi_enable(void *hdmi, unsigned long pixelclock) +{ + return static_cast(hdmi)->enable(pixelclock); +}