# HG changeset patch # User Paul Boddie # Date 1695048015 -7200 # Node ID 0de8477d181b94dd4a0c2a2969620abd2b59d452 # Parent eb796e0d2f904d1092f999f43bf26e5c8a0fb35c Reformatted, tidied up whitespace. diff -r eb796e0d2f90 -r 0de8477d181b pkg/devices/lib/cpm/src/x1600.cc --- a/pkg/devices/lib/cpm/src/x1600.cc Mon Sep 18 02:21:50 2023 +0200 +++ b/pkg/devices/lib/cpm/src/x1600.cc Mon Sep 18 16:40:15 2023 +0200 @@ -255,125 +255,126 @@ // Note the use of extra parentheses due to the annoying C++ "most vexing parse" // problem. See: https://en.wikipedia.org/wiki/Most_vexing_parse -static Clock clock_ahb2_apb(Source(mux_core, Clock_source_hclock2)), +static Clock clock_ahb2_apb(Source(mux_core, Clock_source_hclock2)), + + clock_dma((Source(mux_pclock)), (Control(Clock_gate_dma))), + + clock_i2c((Source(mux_pclock)), (Control(Clock_gate_i2c0))), + + clock_i2c0((Source(mux_pclock)), (Control(Clock_gate_i2c0))), + + clock_i2c1((Source(mux_pclock)), (Control(Clock_gate_i2c1))), + + clock_main(Source(mux_core, Clock_source_main), Control(Clock_gate_main)), + + clock_timer((Source(mux_pclock)), (Control(Clock_gate_timer))), + + clock_uart0((Source(mux_external)), (Control(Clock_gate_uart0))), + + clock_uart1((Source(mux_external)), (Control(Clock_gate_uart1))), + + clock_uart2((Source(mux_external)), (Control(Clock_gate_uart2))), + + clock_uart3((Source(mux_external)), (Control(Clock_gate_uart3))); + +static Clock_divided + clock_can0(Source(mux_bus, Clock_source_can0), + Control(Clock_gate_can0, Clock_change_enable_can0, Clock_busy_can0), + Divider(Clock_divider_can0)), + + clock_can1(Source(mux_bus, Clock_source_can1), + Control(Clock_gate_can1, Clock_change_enable_can1, Clock_busy_can1), + Divider(Clock_divider_can1)), + + clock_cdbus(Source(mux_dev, Clock_source_cdbus), + Control(Clock_gate_cdbus, Clock_change_enable_cdbus, Clock_busy_cdbus), + Divider(Clock_divider_cdbus)), + + clock_cim(Source(mux_dev, Clock_source_cim), + Control(Clock_gate_cim, Clock_change_enable_cim, Clock_busy_cim), + Divider(Clock_divider_cim)), + + clock_cpu(Source(mux_core, Clock_source_cpu), + Control(Field::undefined, Clock_change_enable_cpu, Clock_busy_cpu), + Divider(Clock_divider_cpu)), + + clock_ddr(Source(mux_core, Clock_source_ddr), + Control(Clock_gate_ddr, Clock_change_enable_ddr, Clock_busy_ddr), + Divider(Clock_divider_ddr)), + + clock_hclock0(Source(mux_core, Clock_source_hclock0), + Control(Clock_gate_ahb0, Clock_change_enable_ahb0), + Divider(Clock_divider_hclock0)), + + clock_hclock2(Source(mux_ahb2_apb), + Control(Clock_gate_apb0, Clock_change_enable_ahb2), + Divider(Clock_divider_hclock2)), + + clock_lcd_pixel(Source(mux_dev, Clock_source_lcd), + Control(Clock_gate_lcd_pixel, Clock_change_enable_lcd, Clock_busy_lcd), + Divider(Clock_divider_lcd)), - clock_dma((Source(mux_pclock)), (Control(Clock_gate_dma))), - - clock_i2c((Source(mux_pclock)), (Control(Clock_gate_i2c0))), - - clock_i2c0((Source(mux_pclock)), (Control(Clock_gate_i2c0))), - - clock_i2c1((Source(mux_pclock)), (Control(Clock_gate_i2c1))), - - clock_main(Source(mux_core, Clock_source_main), - Control(Clock_gate_main)), - - clock_timer((Source(mux_pclock)), (Control(Clock_gate_timer))), - - clock_uart0((Source(mux_external)), (Control(Clock_gate_uart0))), - - clock_uart1((Source(mux_external)), (Control(Clock_gate_uart1))), - - clock_uart2((Source(mux_external)), (Control(Clock_gate_uart2))), - - clock_uart3((Source(mux_external)), (Control(Clock_gate_uart3))); - -static Clock_divided clock_can0(Source(mux_bus, Clock_source_can0), - Control(Clock_gate_can0, Clock_change_enable_can0, Clock_busy_can0), - Divider(Clock_divider_can0)), - - clock_can1(Source(mux_bus, Clock_source_can1), - Control(Clock_gate_can1, Clock_change_enable_can1, Clock_busy_can1), - Divider(Clock_divider_can1)), - - clock_cdbus(Source(mux_dev, Clock_source_cdbus), - Control(Clock_gate_cdbus, Clock_change_enable_cdbus, Clock_busy_cdbus), - Divider(Clock_divider_cdbus)), - - clock_cim(Source(mux_dev, Clock_source_cim), - Control(Clock_gate_cim, Clock_change_enable_cim, Clock_busy_cim), - Divider(Clock_divider_cim)), - - clock_cpu(Source(mux_core, Clock_source_cpu), - Control(Field::undefined, Clock_change_enable_cpu, Clock_busy_cpu), - Divider(Clock_divider_cpu)), - - clock_ddr(Source(mux_core, Clock_source_ddr), - Control(Clock_gate_ddr, Clock_change_enable_ddr, Clock_busy_ddr), - Divider(Clock_divider_ddr)), - - clock_hclock0(Source(mux_core, Clock_source_hclock0), - Control(Clock_gate_ahb0, Clock_change_enable_ahb0), - Divider(Clock_divider_hclock0)), - - clock_hclock2(Source(mux_ahb2_apb), - Control(Clock_gate_apb0, Clock_change_enable_ahb2), - Divider(Clock_divider_hclock2)), - - clock_lcd_pixel(Source(mux_dev, Clock_source_lcd), - Control(Clock_gate_lcd_pixel, Clock_change_enable_lcd, Clock_busy_lcd), - Divider(Clock_divider_lcd)), - - clock_mac(Source(mux_dev, Clock_source_mac), - Control(Clock_gate_gmac0, Clock_change_enable_mac, Clock_busy_mac), - Divider(Clock_divider_mac)), - - clock_msc(Source(mux_dev, Clock_source_msc0), - Control(Clock_gate_msc0, Clock_change_enable_msc0, Clock_busy_msc0), - Divider(Clock_divider_msc0)), - - clock_msc0(Source(mux_dev, Clock_source_msc0), - Control(Clock_gate_msc0, Clock_change_enable_msc0, Clock_busy_msc0), - Divider(Clock_divider_msc0)), - - clock_msc1(Source(mux_dev, Clock_source_msc1), - Control(Clock_gate_msc1, Clock_change_enable_msc1, Clock_busy_msc1), - Divider(Clock_divider_msc1)), - - clock_pclock((Source(mux_ahb2_apb)), - (Control(Clock_gate_apb0)), - (Divider(Clock_divider_pclock))), - - clock_pwm(Source(mux_dev, Clock_source_pwm), - Control(Clock_gate_pwm, Clock_change_enable_pwm, Clock_busy_pwm), - Divider(Clock_divider_pwm)), - - clock_pwm0(Source(mux_dev, Clock_source_pwm), - Control(Clock_gate_pwm, Clock_change_enable_pwm, Clock_busy_pwm), - Divider(Clock_divider_pwm)), - - clock_sfc(Source(mux_dev, Clock_source_sfc), - Control(Clock_gate_sfc, Clock_change_enable_sfc, Clock_busy_sfc), - Divider(Clock_divider_sfc)), - - clock_ssi(Source(mux_dev, Clock_source_ssi), - Control(Clock_gate_ssi0, Clock_change_enable_ssi, Clock_busy_ssi), - Divider(Clock_divider_ssi)); - -static Clock_divided_i2s clock_i2s0_rx(Source(mux_i2s, Clock_source_i2s), - Control(Clock_gate_i2s0_rx, Clock_change_enable_i2s), - Divider_i2s(Clock_divider_i2s0_m, Clock_divider_i2s0_n, - Clock_divider_i2s0_d)), + clock_mac(Source(mux_dev, Clock_source_mac), + Control(Clock_gate_gmac0, Clock_change_enable_mac, Clock_busy_mac), + Divider(Clock_divider_mac)), + + clock_msc(Source(mux_dev, Clock_source_msc0), + Control(Clock_gate_msc0, Clock_change_enable_msc0, Clock_busy_msc0), + Divider(Clock_divider_msc0)), + + clock_msc0(Source(mux_dev, Clock_source_msc0), + Control(Clock_gate_msc0, Clock_change_enable_msc0, Clock_busy_msc0), + Divider(Clock_divider_msc0)), + + clock_msc1(Source(mux_dev, Clock_source_msc1), + Control(Clock_gate_msc1, Clock_change_enable_msc1, Clock_busy_msc1), + Divider(Clock_divider_msc1)), + + clock_pclock((Source(mux_ahb2_apb)), + (Control(Clock_gate_apb0)), + (Divider(Clock_divider_pclock))), + + clock_pwm(Source(mux_dev, Clock_source_pwm), + Control(Clock_gate_pwm, Clock_change_enable_pwm, Clock_busy_pwm), + Divider(Clock_divider_pwm)), + + clock_pwm0(Source(mux_dev, Clock_source_pwm), + Control(Clock_gate_pwm, Clock_change_enable_pwm, Clock_busy_pwm), + Divider(Clock_divider_pwm)), - clock_i2s0_tx(Source(mux_i2s, Clock_source_i2s), - Control(Clock_gate_i2s0_tx, Clock_change_enable_i2s), - Divider_i2s(Clock_divider_i2s1_m, Clock_divider_i2s1_n, - Clock_divider_i2s1_d)); + clock_sfc(Source(mux_dev, Clock_source_sfc), + Control(Clock_gate_sfc, Clock_change_enable_sfc, Clock_busy_sfc), + Divider(Clock_divider_sfc)), -static Pll clock_pll_A(Source(mux_external), - Control_pll(Pll_enable_A, Pll_stable_A, Pll_bypass_A), - Divider_pll(Pll_multiplier_A, Pll_input_division_A, - Pll_output_division0_A, Pll_output_division1_A)), + clock_ssi(Source(mux_dev, Clock_source_ssi), + Control(Clock_gate_ssi0, Clock_change_enable_ssi, Clock_busy_ssi), + Divider(Clock_divider_ssi)); + +static Clock_divided_i2s + clock_i2s0_rx(Source(mux_i2s, Clock_source_i2s), + Control(Clock_gate_i2s0_rx, Clock_change_enable_i2s), + Divider_i2s(Clock_divider_i2s0_m, Clock_divider_i2s0_n, + Clock_divider_i2s0_d)), - clock_pll_E(Source(mux_external), - Control_pll(Pll_enable_E, Pll_stable_E, Pll_bypass_E), - Divider_pll(Pll_multiplier_E, Pll_input_division_E, - Pll_output_division0_E, Pll_output_division1_E)), + clock_i2s0_tx(Source(mux_i2s, Clock_source_i2s), + Control(Clock_gate_i2s0_tx, Clock_change_enable_i2s), + Divider_i2s(Clock_divider_i2s1_m, Clock_divider_i2s1_n, + Clock_divider_i2s1_d)); + +static Pll clock_pll_A(Source(mux_external), + Control_pll(Pll_enable_A, Pll_stable_A, Pll_bypass_A), + Divider_pll(Pll_multiplier_A, Pll_input_division_A, + Pll_output_division0_A, Pll_output_division1_A)), - clock_pll_M(Source(mux_external), - Control_pll(Pll_enable_M, Pll_stable_M, Pll_bypass_M), - Divider_pll(Pll_multiplier_M, Pll_input_division_M, - Pll_output_division0_M, Pll_output_division1_M)); + clock_pll_E(Source(mux_external), + Control_pll(Pll_enable_E, Pll_stable_E, Pll_bypass_E), + Divider_pll(Pll_multiplier_E, Pll_input_division_E, + Pll_output_division0_E, Pll_output_division1_E)), + + clock_pll_M(Source(mux_external), + Control_pll(Pll_enable_M, Pll_stable_M, Pll_bypass_M), + Divider_pll(Pll_multiplier_M, Pll_input_division_M, + Pll_output_division0_M, Pll_output_division1_M)); @@ -601,31 +602,31 @@ int x1600_cpm_get_parameters(void *cpm, enum Clock_identifiers clock, uint32_t parameters[]) -{ +{ return static_cast(cpm)->get_parameters(clock, parameters); } void x1600_cpm_set_parameters(void *cpm, enum Clock_identifiers clock, uint32_t parameters[]) -{ +{ return static_cast(cpm)->set_parameters(clock, parameters); } uint8_t x1600_cpm_get_source(void *cpm, enum Clock_identifiers clock) -{ +{ return static_cast(cpm)->get_source(clock); } void x1600_cpm_set_source(void *cpm, enum Clock_identifiers clock, uint8_t source) -{ +{ static_cast(cpm)->set_source(clock, source); } uint32_t x1600_cpm_get_source_frequency(void *cpm, enum Clock_identifiers clock) -{ +{ return static_cast(cpm)->get_source_frequency(clock); }