# HG changeset patch # User Paul Boddie # Date 1702660213 -3600 # Node ID 487c3de9908c4743173d42a30e57c40b337caffc # Parent 2c27c7715d4e2a7419fa77fe904aa90b861aeebc Introduced a value adjustment to the field abstraction, removing the specialised value adjustment in the PLL divider abstraction. diff -r 2c27c7715d4e -r 487c3de9908c pkg/devices/lib/cpm/include/cpm-common.h --- a/pkg/devices/lib/cpm/include/cpm-common.h Thu Dec 14 22:49:02 2023 +0100 +++ b/pkg/devices/lib/cpm/include/cpm-common.h Fri Dec 15 18:10:13 2023 +0100 @@ -63,6 +63,7 @@ uint32_t mask; uint8_t bit; bool defined; + uint32_t adjustment; uint32_t _asserted = 0, _deasserted = 0; public: @@ -72,8 +73,8 @@ } explicit Field(uint32_t reg, uint32_t mask, uint32_t bit, - bool inverted = false) - : reg(reg), mask(mask), bit(bit), defined(true) + bool inverted = false, uint32_t adjustment = 0) + : reg(reg), mask(mask), bit(bit), defined(true), adjustment(adjustment) { if (inverted) _deasserted = mask; @@ -347,7 +348,6 @@ { Field _multiplier, _input_divider, _output_divider0, _output_divider1; double _intermediate_min, _intermediate_max; - bool _adjust_by_one; // General frequency modifiers. @@ -364,12 +364,10 @@ explicit Divider_pll(Field multiplier, Field input_divider, Field output_divider0, Field output_divider1, - double intermediate_min, double intermediate_max, - bool adjust_by_one) + double intermediate_min, double intermediate_max) : _multiplier(multiplier), _input_divider(input_divider), _output_divider0(output_divider0), _output_divider1(output_divider1), - _intermediate_min(intermediate_min), _intermediate_max(intermediate_max), - _adjust_by_one(adjust_by_one) + _intermediate_min(intermediate_min), _intermediate_max(intermediate_max) { } @@ -377,12 +375,10 @@ explicit Divider_pll(Field multiplier, Field input_divider, Field output_divider, - double intermediate_min, double intermediate_max, - bool adjust_by_one) + double intermediate_min, double intermediate_max) : _multiplier(multiplier), _input_divider(input_divider), _output_divider0(output_divider), _output_divider1(Field::undefined), - _intermediate_min(intermediate_min), _intermediate_max(intermediate_max), - _adjust_by_one(adjust_by_one) + _intermediate_min(intermediate_min), _intermediate_max(intermediate_max) { } diff -r 2c27c7715d4e -r 487c3de9908c pkg/devices/lib/cpm/src/common.cc --- a/pkg/devices/lib/cpm/src/common.cc Thu Dec 14 22:49:02 2023 +0100 +++ b/pkg/devices/lib/cpm/src/common.cc Fri Dec 15 18:10:13 2023 +0100 @@ -63,7 +63,7 @@ Field::get_field(Cpm_regs ®s) { if (defined) - return regs.get_field(reg, mask, bit); + return regs.get_field(reg, mask, bit) + adjustment; else return 0; } @@ -72,7 +72,7 @@ Field::set_field(Cpm_regs ®s, uint32_t value) { if (defined) - regs.set_field(reg, mask, bit, value); + regs.set_field(reg, mask, bit, value >= adjustment ? value - adjustment : 0); } // Undefined field. @@ -451,19 +451,13 @@ uint32_t Divider_pll::get_multiplier(Cpm_regs ®s) { - if (_adjust_by_one) - return _multiplier.get_field(regs) + 1; - else - return zero_as_one(_multiplier.get_field(regs)); + return zero_as_one(_multiplier.get_field(regs)); } void Divider_pll::set_multiplier(Cpm_regs ®s, uint32_t multiplier) { - if (_adjust_by_one) - _multiplier.set_field(regs, multiplier - 1); - else - _multiplier.set_field(regs, multiplier); + _multiplier.set_field(regs, multiplier); } // Input divider. @@ -471,19 +465,13 @@ uint32_t Divider_pll::get_input_divider(Cpm_regs ®s) { - if (_adjust_by_one) - return _input_divider.get_field(regs) + 1; - else - return zero_as_one(_input_divider.get_field(regs)); + return zero_as_one(_input_divider.get_field(regs)); } void Divider_pll::set_input_divider(Cpm_regs ®s, uint32_t divider) { - if (_adjust_by_one) - _input_divider.set_field(regs, divider - 1); - else - _input_divider.set_field(regs, divider); + _input_divider.set_field(regs, divider); } // Output dividers. @@ -493,18 +481,9 @@ { uint32_t d0, d1; - if (_adjust_by_one) - { - d0 = _output_divider0.get_field(regs) + 1; - d1 = _output_divider1.is_defined() ? - _output_divider1.get_field(regs) + 1 : 1; - } - else - { - d0 = zero_as_one(_output_divider0.get_field(regs)); - d1 = _output_divider1.is_defined() ? - zero_as_one(_output_divider1.get_field(regs)) : 1; - } + d0 = zero_as_one(_output_divider0.get_field(regs)); + d1 = _output_divider1.is_defined() ? + zero_as_one(_output_divider1.get_field(regs)) : 1; return d0 * d1; } @@ -523,10 +502,7 @@ if (!_output_divider1.is_defined()) { - if (_adjust_by_one) - _output_divider0.set_field(regs, divider); - else - _output_divider0.set_field(regs, divider - 1); + _output_divider0.set_field(regs, divider); return; } @@ -544,16 +520,8 @@ d1 = divider / d0; } - if (_adjust_by_one) - { - _output_divider0.set_field(regs, d0 - 1); - _output_divider1.set_field(regs, d1 - 1); - } - else - { - _output_divider0.set_field(regs, d0); - _output_divider1.set_field(regs, d1); - } + _output_divider0.set_field(regs, d0); + _output_divider1.set_field(regs, d1); } uint64_t diff -r 2c27c7715d4e -r 487c3de9908c pkg/devices/lib/cpm/src/jz4780.cc --- a/pkg/devices/lib/cpm/src/jz4780.cc Thu Dec 14 22:49:02 2023 +0100 +++ b/pkg/devices/lib/cpm/src/jz4780.cc Fri Dec 15 18:10:13 2023 +0100 @@ -220,20 +220,22 @@ Pll_bypass_M (Pll_control_M, 1, 1), // MPLL_BP Pll_bypass_V (Pll_control_V, 1, 1), // VPLL_BP - Pll_multiplier_A (Pll_control_A, 0x1fff, 19), // APLLM - Pll_multiplier_E (Pll_control_E, 0x1fff, 19), // EPLLM - Pll_multiplier_M (Pll_control_M, 0x1fff, 19), // MPLLM - Pll_multiplier_V (Pll_control_V, 0x1fff, 19), // VPLLM + // Multipliers and dividers yield 1-based values. + + Pll_multiplier_A (Pll_control_A, 0x1fff, 19, 1), // APLLM + Pll_multiplier_E (Pll_control_E, 0x1fff, 19, 1), // EPLLM + Pll_multiplier_M (Pll_control_M, 0x1fff, 19, 1), // MPLLM + Pll_multiplier_V (Pll_control_V, 0x1fff, 19, 1), // VPLLM - Pll_input_division_A (Pll_control_A, 0x3f, 13), // APLLN - Pll_input_division_E (Pll_control_E, 0x3f, 13), // EPLLN - Pll_input_division_M (Pll_control_M, 0x3f, 13), // MPLLN - Pll_input_division_V (Pll_control_V, 0x3f, 13), // VPLLN + Pll_input_division_A (Pll_control_A, 0x3f, 13, 1), // APLLN + Pll_input_division_E (Pll_control_E, 0x3f, 13, 1), // EPLLN + Pll_input_division_M (Pll_control_M, 0x3f, 13, 1), // MPLLN + Pll_input_division_V (Pll_control_V, 0x3f, 13, 1), // VPLLN - Pll_output_division_A (Pll_control_A, 0x0f, 9), // APLLOD - Pll_output_division_E (Pll_control_E, 0x0f, 9), // EPLLOD - Pll_output_division_M (Pll_control_M, 0x0f, 9), // MPLLOD - Pll_output_division_V (Pll_control_V, 0x0f, 9); // VPLLOD + Pll_output_division_A (Pll_control_A, 0x0f, 9, 1), // APLLOD + Pll_output_division_E (Pll_control_E, 0x0f, 9, 1), // EPLLOD + Pll_output_division_M (Pll_control_M, 0x0f, 9, 1), // MPLLOD + Pll_output_division_V (Pll_control_V, 0x0f, 9, 1); // VPLLOD @@ -457,29 +459,25 @@ Control_pll(Pll_enable_A, Pll_stable_A, Pll_bypass_A), Divider_pll(Pll_multiplier_A, Pll_input_division_A, Pll_output_division_A, - jz4780_pll_intermediate_min, jz4780_pll_intermediate_max, - true)), + jz4780_pll_intermediate_min, jz4780_pll_intermediate_max)), clock_pll_E(Source(mux_external), Control_pll(Pll_enable_E, Pll_stable_E, Pll_bypass_E), Divider_pll(Pll_multiplier_E, Pll_input_division_E, Pll_output_division_E, - jz4780_pll_intermediate_min, jz4780_pll_intermediate_max, - true)), + jz4780_pll_intermediate_min, jz4780_pll_intermediate_max)), clock_pll_M(Source(mux_external), Control_pll(Pll_enable_M, Pll_stable_M, Pll_bypass_M), Divider_pll(Pll_multiplier_M, Pll_input_division_M, Pll_output_division_M, - jz4780_pll_intermediate_min, jz4780_pll_intermediate_max, - true)), + jz4780_pll_intermediate_min, jz4780_pll_intermediate_max)), clock_pll_V(Source(mux_external), Control_pll(Pll_enable_V, Pll_stable_V, Pll_bypass_V), Divider_pll(Pll_multiplier_V, Pll_input_division_V, Pll_output_division_V, - jz4780_pll_intermediate_min, jz4780_pll_intermediate_max, - true)); + jz4780_pll_intermediate_min, jz4780_pll_intermediate_max)); diff -r 2c27c7715d4e -r 487c3de9908c pkg/devices/lib/cpm/src/x1600.cc --- a/pkg/devices/lib/cpm/src/x1600.cc Thu Dec 14 22:49:02 2023 +0100 +++ b/pkg/devices/lib/cpm/src/x1600.cc Fri Dec 15 18:10:13 2023 +0100 @@ -403,22 +403,19 @@ Control_pll(Pll_enable_A, Pll_stable_A, Pll_bypass_A), Divider_pll(Pll_multiplier_A, Pll_input_division_A, Pll_output_division0_A, Pll_output_division1_A, - x1600_pll_intermediate_min, x1600_pll_intermediate_max, - false)), + x1600_pll_intermediate_min, x1600_pll_intermediate_max)), clock_pll_E(Source(mux_external), Control_pll(Pll_enable_E, Pll_stable_E, Pll_bypass_E), Divider_pll(Pll_multiplier_E, Pll_input_division_E, Pll_output_division0_E, Pll_output_division1_E, - x1600_pll_intermediate_min, x1600_pll_intermediate_max, - false)), + x1600_pll_intermediate_min, x1600_pll_intermediate_max)), clock_pll_M(Source(mux_external), Control_pll(Pll_enable_M, Pll_stable_M, Pll_bypass_M), Divider_pll(Pll_multiplier_M, Pll_input_division_M, Pll_output_division0_M, Pll_output_division1_M, - x1600_pll_intermediate_min, x1600_pll_intermediate_max, - false)); + x1600_pll_intermediate_min, x1600_pll_intermediate_max));