# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1715956469 -7200
# Node ID 5db87c60ad18521de7c3192f7a0129aeafa58dca
# Parent  ef29d83b79f853c895654e388b17f8ae78a282f9
Made I2S0 RX and TX simple gated clocks, moving division to I2S0 and I2S1.

diff -r ef29d83b79f8 -r 5db87c60ad18 pkg/devices/lib/cpm/src/x1600.cc
--- a/pkg/devices/lib/cpm/src/x1600.cc	Fri May 17 16:32:55 2024 +0200
+++ b/pkg/devices/lib/cpm/src/x1600.cc	Fri May 17 16:34:29 2024 +0200
@@ -296,9 +296,9 @@
 
              clock_i2c1((Source(mux_pclock)), (Control(Clock_gate_i2c1))),
 
-             clock_i2s0(Source(mux_i2s, Clock_source_i2s0), Control(Clock_gate_i2s0)),
+             clock_i2s0_rx((Source(mux_i2s0_rx)), (Control(Clock_gate_i2s0_rx))),
 
-             clock_i2s1(Source(mux_i2s, Clock_source_i2s1), Control(Clock_gate_i2s1)),
+             clock_i2s0_tx((Source(mux_i2s0_tx)), (Control(Clock_gate_i2s0_tx))),
 
              clock_main(Source(mux_main, Clock_source_main), Control(Clock_gate_main)),
 
@@ -413,17 +413,17 @@
              clock_external_div((Source(mux_external)), (Divider_fixed(512)));
 
 static Clock_divided_i2s
-             clock_i2s0_rx(Source(mux_i2s0_rx),
-                           Control(Clock_gate_i2s0_rx),
-                           Divider_i2s(Clock_divider_i2s0_m, Clock_divider_i2s0_n,
-                                       Clock_divider_i2s0_d, Clock_divider_i2s0_n_auto,
-                                       Clock_divider_i2s0_d_auto)),
+             clock_i2s0(Source(mux_i2s, Clock_source_i2s0),
+                        Control(Clock_gate_i2s0),
+                        Divider_i2s(Clock_divider_i2s0_m, Clock_divider_i2s0_n,
+                                    Clock_divider_i2s0_d, Clock_divider_i2s0_n_auto,
+                                    Clock_divider_i2s0_d_auto)),
 
-             clock_i2s0_tx(Source(mux_i2s0_tx),
-                           Control(Clock_gate_i2s0_tx),
-                           Divider_i2s(Clock_divider_i2s1_m, Clock_divider_i2s1_n,
-                                       Clock_divider_i2s1_d, Clock_divider_i2s1_n_auto,
-                                       Clock_divider_i2s1_d_auto));
+             clock_i2s1(Source(mux_i2s, Clock_source_i2s1),
+                        Control(Clock_gate_i2s1),
+                        Divider_i2s(Clock_divider_i2s1_m, Clock_divider_i2s1_n,
+                                    Clock_divider_i2s1_d, Clock_divider_i2s1_n_auto,
+                                    Clock_divider_i2s1_d_auto));
 
 const double x1600_pll_intermediate_min = 600000000,
              x1600_pll_intermediate_max = 2400000000;