# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1713536236 -7200
# Node ID 5f26a9f2c2f6e2d970de51b158097f68a50db4ba
# Parent  f2cac5d96acd27ddbdef6d8d32014e8cb143a5f0
Fixed JZ4780 PLL fields disrupted by earlier Field constructor change.

diff -r f2cac5d96acd -r 5f26a9f2c2f6 pkg/devices/lib/cpm/src/jz4780.cc
--- a/pkg/devices/lib/cpm/src/jz4780.cc	Thu Apr 04 00:31:36 2024 +0200
+++ b/pkg/devices/lib/cpm/src/jz4780.cc	Fri Apr 19 16:17:16 2024 +0200
@@ -3,7 +3,8 @@
  * provided by the jz4780 and related SoCs. The power management
  * functionality could be exposed using a separate driver.
  *
- * Copyright (C) 2017, 2018, 2020, 2021, 2023 Paul Boddie <paul@boddie.org.uk>
+ * Copyright (C) 2017, 2018, 2020, 2021, 2023,
+ *               2024 Paul Boddie <paul@boddie.org.uk>
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -222,20 +223,20 @@
 
              // Multipliers and dividers yield 1-based values.
 
-             Pll_multiplier_A          (Pll_control_A, 0x1fff, 19, 1),  // APLLM
-             Pll_multiplier_E          (Pll_control_E, 0x1fff, 19, 1),  // EPLLM
-             Pll_multiplier_M          (Pll_control_M, 0x1fff, 19, 1),  // MPLLM
-             Pll_multiplier_V          (Pll_control_V, 0x1fff, 19, 1),  // VPLLM
+             Pll_multiplier_A          (Pll_control_A, 0x1fff, 19, false, 1), // APLLM
+             Pll_multiplier_E          (Pll_control_E, 0x1fff, 19, false, 1), // EPLLM
+             Pll_multiplier_M          (Pll_control_M, 0x1fff, 19, false, 1), // MPLLM
+             Pll_multiplier_V          (Pll_control_V, 0x1fff, 19, false, 1), // VPLLM
 
-             Pll_input_division_A      (Pll_control_A, 0x3f, 13, 1),    // APLLN
-             Pll_input_division_E      (Pll_control_E, 0x3f, 13, 1),    // EPLLN
-             Pll_input_division_M      (Pll_control_M, 0x3f, 13, 1),    // MPLLN
-             Pll_input_division_V      (Pll_control_V, 0x3f, 13, 1),    // VPLLN
+             Pll_input_division_A      (Pll_control_A, 0x3f, 13, false, 1),   // APLLN
+             Pll_input_division_E      (Pll_control_E, 0x3f, 13, false, 1),   // EPLLN
+             Pll_input_division_M      (Pll_control_M, 0x3f, 13, false, 1),   // MPLLN
+             Pll_input_division_V      (Pll_control_V, 0x3f, 13, false, 1),   // VPLLN
 
-             Pll_output_division_A     (Pll_control_A, 0x0f, 9, 1),     // APLLOD
-             Pll_output_division_E     (Pll_control_E, 0x0f, 9, 1),     // EPLLOD
-             Pll_output_division_M     (Pll_control_M, 0x0f, 9, 1),     // MPLLOD
-             Pll_output_division_V     (Pll_control_V, 0x0f, 9, 1);     // VPLLOD
+             Pll_output_division_A     (Pll_control_A, 0x0f, 9, false, 1),    // APLLOD
+             Pll_output_division_E     (Pll_control_E, 0x0f, 9, false, 1),    // EPLLOD
+             Pll_output_division_M     (Pll_control_M, 0x0f, 9, false, 1),    // MPLLOD
+             Pll_output_division_V     (Pll_control_V, 0x0f, 9, false, 1);    // VPLLOD