# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1700320980 -3600
# Node ID 7e6f353b0f8210d1aa0353ffa70ff4229c9e0019
# Parent  c705336ff60014d9d968ce3735219806eb40096f
Introduced a scale factor to dividers, fixing the MSC clock dividers.
Exposed more clocks via the common clock register.

diff -r c705336ff600 -r 7e6f353b0f82 pkg/devices/include/clocks.h
--- a/pkg/devices/include/clocks.h	Fri Nov 17 18:38:44 2023 +0100
+++ b/pkg/devices/include/clocks.h	Sat Nov 18 16:23:00 2023 +0100
@@ -69,6 +69,7 @@
   Clock_msc0,
   Clock_msc1,
   Clock_msc2,
+  Clock_nemc,
   Clock_otg0,
   Clock_otg1,
   Clock_pclock,           /* APB */
@@ -81,6 +82,7 @@
   Clock_pwm1,
   Clock_rtc,              /* RTC parent clock */
   Clock_rtc_external,     /* RTCLK */
+  Clock_sadc,
   Clock_scc,
   Clock_sfc,
   Clock_ssi,              /* SSI parent clock (JZ4780) */
diff -r c705336ff600 -r 7e6f353b0f82 pkg/devices/lib/cpm/include/cpm-common.h
--- a/pkg/devices/lib/cpm/include/cpm-common.h	Fri Nov 17 18:38:44 2023 +0100
+++ b/pkg/devices/lib/cpm/include/cpm-common.h	Sat Nov 18 16:23:00 2023 +0100
@@ -310,15 +310,16 @@
 class Divider : public Divider_base
 {
   Field _divider;
+  int _scale;
 
 public:
-  explicit Divider(Field divider)
-  : _divider(divider)
+  explicit Divider(Field divider, int scale = 1)
+  : _divider(divider), _scale(scale)
   {
   }
 
   explicit Divider()
-  : _divider(Field::undefined)
+  : _divider(Field::undefined), _scale(1)
   {
   }
 
diff -r c705336ff600 -r 7e6f353b0f82 pkg/devices/lib/cpm/src/common.cc
--- a/pkg/devices/lib/cpm/src/common.cc	Fri Nov 17 18:38:44 2023 +0100
+++ b/pkg/devices/lib/cpm/src/common.cc	Sat Nov 18 16:23:00 2023 +0100
@@ -342,7 +342,7 @@
 Divider::get_divider(Cpm_regs &regs)
 {
   if (_divider.is_defined())
-    return _divider.get_field(regs) + 1;
+    return _scale * (_divider.get_field(regs) + 1);
   else
     return 1;
 }
@@ -351,7 +351,7 @@
 Divider::set_divider(Cpm_regs &regs, uint32_t divider)
 {
   if (_divider.is_defined())
-    _divider.set_field(regs, divider - 1);
+    _divider.set_field(regs, divider / _scale - 1);
 }
 
 // Output clock frequencies.
diff -r c705336ff600 -r 7e6f353b0f82 pkg/devices/lib/cpm/src/jz4780.cc
--- a/pkg/devices/lib/cpm/src/jz4780.cc	Fri Nov 17 18:38:44 2023 +0100
+++ b/pkg/devices/lib/cpm/src/jz4780.cc	Sat Nov 18 16:23:00 2023 +0100
@@ -417,15 +417,15 @@
 
              clock_msc0(Source(mux_clock_msc),
                         Control(Clock_gate_msc0, Clock_change_enable_msc0, Clock_busy_msc0),
-                        Divider(Clock_divider_msc0)),
+                        Divider(Clock_divider_msc0, 2)),
 
              clock_msc1(Source(mux_clock_msc),
                         Control(Clock_gate_msc1, Clock_change_enable_msc1, Clock_busy_msc1),
-                        Divider(Clock_divider_msc1)),
+                        Divider(Clock_divider_msc1, 2)),
 
              clock_msc2(Source(mux_clock_msc),
                         Control(Clock_gate_msc2, Clock_change_enable_msc2, Clock_busy_msc2),
-                        Divider(Clock_divider_msc2)),
+                        Divider(Clock_divider_msc2, 2)),
 
              clock_pcm(Source(mux_pcm, Clock_source_pcm),
                        Control(Clock_gate_pcm, Clock_change_enable_pcm, Clock_busy_pcm),
@@ -528,6 +528,7 @@
   &clock_msc0,
   &clock_msc1,
   &clock_msc2,
+  &clock_nemc,
   &clock_otg0,
   &clock_otg1,
   &clock_pclock,
@@ -540,6 +541,7 @@
   &clock_none,            // Clock_pwm1
   &clock_external_div_512,// Clock_rtc
   &clock_rtc_external,
+  &clock_sadc,
   &clock_scc,
   &clock_none,            // Clock_sfc
   &clock_ssi,
diff -r c705336ff600 -r 7e6f353b0f82 pkg/devices/lib/cpm/src/x1600.cc
--- a/pkg/devices/lib/cpm/src/x1600.cc	Fri Nov 17 18:38:44 2023 +0100
+++ b/pkg/devices/lib/cpm/src/x1600.cc	Sat Nov 18 16:23:00 2023 +0100
@@ -290,10 +290,14 @@
 
              clock_mipi_csi((Source(mux_hclock0)), Control(Clock_gate_mipi_csi)),
 
+             clock_nemc((Source(mux_hclock2)), (Control(Clock_gate_nemc))),
+
              clock_otg0((Source(mux_hclock2)), (Control(Clock_gate_otg))),
 
              clock_rtc(Source(mux_rtc, Clock_source_rtc), (Control(Clock_gate_rtc))),
 
+             clock_sadc((Source(mux_hclock2)), (Control(Clock_gate_sadc))),
+
              clock_timer((Source(mux_pclock)), (Control(Clock_gate_timer))),
 
              clock_uart0((Source(mux_external)), (Control(Clock_gate_uart0))),
@@ -356,11 +360,11 @@
 
              clock_msc0(Source(mux_dev, Clock_source_msc0),
                         Control(Clock_gate_msc0, Clock_change_enable_msc0, Clock_busy_msc0),
-                        Divider(Clock_divider_msc0)),
+                        Divider(Clock_divider_msc0, 2)),
 
              clock_msc1(Source(mux_dev, Clock_source_msc1),
                         Control(Clock_gate_msc1, Clock_change_enable_msc1, Clock_busy_msc1),
-                        Divider(Clock_divider_msc1)),
+                        Divider(Clock_divider_msc1, 2)),
 
              clock_pclock((Source(mux_hclock2_pclock)), (Divider(Clock_divider_pclock))),
 
@@ -463,6 +467,7 @@
   &clock_msc0,
   &clock_msc1,
   &clock_none,            // Clock_msc2
+  &clock_nemc,
   &clock_otg0,
   &clock_none,            // Clock_otg1
   &clock_pclock,
@@ -475,6 +480,7 @@
   &clock_none,            // Clock_pwm1
   &clock_rtc,
   &clock_rtc_external,
+  &clock_sadc,
   &clock_none,            // Clock_scc
   &clock_sfc,
   &clock_none,            // Clock_ssi