# HG changeset patch # User Paul Boddie # Date 1694710301 -7200 # Node ID 8db009384d0bbedba72a83a89222d46f84b5964b # Parent e8a795e4d3bfd720b2fc090c1df30061b61c4360 Merged clock identifiers to permit uniform clock handling. diff -r e8a795e4d3bf -r 8db009384d0b pkg/devices/include/clocks.h --- a/pkg/devices/include/clocks.h Thu Sep 14 01:38:13 2023 +0200 +++ b/pkg/devices/include/clocks.h Thu Sep 14 18:51:41 2023 +0200 @@ -27,6 +27,7 @@ enum Clock_identifiers { + Clock_ahb2_apb, Clock_aic_bitclk, Clock_aic_pclk, Clock_can0, @@ -37,6 +38,7 @@ Clock_ddr, Clock_dma, Clock_emac, + Clock_external, Clock_hclock0, Clock_hclock2, Clock_hdmi, @@ -54,7 +56,11 @@ Clock_msc, Clock_msc0, Clock_msc1, + Clock_none, Clock_pclock, + Clock_pll_A, + Clock_pll_E, + Clock_pll_M, Clock_pwm, Clock_pwm0, Clock_pwm1, diff -r e8a795e4d3bf -r 8db009384d0b pkg/devices/lib/cpm/include/cpm-x1600.h --- a/pkg/devices/lib/cpm/include/cpm-x1600.h Thu Sep 14 01:38:13 2023 +0200 +++ b/pkg/devices/lib/cpm/include/cpm-x1600.h Thu Sep 14 18:51:41 2023 +0200 @@ -32,20 +32,6 @@ #include -enum Clock_input_identifiers -{ - Clock_input_ahb2_apb, - Clock_input_external, - Clock_input_main, - Clock_input_none, - Clock_input_pll_A, - Clock_input_pll_E, - Clock_input_pll_M, - Clock_input_identifier_count, /* not a clock: limit for array definition */ -}; - - - /* A simple abstraction for accessing the CPM registers. * A proper device could inherit from Hw::Device and use an * Int_property for _exclk_freq. */ diff -r e8a795e4d3bf -r 8db009384d0b pkg/devices/lib/cpm/src/x1600.cc --- a/pkg/devices/lib/cpm/src/x1600.cc Thu Sep 14 01:38:13 2023 +0200 +++ b/pkg/devices/lib/cpm/src/x1600.cc Thu Sep 14 18:51:41 2023 +0200 @@ -263,42 +263,6 @@ -// Clock input descriptions. - -struct Clock_input_desc -{ - uint32_t source_reg; - enum Clock_source_bits source_bit; - int num_inputs; - enum Clock_input_identifiers inputs[3]; -}; - -struct Clock_input_desc clock_input_desc[Clock_input_identifier_count] = { - - /* Clock_input_ahb2_apb */ {Clock_control, Clock_source_hclock2, - 3, {Clock_input_none, Clock_input_main, Clock_input_pll_M}}, - - /* Clock_input_external */ {Reg_undefined, Clock_source_undefined, - 0, {}}, - - /* Clock_input_main */ {Clock_control, Clock_source_main, - 3, {Clock_input_none, Clock_input_external, Clock_input_pll_A}}, - - /* Clock_input_none */ {Reg_undefined, Clock_source_undefined, - 0, {}}, - - /* Clock_input_pll_A */ {Reg_undefined, Clock_source_undefined, - 1, {Clock_input_external}}, - - /* Clock_input_pll_E */ {Reg_undefined, Clock_source_undefined, - 1, {Clock_input_external}}, - - /* Clock_input_pll_M */ {Reg_undefined, Clock_source_undefined, - 1, {Clock_input_external}}, -}; - - - // Clock descriptions. struct Clock_desc @@ -315,8 +279,7 @@ enum Clock_divider_bits divider_bit; uint32_t divider_mask; int num_inputs; - enum Clock_input_identifiers inputs[4]; - enum Clock_identifiers clock_input; + enum Clock_identifiers inputs[4]; }; #define Clock_desc_undefined {Reg_undefined, Clock_source_undefined, \ @@ -324,11 +287,17 @@ Reg_undefined, Clock_change_enable_undefined, \ Reg_undefined, Clock_busy_undefined, \ Reg_undefined, Clock_divider_undefined, 0, \ - 0, {}, \ - Clock_undefined} + 0, {}} static struct Clock_desc clock_desc[Clock_identifier_count] = { + /* Clock_ahb2_apb */ {Clock_control, Clock_source_hclock2, + Reg_undefined, Clock_gate_undefined, + Reg_undefined, Clock_change_enable_undefined, + Reg_undefined, Clock_busy_undefined, + Reg_undefined, Clock_divider_undefined, 0, + 3, {Clock_none, Clock_main, Clock_pll_M}}, + /* Clock_aic_bitclk */ Clock_desc_undefined, /* Clock_aic_pclk */ Clock_desc_undefined, @@ -338,74 +307,72 @@ Can_divider0, Clock_change_enable_can0, Can_divider0, Clock_busy_can0, Can_divider0, Clock_divider_can0, 0xff, - 4, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E, Clock_input_external}, - Clock_undefined}, + 4, {Clock_main, Clock_pll_M, Clock_pll_E, Clock_external}}, /* Clock_can1 */ {Can_divider1, Clock_source_can1, Clock_gate1, Clock_gate_can1, Can_divider1, Clock_change_enable_can1, Can_divider1, Clock_busy_can1, Can_divider1, Clock_divider_can1, 0xff, - 4, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E, Clock_input_external}, - Clock_undefined}, + 4, {Clock_main, Clock_pll_M, Clock_pll_E, Clock_external}}, /* Clock_cdbus */ {Cdbus_divider, Clock_source_cdbus, Clock_gate1, Clock_gate_cdbus, Cdbus_divider, Clock_change_enable_cdbus, Cdbus_divider, Clock_busy_cdbus, Cdbus_divider, Clock_divider_cdbus, 0xff, - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E}, - Clock_undefined}, + 3, {Clock_main, Clock_pll_M, Clock_pll_E}}, /* Clock_cim */ {Cim_divider, Clock_source_cim, Clock_gate0, Clock_gate_cim, Cim_divider, Clock_change_enable_cim, Cim_divider, Clock_busy_cim, Cim_divider, Clock_divider_cim, 0xff, - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E}, - Clock_undefined}, + 3, {Clock_main, Clock_pll_M, Clock_pll_E}}, /* Clock_cpu */ {Clock_control, Clock_source_cpu, Reg_undefined, Clock_gate_undefined, Clock_control, Clock_change_enable_cpu, Clock_status, Clock_busy_cpu, Clock_control, Clock_divider_cpu, 0x0f, - 3, {Clock_input_none, Clock_input_main, Clock_input_pll_M}, - Clock_undefined}, + 3, {Clock_none, Clock_main, Clock_pll_M}}, /* Clock_ddr */ {Ddr_divider, Clock_source_ddr, Clock_gate0, Clock_gate_ddr, Ddr_divider, Clock_change_enable_ddr, Ddr_divider, Clock_busy_ddr, Ddr_divider, Clock_divider_ddr, 0x0f, - 3, {Clock_input_none, Clock_input_main, Clock_input_pll_M}, - Clock_undefined}, + 3, {Clock_none, Clock_main, Clock_pll_M}}, /* Clock_dma */ {Reg_undefined, Clock_source_undefined, Clock_gate0, Clock_gate_dma, Reg_undefined, Clock_change_enable_undefined, Reg_undefined, Clock_busy_undefined, Reg_undefined, Clock_divider_undefined, 0, - 0, {}, - Clock_pclock}, + 1, {Clock_pclock}}, /* Clock_emac */ Clock_desc_undefined, + /* Clock_external */ {Reg_undefined, Clock_source_undefined, + Reg_undefined, Clock_gate_undefined, + Reg_undefined, Clock_change_enable_undefined, + Reg_undefined, Clock_busy_undefined, + Reg_undefined, Clock_divider_undefined, 0, + 0, {}}, + /* Clock_hclock0 */ {Clock_control, Clock_source_hclock0, Clock_gate0, Clock_gate_ahb0, Clock_control, Clock_change_enable_ahb0, Reg_undefined, Clock_busy_undefined, Clock_control, Clock_divider_hclock0, 0x0f, - 3, {Clock_input_none, Clock_input_main, Clock_input_pll_M}, - Clock_undefined}, + 3, {Clock_none, Clock_main, Clock_pll_M}}, /* Clock_hclock2 */ {Reg_undefined, Clock_source_undefined, Clock_gate0, Clock_gate_apb0, Clock_control, Clock_change_enable_ahb2, Reg_undefined, Clock_busy_undefined, Clock_control, Clock_divider_hclock2, 0x0f, - 1, {Clock_input_ahb2_apb}, - Clock_undefined}, + 1, {Clock_ahb2_apb}}, /* Clock_hdmi */ Clock_desc_undefined, @@ -414,24 +381,21 @@ Reg_undefined, Clock_change_enable_undefined, Reg_undefined, Clock_busy_undefined, Reg_undefined, Clock_divider_undefined, 0, - 0, {}, - Clock_pclock}, + 1, {Clock_pclock}}, /* Clock_i2c0 */ {Reg_undefined, Clock_source_undefined, Clock_gate0, Clock_gate_i2c0, Reg_undefined, Clock_change_enable_undefined, Reg_undefined, Clock_busy_undefined, Reg_undefined, Clock_divider_undefined, 0, - 0, {}, - Clock_pclock}, + 1, {Clock_pclock}}, /* Clock_i2c1 */ {Reg_undefined, Clock_source_undefined, Clock_gate0, Clock_gate_i2c1, Reg_undefined, Clock_change_enable_undefined, Reg_undefined, Clock_busy_undefined, Reg_undefined, Clock_divider_undefined, 0, - 0, {}, - Clock_pclock}, + 1, {Clock_pclock}}, /* Clock_i2s */ Clock_desc_undefined, @@ -440,16 +404,14 @@ I2s_divider0, Clock_change_enable_i2s, Reg_undefined, Clock_busy_undefined, Reg_undefined, Clock_divider_undefined, 0, // NOTE: To define. - 2, {Clock_input_main, Clock_input_pll_E}, - Clock_undefined}, + 2, {Clock_main, Clock_pll_E}}, /* Clock_i2s0_tx */ {I2s_divider0, Clock_source_i2s, Clock_gate1, Clock_gate_i2s0_tx, I2s_divider0, Clock_change_enable_i2s, Reg_undefined, Clock_busy_undefined, Reg_undefined, Clock_divider_undefined, 0, // NOTE: To define. - 2, {Clock_input_main, Clock_input_pll_E}, - Clock_undefined}, + 2, {Clock_main, Clock_pll_E}}, /* Clock_kbc */ Clock_desc_undefined, @@ -460,72 +422,91 @@ Lcd_divider, Clock_change_enable_lcd, Lcd_divider, Clock_busy_lcd, Lcd_divider, Clock_divider_lcd, 0xff, - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E}, - Clock_undefined}, + 3, {Clock_main, Clock_pll_M, Clock_pll_E}}, /* Clock_mac */ {Mac_divider, Clock_source_mac, Clock_gate1, Clock_gate_gmac0, Mac_divider, Clock_change_enable_mac, Mac_divider, Clock_busy_mac, Mac_divider, Clock_divider_mac, 0xff, - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E}, - Clock_undefined}, + 3, {Clock_main, Clock_pll_M, Clock_pll_E}}, - /* Clock_main */ {Reg_undefined, Clock_source_undefined, + /* Clock_main */ {Clock_control, Clock_source_main, Clock_control, Clock_gate_main, Reg_undefined, Clock_change_enable_undefined, Reg_undefined, Clock_busy_undefined, Reg_undefined, Clock_divider_undefined, 0, - 1, {Clock_input_main}, - Clock_undefined}, + 3, {Clock_none, Clock_external, Clock_pll_A}}, /* Clock_msc */ {Msc_divider0, Clock_source_msc0, Clock_gate0, Clock_gate_msc0, Msc_divider0, Clock_change_enable_msc0, Msc_divider0, Clock_busy_msc0, Msc_divider0, Clock_divider_msc0, 0xff, - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E}, - Clock_undefined}, + 3, {Clock_main, Clock_pll_M, Clock_pll_E}}, /* Clock_msc0 */ {Msc_divider0, Clock_source_msc0, Clock_gate0, Clock_gate_msc0, Msc_divider0, Clock_change_enable_msc0, Msc_divider0, Clock_busy_msc0, Msc_divider0, Clock_divider_msc0, 0xff, - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E}, - Clock_undefined}, + 3, {Clock_main, Clock_pll_M, Clock_pll_E}}, /* Clock_msc1 */ {Msc_divider1, Clock_source_msc1, Clock_gate0, Clock_gate_msc1, Msc_divider1, Clock_change_enable_msc1, Msc_divider1, Clock_busy_msc1, Msc_divider1, Clock_divider_msc1, 0xff, - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E}, - Clock_undefined}, + 3, {Clock_main, Clock_pll_M, Clock_pll_E}}, + + /* Clock_none */ {Reg_undefined, Clock_source_undefined, + Reg_undefined, Clock_gate_undefined, + Reg_undefined, Clock_change_enable_undefined, + Reg_undefined, Clock_busy_undefined, + Reg_undefined, Clock_divider_undefined, 0, + 0, {}}, /* Clock_pclock */ {Reg_undefined, Clock_source_undefined, Clock_gate0, Clock_gate_apb0, Reg_undefined, Clock_change_enable_undefined, Reg_undefined, Clock_busy_undefined, Clock_control, Clock_divider_pclock, 0x0f, - 1, {Clock_input_ahb2_apb}, - Clock_undefined}, + 1, {Clock_ahb2_apb}}, + + /* Clock_pll_A */ {Reg_undefined, Clock_source_undefined, + Reg_undefined, Clock_gate_undefined, + Reg_undefined, Clock_change_enable_undefined, + Reg_undefined, Clock_busy_undefined, + Reg_undefined, Clock_divider_undefined, 0, + 1, {Clock_external}}, + + /* Clock_pll_E */ {Reg_undefined, Clock_source_undefined, + Reg_undefined, Clock_gate_undefined, + Reg_undefined, Clock_change_enable_undefined, + Reg_undefined, Clock_busy_undefined, + Reg_undefined, Clock_divider_undefined, 0, + 1, {Clock_external}}, + + /* Clock_pll_M */ {Reg_undefined, Clock_source_undefined, + Reg_undefined, Clock_gate_undefined, + Reg_undefined, Clock_change_enable_undefined, + Reg_undefined, Clock_busy_undefined, + Reg_undefined, Clock_divider_undefined, 0, + 1, {Clock_external}}, /* Clock_pwm */ {Pwm_divider, Clock_source_pwm, Clock_gate1, Clock_gate_pwm, Pwm_divider, Clock_change_enable_pwm, Pwm_divider, Clock_busy_pwm, Pwm_divider, Clock_divider_pwm, 0x0f, - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E}, - Clock_undefined}, + 3, {Clock_main, Clock_pll_M, Clock_pll_E}}, /* Clock_pwm0 */ {Pwm_divider, Clock_source_pwm, Clock_gate1, Clock_gate_pwm, Pwm_divider, Clock_change_enable_pwm, Pwm_divider, Clock_busy_pwm, Pwm_divider, Clock_divider_pwm, 0x0f, - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E}, - Clock_undefined}, + 3, {Clock_main, Clock_pll_M, Clock_pll_E}}, /* Clock_pwm1 */ Clock_desc_undefined, @@ -536,8 +517,7 @@ Sfc_divider, Clock_change_enable_sfc, Sfc_divider, Clock_busy_sfc, Sfc_divider, Clock_divider_sfc, 0xff, - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E}, - Clock_undefined}, + 3, {Clock_main, Clock_pll_M, Clock_pll_E}}, /* Clock_smb0 */ Clock_desc_undefined, @@ -554,48 +534,42 @@ Ssi_divider, Clock_change_enable_ssi, Ssi_divider, Clock_busy_ssi, Ssi_divider, Clock_divider_ssi, 0xff, - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E}, - Clock_undefined}, + 3, {Clock_main, Clock_pll_M, Clock_pll_E}}, /* Clock_timer */ {Reg_undefined, Clock_source_undefined, Clock_gate0, Clock_gate_timer, Reg_undefined, Clock_change_enable_undefined, Reg_undefined, Clock_busy_undefined, Reg_undefined, Clock_divider_undefined, 0, - 0, {}, - Clock_pclock}, + 1, {Clock_pclock}}, /* Clock_uart0 */ {Reg_undefined, Clock_source_undefined, Clock_gate0, Clock_gate_uart0, Reg_undefined, Clock_change_enable_undefined, Reg_undefined, Clock_busy_undefined, Reg_undefined, Clock_divider_undefined, 0, - 1, {Clock_input_external}, - Clock_undefined}, + 1, {Clock_external}}, /* Clock_uart1 */ {Reg_undefined, Clock_source_undefined, Clock_gate0, Clock_gate_uart1, Reg_undefined, Clock_change_enable_undefined, Reg_undefined, Clock_busy_undefined, Reg_undefined, Clock_divider_undefined, 0, - 1, {Clock_input_external}, - Clock_undefined}, + 1, {Clock_external}}, /* Clock_uart2 */ {Reg_undefined, Clock_source_undefined, Clock_gate0, Clock_gate_uart2, Reg_undefined, Clock_change_enable_undefined, Reg_undefined, Clock_busy_undefined, Reg_undefined, Clock_divider_undefined, 0, - 1, {Clock_input_external}, - Clock_undefined}, + 1, {Clock_external}}, /* Clock_uart3 */ {Reg_undefined, Clock_source_undefined, Clock_gate1, Clock_gate_uart3, Reg_undefined, Clock_change_enable_undefined, Reg_undefined, Clock_busy_undefined, Reg_undefined, Clock_divider_undefined, 0, - 1, {Clock_input_external}, - Clock_undefined}, + 1, {Clock_external}}, /* Clock_udc */ Clock_desc_undefined, @@ -892,68 +866,32 @@ // Clock source frequencies. uint32_t -Cpm_x1600_chip::get_input_frequency(enum Clock_input_identifiers clock) -{ - struct Clock_input_desc desc = clock_input_desc[clock]; - - // Clocks with no inputs provide a frequency. - - if (desc.num_inputs == 0) - { - switch (clock) - { - case Clock_input_external: return _exclk_freq; - default: return 0; - } - } - - // Of the input clocks, only PLLs have a single input. - - else if (desc.num_inputs == 1) - { - switch (clock) - { - case Clock_input_pll_A: return get_pll_frequency(Pll_control_A); - case Clock_input_pll_E: return get_pll_frequency(Pll_control_E); - case Clock_input_pll_M: return get_pll_frequency(Pll_control_M); - default: return 0; - } - } - - // With multiple sources, obtain the selected source for the clock. - - uint8_t source = get_field(desc.source_reg, Source_mask, desc.source_bit); - - // Return the frequency of the source. - - if (source < desc.num_inputs) - return get_input_frequency(desc.inputs[source]); - else - return 0; -} - -uint32_t Cpm_x1600_chip::get_source_frequency(enum Clock_identifiers clock) { struct Clock_desc desc = clock_desc[clock]; if (desc.num_inputs == 0) { - // Clocks may reference other clocks. - - if (desc.clock_input != Clock_undefined) - return get_frequency(desc.clock_input); - - // Undefined clocks return zero. - - else - return 0; + switch (clock) + { + case Clock_external: return _exclk_freq; + default: return 0; + } } - // Clocks with one source yield that input frequency. + // Clocks with one source yield that input frequency, although PLLs are + // handled specially. else if (desc.num_inputs == 1) - return get_input_frequency(desc.inputs[0]); + { + switch (clock) + { + case Clock_pll_A: return get_pll_frequency(Pll_control_A); + case Clock_pll_E: return get_pll_frequency(Pll_control_E); + case Clock_pll_M: return get_pll_frequency(Pll_control_M); + default: return get_frequency(desc.inputs[0]); + } + } // With multiple sources, obtain the selected source for the clock. @@ -962,7 +900,7 @@ // Return the frequency of the source. if (source < desc.num_inputs) - return get_input_frequency(desc.inputs[source]); + return get_frequency(desc.inputs[source]); else return 0; }