2.1 --- a/pkg/devices/lib/hdmi/src/jz4780.cc Sat May 23 22:34:17 2020 +0200
2.2 +++ b/pkg/devices/lib/hdmi/src/jz4780.cc Mon Jun 01 15:37:38 2020 +0200
2.3 @@ -3,6 +3,13 @@
2.4 *
2.5 * Copyright (C) 2020 Paul Boddie <paul@boddie.org.uk>
2.6 *
2.7 + * Techniques and operations introduced from the Linux DRM bridge driver for
2.8 + * Synopsys DW-HDMI whose authors are as follows:
2.9 + *
2.10 + * Copyright (C) 2013-2015 Mentor Graphics Inc.
2.11 + * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
2.12 + * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
2.13 + *
2.14 * This program is free software; you can redistribute it and/or
2.15 * modify it under the terms of the GNU General Public License as
2.16 * published by the Free Software Foundation; either version 2 of
2.17 @@ -17,10 +24,31 @@
2.18 * along with this program; if not, write to the Free Software
2.19 * Foundation, Inc., 51 Franklin Street, Fifth Floor,
2.20 * Boston, MA 02110-1301, USA
2.21 + *
2.22 + * ----
2.23 + *
2.24 + * Some acronyms:
2.25 + *
2.26 + * CEC (Consumer Electronics Control) is a HDMI device control interface for up
2.27 + * to 15 devices.
2.28 + *
2.29 + * CSC (Colour Space Conversion) is the processing needed to convert from one
2.30 + * representation of colours to another.
2.31 + *
2.32 + * HEAC (HDMI Ethernet and Audio Return Channel) is a combination of HEC (HDMI
2.33 + * Ethernet Channel) which provides a 100Mb/s bidirectional link and ARC (Audio
2.34 + * Return Channel) which permits the consumption of audio data from the device.
2.35 + *
2.36 + * MHL (Mobile High-Definition Link) is an adaptation of HDMI for mobile
2.37 + * devices.
2.38 + *
2.39 + * TMDS (Transition-Minimized Differential Signaling) is the method by which
2.40 + * audio, control and video data are all sent to the device.
2.41 */
2.42
2.43 #include <l4/devices/hdmi-jz4780.h>
2.44 #include <l4/devices/hw_mmio_register_block.h>
2.45 +#include <l4/devices/lcd-jz4740-config.h>
2.46
2.47 #include <l4/sys/irq.h>
2.48 #include <l4/util/util.h>
2.49 @@ -39,74 +67,150 @@
2.50 {
2.51 // Identification.
2.52
2.53 - Design_id = 0x000, // DESIGN_ID
2.54 - Revision_id = 0x001, // REVISION_ID
2.55 - Product_id0 = 0x002, // PRODUCT_ID0
2.56 - Product_id1 = 0x003, // PRODUCT_ID1
2.57 - Config_id0 = 0x004, // CONFIG_ID0
2.58 - Config_id1 = 0x005, // CONFIG_ID1
2.59 - Config_id2 = 0x006, // CONFIG_ID2
2.60 - Config_id3 = 0x007, // CONFIG_ID3
2.61 + Design_id = 0x000, // DESIGN_ID
2.62 + Revision_id = 0x001, // REVISION_ID
2.63 + Product_id0 = 0x002, // PRODUCT_ID0
2.64 + Product_id1 = 0x003, // PRODUCT_ID1
2.65 + Config_id0 = 0x004, // CONFIG_ID0
2.66 + Config_id1 = 0x005, // CONFIG_ID1
2.67 + Config_id2 = 0x006, // CONFIG_ID2
2.68 + Config_id3 = 0x007, // CONFIG_ID3
2.69
2.70 // Top-level interrupt control.
2.71
2.72 - Int_mask = 0x1ff, // MUTE
2.73 + Int_mask = 0x1ff, // MUTE
2.74
2.75 // Interrupt status and mask for various functions.
2.76
2.77 - Fc_int_status0 = 0x100, // FC_STAT0
2.78 - Fc_int_status1 = 0x101, // FC_STAT1
2.79 - Fc_int_status2 = 0x102, // FC_STAT2
2.80 - As_int_status = 0x103, // AS_STAT0
2.81 - Phy_int_status = 0x104, // PHY_STAT0
2.82 - Cec_int_status = 0x106, // CEC_STAT0
2.83 - Vp_int_status = 0x107, // VP_STAT0
2.84 - Ahb_dma_audio_int_status = 0x109, // AHBDMAAUD_STAT0
2.85 + Fc_int_status0 = 0x100, // FC_STAT0
2.86 + Fc_int_status1 = 0x101, // FC_STAT1
2.87 + Fc_int_status2 = 0x102, // FC_STAT2
2.88 + As_int_status = 0x103, // AS_STAT0
2.89 + Phy_int_status = 0x104, // PHY_STAT0
2.90 + Cec_int_status = 0x106, // CEC_STAT0
2.91 + Vp_int_status = 0x107, // VP_STAT0
2.92 + Ahb_dma_audio_int_status = 0x109, // AHBDMAAUD_STAT0
2.93
2.94 - Fc_int_mask0 = 0x180, // MUTE_FC_STAT0
2.95 - Fc_int_mask1 = 0x181, // MUTE_FC_STAT1
2.96 - Fc_int_mask2 = 0x182, // MUTE_FC_STAT2
2.97 - As_int_mask = 0x183, // MUTE_AS_STAT0
2.98 - Phy_int_mask = 0x184, // MUTE_PHY_STAT0
2.99 - Cec_int_mask = 0x186, // MUTE_CEC_STAT0
2.100 - Vp_int_mask = 0x187, // MUTE_VP_STAT0
2.101 - Ahb_dma_audio_int_mask = 0x189, // MUTE_AHBDMAAUD_STAT0
2.102 + Fc_int_mask0 = 0x180, // MUTE_FC_STAT0
2.103 + Fc_int_mask1 = 0x181, // MUTE_FC_STAT1
2.104 + Fc_int_mask2 = 0x182, // MUTE_FC_STAT2
2.105 + As_int_mask = 0x183, // MUTE_AS_STAT0
2.106 + Phy_int_mask = 0x184, // MUTE_PHY_STAT0
2.107 + Cec_int_mask = 0x186, // MUTE_CEC_STAT0
2.108 + Vp_int_mask = 0x187, // MUTE_VP_STAT0
2.109 + Ahb_dma_audio_int_mask = 0x189, // MUTE_AHBDMAAUD_STAT0
2.110
2.111 // I2C for E-DDC.
2.112
2.113 - I2c_int_status = 0x105, // I2CM_STAT0
2.114 - I2c_int_mask = 0x185, // MUTE_I2CM_STAT0
2.115 + I2c_int_status = 0x105, // I2CM_STAT0
2.116 + I2c_int_mask = 0x185, // MUTE_I2CM_STAT0
2.117
2.118 - I2c_device_address = 0x7e00, // I2CM_SLAVE
2.119 - I2c_register = 0x7e01, // I2CM_ADDRESS
2.120 - I2c_data_out = 0x7e02, // I2CM_DATAO
2.121 - I2c_data_in = 0x7e03, // I2CM_DATAI
2.122 - I2c_operation = 0x7e04, // I2CM_OPERATION
2.123 - I2c_int_config0 = 0x7e05, // I2CM_INT
2.124 - I2c_int_config1 = 0x7e06, // I2CM_CTLINT
2.125 - I2c_divider = 0x7e07, // I2CM_DIV
2.126 - I2c_segment_address = 0x7e08, // I2CM_SEGADDR
2.127 - I2c_software_reset = 0x7e09, // I2CM_SOFTRSTZ
2.128 - I2c_segment_pointer = 0x7e0a, // I2CM_SEGPTR
2.129 + I2c_device_address = 0x7e00, // I2CM_SLAVE
2.130 + I2c_register = 0x7e01, // I2CM_ADDRESS
2.131 + I2c_data_out = 0x7e02, // I2CM_DATAO
2.132 + I2c_data_in = 0x7e03, // I2CM_DATAI
2.133 + I2c_operation = 0x7e04, // I2CM_OPERATION
2.134 + I2c_int_config0 = 0x7e05, // I2CM_INT
2.135 + I2c_int_config1 = 0x7e06, // I2CM_CTLINT
2.136 + I2c_divider = 0x7e07, // I2CM_DIV
2.137 + I2c_segment_address = 0x7e08, // I2CM_SEGADDR
2.138 + I2c_software_reset = 0x7e09, // I2CM_SOFTRSTZ
2.139 + I2c_segment_pointer = 0x7e0a, // I2CM_SEGPTR
2.140
2.141 // I2C for PHY.
2.142
2.143 - I2c_phy_int_status = 0x108, // I2CMPHY_STAT0
2.144 - I2c_phy_int_mask = 0x188, // MUTE_I2CMPHY_STAT0
2.145 + I2c_phy_int_status = 0x108, // I2CMPHY_STAT0
2.146 + I2c_phy_int_mask = 0x188, // MUTE_I2CMPHY_STAT0
2.147
2.148 - I2c_phy_int_config0 = 0x3027, // PHY_I2CM_INT_ADDR
2.149 - I2c_phy_int_config1 = 0x3028, // PHY_I2CM_CTLINT_ADDR
2.150 + I2c_phy_device_address = 0x3020, // PHY_I2CM_SLAVE_ADDR
2.151 + I2c_phy_register = 0x3021, // PHY_I2CM_ADDRESS_ADDR
2.152 + I2c_phy_data_out1 = 0x3022, // PHY_I2CM_DATAO_1_ADDR
2.153 + I2c_phy_data_out0 = 0x3023, // PHY_I2CM_DATAO_0_ADDR
2.154 + I2c_phy_data_in1 = 0x3024, // PHY_I2CM_DATAI_1_ADDR
2.155 + I2c_phy_data_in0 = 0x3025, // PHY_I2CM_DATAI_0_ADDR
2.156 + I2c_phy_operation = 0x3026, // PHY_I2CM_OPERATION_ADDR
2.157 + I2c_phy_int_config0 = 0x3027, // PHY_I2CM_INT_ADDR
2.158 + I2c_phy_int_config1 = 0x3028, // PHY_I2CM_CTLINT_ADDR
2.159 + I2c_phy_divider = 0x3029, // PHY_I2CM_DIV_ADDR
2.160 + I2c_phy_software_reset = 0x302a, // PHY_I2CM_SOFTRSTZ_ADDR
2.161
2.162 // PHY registers.
2.163
2.164 - Phy_config = 0x3000, // PHY_CONF0
2.165 - Phy_test0 = 0x3001, // PHY_TST0
2.166 - Phy_test1 = 0x3002, // PHY_TST1
2.167 - Phy_test2 = 0x3003, // PHY_TST2
2.168 - Phy_status = 0x3004, // PHY_STAT0
2.169 - Phy_int_config = 0x3005, // PHY_INT0
2.170 - Phy_mask = 0x3006, // PHY_MASK0
2.171 - Phy_polarity = 0x3007, // PHY_POL0
2.172 + Phy_config = 0x3000, // PHY_CONF0
2.173 + Phy_test0 = 0x3001, // PHY_TST0
2.174 + Phy_test1 = 0x3002, // PHY_TST1
2.175 + Phy_test2 = 0x3003, // PHY_TST2
2.176 + Phy_status = 0x3004, // PHY_STAT0
2.177 + Phy_int_config = 0x3005, // PHY_INT0
2.178 + Phy_mask = 0x3006, // PHY_MASK0
2.179 + Phy_polarity = 0x3007, // PHY_POL0
2.180 +
2.181 + // Main controller registers.
2.182 +
2.183 + Main_clock_disable = 0x4001, // MC_CLKDIS
2.184 + Main_software_reset = 0x4002, // MC_SWRSTZ
2.185 + Main_flow_control = 0x4004, // MC_FLOWCTRL
2.186 + Main_reset = 0x4005, // MC_PHYRSTZ
2.187 + Main_heac_phy_reset = 0x4007, // MC_HEACPHY_RST
2.188 +
2.189 + // Frame composer registers for input video.
2.190 +
2.191 + Fc_video_config = 0x1000, // FC_INVIDCONF
2.192 + Fc_horizontal_active_width0 = 0x1001, // FC_INHACTV0
2.193 + Fc_horizontal_active_width1 = 0x1002, // FC_INHACTV1
2.194 + Fc_horizontal_blank_width0 = 0x1003, // FC_INHBLANK0
2.195 + Fc_horizontal_blank_width1 = 0x1004, // FC_INHBLANK1
2.196 + Fc_vertical_active_height0 = 0x1005, // FC_INVACTV0
2.197 + Fc_vertical_active_height1 = 0x1006, // FC_INVACTV1
2.198 + Fc_vertical_blank_height = 0x1007, // FC_INVBLANK
2.199 +
2.200 + // Frame composer registers for sync pulses.
2.201 +
2.202 + Fc_hsync_delay0 = 0x1008, // FC_HSYNCINDELAY0
2.203 + Fc_hsync_delay1 = 0x1009, // FC_HSYNCINDELAY1
2.204 + Fc_hsync_width0 = 0x100A, // FC_HSYNCINWIDTH0
2.205 + Fc_hsync_width1 = 0x100B, // FC_HSYNCINWIDTH1
2.206 + Fc_vsync_delay = 0x100C, // FC_VSYNCINDELAY
2.207 + Fc_vsync_height = 0x100D, // FC_VSYNCINWIDTH
2.208 +
2.209 + // Frame composer registers for video path configuration.
2.210 +
2.211 + Fc_control_duration = 0x1011, // FC_CTRLDUR
2.212 + Fc_ex_control_duration = 0x1012, // FC_EXCTRLDUR
2.213 + Fc_ex_control_space = 0x1013, // FC_EXCTRLSPAC
2.214 + Fc_channel0_preamble = 0x1014, // FC_CH0PREAM
2.215 + Fc_channel1_preamble = 0x1015, // FC_CH1PREAM
2.216 + Fc_channel2_preamble = 0x1016, // FC_CH2PREAM
2.217 +
2.218 + // Colour space conversion registers.
2.219 +
2.220 + Csc_config = 0x4100, // CSC_CFG
2.221 + Csc_scale = 0x4101, // CSC_SCALE
2.222 +
2.223 + // HDCP registers.
2.224 +
2.225 + Hdcp_config0 = 0x5000, // A_HDCPCFG0
2.226 + Hdcp_config1 = 0x5001, // A_HDCPCFG1
2.227 + Hdcp_video_polarity = 0x5009, // A_VIDPOLCFG
2.228 +
2.229 + // Video sample registers.
2.230 +
2.231 + Sample_video_config = 0x0200, // TX_INVID0
2.232 + Sample_video_stuffing = 0x0201, // TX_INSTUFFING
2.233 + Sample_gy_data0 = 0x0202, // TX_GYDATA0
2.234 + Sample_gy_data1 = 0x0203, // TX_GYDATA1
2.235 + Sample_rcr_data0 = 0x0204, // TX_RCRDATA0
2.236 + Sample_rcr_data1 = 0x0205, // TX_RCRDATA1
2.237 + Sample_bcb_data0 = 0x0206, // TX_BCBDATA0
2.238 + Sample_bcb_data1 = 0x0207, // TX_BCBDATA1
2.239 +
2.240 + // Video packetizer registers.
2.241 +
2.242 + Packet_status = 0x0800, // VP_STATUS
2.243 + Packet_pixel_repeater = 0x0801, // VP_PR_CD
2.244 + Packet_stuffing = 0x0802, // VP_STUFF
2.245 + Packet_remap = 0x0803, // VP_REMAP
2.246 + Packet_config = 0x0804, // VP_CONF
2.247 };
2.248
2.249 // Identification values.
2.250 @@ -149,6 +253,8 @@
2.251 Int_mask_all = 0x01,
2.252 };
2.253
2.254 +// I2C status and mask bits, also for PHY I2C.
2.255 +
2.256 enum I2c_int_status_bits : unsigned
2.257 {
2.258 I2c_int_status_done = 0x02,
2.259 @@ -160,38 +266,73 @@
2.260 enum I2c_operation_bits : unsigned
2.261 {
2.262 I2c_operation_write = 0x10,
2.263 - I2c_operation_segment_read = 0x02,
2.264 + I2c_operation_segment_read = 0x02, // not PHY I2C
2.265 I2c_operation_read = 0x01,
2.266 };
2.267
2.268 -// Interrupt configuration bits.
2.269 +// Device addresses.
2.270 +
2.271 +enum I2c_phy_device_addresses : unsigned
2.272 +{
2.273 + I2c_phy_device_phy_gen2 = 0x69, // PHY_I2CM_SLAVE_ADDR_PHY_GEN2
2.274 + I2c_phy_device_phy_heac = 0x49, // PHY_I2CM_SLAVE_ADDR_HEAC_PHY
2.275 +};
2.276 +
2.277 +// Device registers.
2.278 +
2.279 +enum I2c_phy_device_registers : unsigned
2.280 +{
2.281 + I2c_phy_3d_tx_clock_cal_ctrl = 0x05, // 3D_TX_PHY_CKCALCTRL
2.282 + I2c_phy_3d_tx_cpce_ctrl = 0x06, // 3D_TX_PHY_CPCE_CTRL
2.283 + I2c_phy_3d_tx_clock_symbol_ctrl = 0x09, // 3D_TX_PHY_CKSYMTXCTRL
2.284 + I2c_phy_3d_tx_vlevel_ctrl = 0x0e, // 3D_TX_PHY_VLEVCTRL
2.285 + I2c_phy_3d_tx_curr_ctrl = 0x10, // 3D_TX_PHY_CURRCTRL
2.286 + I2c_phy_3d_tx_pll_phby_ctrl = 0x13, // 3D_TX_PHY_PLLPHBYCTRL
2.287 + I2c_phy_3d_tx_gmp_ctrl = 0x15, // 3D_TX_PHY_GMPCTRL
2.288 + I2c_phy_3d_tx_msm_ctrl = 0x17, // 3D_TX_PHY_MSM_CTRL
2.289 + I2c_phy_3d_tx_term = 0x19, // 3D_TX_PHY_TXTERM
2.290 +};
2.291 +
2.292 +// PHY I2C register values.
2.293 +
2.294 +enum Msm_ctrl_bits : unsigned
2.295 +{
2.296 + Msm_ctrl_clock_output_select_fb = 1 << 3, // 3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK
2.297 +};
2.298 +
2.299 +enum Clock_cal_ctrl_bits : unsigned
2.300 +{
2.301 + Clock_cal_ctrl_override = 1 << 15, // 3D_TX_PHY_CKCALCTRL_OVERRIDE
2.302 +};
2.303 +
2.304 +// Interrupt configuration bits, also for PHY I2C.
2.305
2.306 enum I2c_int_config0_bits : unsigned
2.307 {
2.308 - I2c_int_config0_done_polarity = 0x08,
2.309 - I2c_int_config0_done_mask = 0x04,
2.310 + I2c_int_config0_done_polarity = 0x08,
2.311 + I2c_int_config0_done_mask = 0x04,
2.312 };
2.313
2.314 enum I2c_int_config1_bits : unsigned
2.315 {
2.316 - I2c_int_config1_nack_polarity = 0x80,
2.317 - I2c_int_config1_nack_mask = 0x40,
2.318 - I2c_int_config1_arb_polarity = 0x08,
2.319 - I2c_int_config1_arb_mask = 0x04,
2.320 + I2c_int_config1_nack_polarity = 0x80,
2.321 + I2c_int_config1_nack_mask = 0x40,
2.322 + I2c_int_config1_arb_polarity = 0x08,
2.323 + I2c_int_config1_arb_mask = 0x04,
2.324 };
2.325
2.326 // PHY configuration values.
2.327
2.328 enum Phy_config_bits : unsigned
2.329 {
2.330 - Phy_config_pdz_mask = 0x80, // PHY_CONF0_PDZ_MASK
2.331 - Phy_config_enable_tmds_mask = 0x40, // PHY_CONF0_ENTMDS_MASK
2.332 - Phy_config_svsret_mask = 0x20, // PHY_CONF0_SVSRET_MASK
2.333 - Phy_config_gen2_pddq_mask = 0x10, // PHY_CONF0_GEN2_PDDQ_MASK
2.334 - Phy_config_gen2_tx_power_on_mask = 0x08, // PHY_CONF0_GEN2_TXPWRON_MASK
2.335 - Phy_config_gen2_enable_hotplug_detect_rx_sense_mask = 0x04, // PHY_CONF0_GEN2_ENHPDRXSENSE_MASK
2.336 - Phy_config_select_data_enable_polarity_mask = 0x02, // PHY_CONF0_SELDATAENPOL_MASK
2.337 - Phy_config_select_interface_control_mask = 0x01, // PHY_CONF0_SELDIPIF_MASK
2.338 + Phy_config_powerdown_disable = 0x80, // PHY_CONF0_PDZ_MASK
2.339 + Phy_config_tmds = 0x40, // PHY_CONF0_ENTMDS_MASK
2.340 + Phy_config_svsret = 0x20, // PHY_CONF0_SVSRET_MASK
2.341 + Phy_config_gen2_powerdown = 0x10, // PHY_CONF0_GEN2_PDDQ_MASK
2.342 + Phy_config_gen2_tx_power = 0x08, // PHY_CONF0_GEN2_TXPWRON_MASK
2.343 + Phy_config_gen2_hotplug_detect_rx_sense = 0x04, // PHY_CONF0_GEN2_ENHPDRXSENSE_MASK
2.344 + Phy_config_select_data_enable_polarity = 0x02, // PHY_CONF0_SELDATAENPOL_MASK
2.345 + Phy_config_select_interface_control = 0x01, // PHY_CONF0_SELDIPIF_MASK
2.346 };
2.347
2.348 enum Phy_test_bits : unsigned
2.349 @@ -205,6 +346,7 @@
2.350
2.351 enum Phy_status_bits : unsigned
2.352 {
2.353 + Phy_status_all = 0xf3,
2.354 Phy_status_rx_sense_all = 0xf0,
2.355 Phy_status_rx_sense3 = 0x80, // PHY_RX_SENSE3
2.356 Phy_status_rx_sense2 = 0x40, // PHY_RX_SENSE2
2.357 @@ -212,12 +354,14 @@
2.358 Phy_status_rx_sense0 = 0x10, // PHY_RX_SENSE0
2.359 Phy_status_hotplug_detect = 0x02, // PHY_HPD
2.360 Phy_status_tx_phy_lock = 0x01, // PHY_TX_PHY_LOCK
2.361 + Phy_status_none = 0,
2.362 };
2.363
2.364 -// PHY interrupt status and mask bits.
2.365 +// PHY interrupt status and mask values.
2.366
2.367 enum Phy_int_status_bits : unsigned
2.368 {
2.369 + Phy_int_status_all = 0x3f,
2.370 Phy_int_status_rx_sense_all = 0x3c,
2.371 Phy_int_status_rx_sense3 = 0x20, // IH_PHY_STAT0_RX_SENSE3
2.372 Phy_int_status_rx_sense2 = 0x10, // IH_PHY_STAT0_RX_SENSE2
2.373 @@ -225,6 +369,202 @@
2.374 Phy_int_status_rx_sense0 = 0x04, // IH_PHY_STAT0_RX_SENSE0
2.375 Phy_int_status_tx_phy_lock = 0x02, // IH_PHY_STAT0_TX_PHY_LOCK
2.376 Phy_int_status_hotplug_detect = 0x01, // IH_PHY_STAT0_HPD
2.377 + Phy_int_status_none = 0,
2.378 +};
2.379 +
2.380 +// PHY main register values.
2.381 +
2.382 +enum Main_heac_phy_reset_bits : unsigned
2.383 +{
2.384 + Main_heac_phy_reset_assert = 0x01, // MC_HEACPHY_RST_ASSERT
2.385 +};
2.386 +
2.387 +enum Main_flow_control_bits : unsigned
2.388 +{
2.389 + Main_flow_control_csc_active = 0x01, // MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH
2.390 + Main_flow_control_csc_inactive = 0x00, // MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS
2.391 +};
2.392 +
2.393 +enum Main_clock_disable_bits : unsigned
2.394 +{
2.395 + Main_clock_disable_hdcp = 0x40, // MC_CLKDIS_HDCPCLK_DISABLE
2.396 + Main_clock_disable_cec = 0x20, // MC_CLKDIS_CECCLK_DISABLE
2.397 + Main_clock_disable_csc = 0x10, // MC_CLKDIS_CSCCLK_DISABLE
2.398 + Main_clock_disable_audio = 0x08, // MC_CLKDIS_AUDCLK_DISABLE
2.399 + Main_clock_disable_prep = 0x04, // MC_CLKDIS_PREPCLK_DISABLE
2.400 + Main_clock_disable_tmds = 0x02, // MC_CLKDIS_TMDSCLK_DISABLE
2.401 + Main_clock_disable_pixel = 0x01, // MC_CLKDIS_PIXELCLK_DISABLE
2.402 +};
2.403 +
2.404 +// Frame composer values.
2.405 +
2.406 +enum Fc_video_config_bits : unsigned
2.407 +{
2.408 + Fc_video_config_hdcp_keepout_active = 0x80, // FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE
2.409 + Fc_video_config_hdcp_keepout_inactive = 0x00, // FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE
2.410 + Fc_video_config_vsync_active_high = 0x40, // FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH
2.411 + Fc_video_config_vsync_active_low = 0x00, // FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW
2.412 + Fc_video_config_hsync_active_high = 0x20, // FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH
2.413 + Fc_video_config_hsync_active_low = 0x00, // FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW
2.414 + Fc_video_config_data_enable_active_high = 0x10, // FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH
2.415 + Fc_video_config_data_enable_active_low = 0x00, // FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW
2.416 + Fc_video_config_hdmi_mode = 0x08, // FC_INVIDCONF_DVI_MODEZ_HDMI_MODE
2.417 + Fc_video_config_dvi_mode = 0x00, // FC_INVIDCONF_DVI_MODEZ_DVI_MODE
2.418 + Fc_video_config_osc_active_high = 0x02, // FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH
2.419 + Fc_video_config_osc_active_low = 0x00, // FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW
2.420 + Fc_video_config_interlaced = 0x01, // FC_INVIDCONF_IN_I_P_INTERLACED
2.421 + Fc_video_config_progressive = 0x00, // FC_INVIDCONF_IN_I_P_PROGRESSIVE
2.422 +};
2.423 +
2.424 +enum Fc_int_status2_bits : unsigned
2.425 +{
2.426 + Fc_int_status2_overflow = 0x03, // FC_STAT2_OVERFLOW_MASK
2.427 + Fc_int_status2_overflow_low = 0x02, // FC_STAT2_LOW_PRIORITY_OVERFLOW
2.428 + Fc_int_status2_overflow_high = 0x01 // FC_STAT2_HIGH_PRIORITY_OVERFLOW,
2.429 +};
2.430 +
2.431 +// Colour space conversion values.
2.432 +
2.433 +enum Csc_config_bits : unsigned
2.434 +{
2.435 + Csc_config_interpolation_mask = 0x30, // CSC_CFG_INTMODE_MASK
2.436 + Csc_config_interpolation_disable = 0x00, // CSC_CFG_INTMODE_DISABLE
2.437 + Csc_config_interpolation_form1 = 0x10, // CSC_CFG_INTMODE_CHROMA_INT_FORMULA1
2.438 + Csc_config_interpolation_form2 = 0x20, // CSC_CFG_INTMODE_CHROMA_INT_FORMULA2
2.439 + Csc_config_decimation_mask = 0x3, // CSC_CFG_DECMODE_MASK
2.440 + Csc_config_decimation_disable = 0x0, // CSC_CFG_DECMODE_DISABLE
2.441 + Csc_config_decimation_form1 = 0x1, // CSC_CFG_DECMODE_CHROMA_INT_FORMULA1
2.442 + Csc_config_decimation_form2 = 0x2, // CSC_CFG_DECMODE_CHROMA_INT_FORMULA2
2.443 + Csc_config_decimation_form3 = 0x3, // CSC_CFG_DECMODE_CHROMA_INT_FORMULA3
2.444 +};
2.445 +
2.446 +enum Csc_scale_bits : unsigned
2.447 +{
2.448 + Csc_scale_colour_depth_mask = 0xf0, // CSC_SCALE_CSC_COLORDE_PTH_MASK
2.449 + Csc_scale_colour_depth_24bpp = 0x00, // CSC_SCALE_CSC_COLORDE_PTH_24BPP
2.450 + Csc_scale_colour_depth_30bpp = 0x50, // CSC_SCALE_CSC_COLORDE_PTH_30BPP
2.451 + Csc_scale_colour_depth_36bpp = 0x60, // CSC_SCALE_CSC_COLORDE_PTH_36BPP
2.452 + Csc_scale_colour_depth_48bpp = 0x70, // CSC_SCALE_CSC_COLORDE_PTH_48BPP
2.453 + Csc_scale_mask = 0x03, // CSC_SCALE_CSCSCALE_MASK
2.454 +};
2.455 +
2.456 +// HDCP register values.
2.457 +
2.458 +enum Hdcp_config0_bits : unsigned
2.459 +{
2.460 + Hdcp_config0_rxdetect_enable = 0x4, // A_HDCPCFG0_RXDETECT_ENABLE
2.461 +};
2.462 +
2.463 +enum Hdcp_config1_bits : unsigned
2.464 +{
2.465 + Hdcp_config1_encryption_disable = 0x2, // A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE
2.466 +};
2.467 +
2.468 +enum Hdcp_video_polarity_bits : unsigned
2.469 +{
2.470 + Hdcp_video_polarity_data_enable_active_high = 0x10, // A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH
2.471 +};
2.472 +
2.473 +// Video sample register values.
2.474 +
2.475 +enum Sample_video_config_bits : unsigned
2.476 +{
2.477 + Sample_video_config_data_enable_active = 0x80, // TX_INVID0_INTERNAL_DE_GENERATOR_ENABLE
2.478 + Sample_video_config_mapping_mask = 0x1f, // TX_INVID0_VIDEO_MAPPING_MASK
2.479 +};
2.480 +
2.481 +enum Sample_video_stuffing_bits : unsigned
2.482 +{
2.483 + Sample_video_stuffing_bdb_data = 0x04, // TX_INSTUFFING_BDBDATA_STUFFING_ENABLE
2.484 + Sample_video_stuffing_rcr_data = 0x02, // TX_INSTUFFING_RCRDATA_STUFFING_ENABLE
2.485 + Sample_video_stuffing_gy_data = 0x01, // TX_INSTUFFING_GYDATA_STUFFING_ENABLE
2.486 +};
2.487 +
2.488 +// Video packetizer register values.
2.489 +
2.490 +enum Packet_stuffing_bits : unsigned
2.491 +{
2.492 + Packet_stuffing_default_phase = 0x20, // VP_STUFF_IDEFAULT_PHASE_MASK
2.493 + Packet_stuffing_ifix_pp_to_last = 0x10, // VP_STUFF_IFIX_PP_TO_LAST_MASK
2.494 + Packet_stuffing_icx = 0x08, // VP_STUFF_ICX_GOTO_P0_ST_MASK
2.495 + Packet_stuffing_ycc422 = 0x04, // VP_STUFF_YCC422_STUFFING_STUFFING_MODE
2.496 + Packet_stuffing_pp = 0x02, // VP_STUFF_PP_STUFFING_STUFFING_MODE
2.497 + Packet_stuffing_pr = 0x01, // VP_STUFF_PR_STUFFING_STUFFING_MODE
2.498 +};
2.499 +
2.500 +enum Packet_config_bits : unsigned
2.501 +{
2.502 + Packet_config_bypass_enable = 0x40, // VP_CONF_BYPASS_EN_ENABLE
2.503 + Packet_config_pp_enable = 0x20, // VP_CONF_PP_EN_ENABLE
2.504 + Packet_config_pr_enable = 0x10, // VP_CONF_PR_EN_ENABLE
2.505 + Packet_config_ycc422_enable = 0x8, // VP_CONF_YCC422_EN_ENABLE
2.506 + Packet_config_bypass_select_packetizer = 0x4, // VP_CONF_BYPASS_SELECT_VID_PACKETIZER
2.507 + Packet_config_output_selector_mask = 0x3, // VP_CONF_OUTPUT_SELECTOR_MASK
2.508 + Packet_config_output_selector_bypass = 0x3, // VP_CONF_OUTPUT_SELECTOR_BYPASS
2.509 + Packet_config_output_selector_ycc422 = 0x1, // VP_CONF_OUTPUT_SELECTOR_YCC422
2.510 + Packet_config_output_selector_pp = 0x0, // VP_CONF_OUTPUT_SELECTOR_PP
2.511 +};
2.512 +
2.513 +enum Packet_remap_bits : unsigned
2.514 +{
2.515 + Packet_remap_mask = 0x3, // VP_REMAP_MASK
2.516 + Packet_remap_ycc422_24bit = 0x2, // VP_REMAP_YCC422_24bit
2.517 + Packet_remap_ycc422_20bit = 0x1, // VP_REMAP_YCC422_20bit
2.518 + Packet_remap_ycc422_16bit = 0x0, // VP_REMAP_YCC422_16bit
2.519 +};
2.520 +
2.521 +enum Packet_pixel_repeater_bits : unsigned
2.522 +{
2.523 + Packet_pixel_repeater_depth_mask = 0xf0, // VP_PR_CD_COLOR_DEPTH_MASK
2.524 + Packet_pixel_repeater_depth_offset = 4, // VP_PR_CD_COLOR_DEPTH_OFFSET
2.525 + Packet_pixel_repeater_factor_mask = 0x0f, // VP_PR_CD_DESIRED_PR_FACTOR_MASK
2.526 + Packet_pixel_repeater_factor_offset = 0, // VP_PR_CD_DESIRED_PR_FACTOR_OFFSET
2.527 +};
2.528 +
2.529 +
2.530 +
2.531 +// PHY capabilities.
2.532 +
2.533 +static const Phy_capabilities phy_capabilities[] = {
2.534 + // name gen svsret configure
2.535 + {Config2_dwc_hdmi_tx_phy, "DWC_HDMI_TX_PHY", 1, false, false},
2.536 + {Config2_dwc_mhl_phy_heac, "DWC_MHL_PHY_HEAC", 2, true, true},
2.537 + {Config2_dwc_mhl_phy, "DWC_MHL_PHY", 2, true, true},
2.538 + {Config2_dwc_hdmi_3d_tx_phy_heac, "DWC_HDMI_3D_TX_PHY_HEAC", 2, false, true},
2.539 + {Config2_dwc_hdmi_3d_tx_phy, "DWC_HDMI_3D_TX_PHY", 2, false, true},
2.540 + {Config2_dwc_hdmi20_tx_phy, "DWC_HDMI20_TX_PHY", 2, true, true},
2.541 + {0, "Vendor PHY", 0, false, false},
2.542 + };
2.543 +
2.544 +
2.545 +
2.546 +// PHY configuration, adopting the Linux driver's tables of values.
2.547 +
2.548 +static const struct Phy_mpll_config phy_mpll_config[] = {
2.549 + // 8bpc 10bpc 12bpc
2.550 + // pixelclock cpce gmp cpce gmp cpce gmp
2.551 + { 45250000, { {0x01e0, 0x0000}, {0x21e1, 0x0000}, {0x41e2, 0x0000} } },
2.552 + { 92500000, { {0x0140, 0x0005}, {0x2141, 0x0005}, {0x4142, 0x0005} } },
2.553 + { 148500000, { {0x00a0, 0x000a}, {0x20a1, 0x000a}, {0x40a2, 0x000a} } },
2.554 + { 216000000, { {0x00a0, 0x000a}, {0x2001, 0x000f}, {0x4002, 0x000f} } },
2.555 + { ~0UL, { {0x0000, 0x0000}, {0x0000, 0x0000}, {0x0000, 0x0000} } }
2.556 +};
2.557 +
2.558 +static const struct Phy_curr_ctrl phy_curr_ctrl[] = {
2.559 + // pixelclock 8bpc 10bpc 12bpc
2.560 + { 54000000, {0x091c, 0x091c, 0x06dc} },
2.561 + { 58400000, {0x091c, 0x06dc, 0x06dc} },
2.562 + { 72000000, {0x06dc, 0x06dc, 0x091c} },
2.563 + { 74250000, {0x06dc, 0x0b5c, 0x091c} },
2.564 + { 118800000, {0x091c, 0x091c, 0x06dc} },
2.565 + { 216000000, {0x06dc, 0x0b5c, 0x091c} },
2.566 + { ~0UL, {0x0000, 0x0000, 0x0000} }
2.567 +};
2.568 +
2.569 +static const struct Phy_config phy_config[] = {
2.570 + // pixelclock symbol term vlevel
2.571 + { 216000000, 0x800d, 0x0005, 0x01ad},
2.572 + { ~0UL, 0x0000, 0x0000, 0x0000}
2.573 };
2.574
2.575
2.576 @@ -232,33 +572,114 @@
2.577 // Initialise the HDMI peripheral.
2.578
2.579 Hdmi_jz4780_chip::Hdmi_jz4780_chip(l4_addr_t start, l4_addr_t end,
2.580 - l4_cap_idx_t irq)
2.581 -: _start(start), _end(end), _irq(irq)
2.582 + l4_cap_idx_t irq,
2.583 + struct Jz4740_lcd_panel *panel)
2.584 +: _start(start), _end(end), _irq(irq), _panel(panel)
2.585 {
2.586 // 8-bit registers with 2-bit address shifting.
2.587
2.588 _regs = new Hw::Mmio_register_block<8>(start, 2);
2.589
2.590 + // Initialise I2C state for DDC.
2.591 +
2.592 _segment_read = false;
2.593 _device_register = 0;
2.594
2.595 + // Initialise I2C state for PHY initialisation.
2.596 +
2.597 + _phy_device_register = 0;
2.598 +
2.599 + // Initialise identifying details and capabilities of the hardware.
2.600 +
2.601 get_identification();
2.602 +
2.603 + // Reset interrupts to a minimal, enabled state.
2.604 +
2.605 irq_init();
2.606 - i2c_init();
2.607 - hotplug_init();
2.608 +
2.609 + // Set up DDC and PHY communication.
2.610 +
2.611 + i2c_init(I2c_software_reset, I2c_divider, I2c_int_config0, I2c_int_config1,
2.612 + I2c_int_status, I2c_int_mask);
2.613 + i2c_init(I2c_phy_software_reset, I2c_phy_divider, I2c_phy_int_config0, I2c_phy_int_config1,
2.614 + I2c_phy_int_status, I2c_phy_int_mask);
2.615 +
2.616 + // Enable PHY interrupts.
2.617 +
2.618 + phy_irq_init();
2.619 +}
2.620 +
2.621 +// Pixel clock frequency calculation.
2.622 +
2.623 +unsigned long Hdmi_jz4780_chip::get_pixelclock()
2.624 +{
2.625 + return _pixelclock;
2.626 +
2.627 +/* Calculated frequency, which may not be the actual pixelclock frequency...
2.628 +
2.629 + return (_panel->line_start + _panel->width + _panel->line_end + _panel->hsync) *
2.630 + (_panel->frame_start + _panel->height + _panel->frame_end + _panel->vsync) *
2.631 + _panel->frame_rate;
2.632 +*/
2.633 }
2.634
2.635 +
2.636 +
2.637 +// Update a register by enabling/setting or disabling/clearing the given bits.
2.638 +
2.639 +void Hdmi_jz4780_chip::reg_update(uint32_t reg, uint32_t bits, bool enable)
2.640 +{
2.641 + if (enable)
2.642 + _regs[reg] = _regs[reg] | bits;
2.643 + else
2.644 + _regs[reg] = _regs[reg] & ~bits;
2.645 +}
2.646 +
2.647 +// Update a field. The bits must be shifted to coincide with the mask.
2.648 +
2.649 +void Hdmi_jz4780_chip::reg_update_field(uint32_t reg, uint32_t mask, uint32_t bits)
2.650 +{
2.651 + _regs[reg] = (_regs[reg] & ~(mask)) | (bits & mask);
2.652 +}
2.653 +
2.654 +void Hdmi_jz4780_chip::reg_fill_field(uint32_t reg, uint32_t mask)
2.655 +{
2.656 + _regs[reg] = _regs[reg] | mask;
2.657 +}
2.658 +
2.659 +
2.660 +
2.661 +// Chipset querying.
2.662 +
2.663 void Hdmi_jz4780_chip::get_identification()
2.664 {
2.665 _version = (_regs[Design_id] << 8) | _regs[Revision_id];
2.666 + _phy_type = _regs[Config_id2];
2.667 +
2.668 + // Initialise a member to any matching capabilities or leave it as the "null"
2.669 + // entry.
2.670 +
2.671 + _phy_def = phy_capabilities;
2.672 +
2.673 + while (_phy_def->gen && (_phy_def->type != _phy_type))
2.674 + _phy_def++;
2.675 }
2.676
2.677 void Hdmi_jz4780_chip::get_version(uint8_t *major, uint16_t *minor)
2.678 {
2.679 - *major = _version >> 12;
2.680 + *major = (_version >> 12) & 0xfff;
2.681 *minor = _version & 0xfff;
2.682 }
2.683
2.684 +void Hdmi_jz4780_chip::get_phy_capabilities(const struct Phy_capabilities **phy_def)
2.685 +{
2.686 + *phy_def = _phy_def;
2.687 +}
2.688 +
2.689 +
2.690 +
2.691 +// Initialisation.
2.692 +
2.693 void Hdmi_jz4780_chip::irq_init()
2.694 {
2.695 // Disable interrupts.
2.696 @@ -273,9 +694,9 @@
2.697 _regs[As_int_mask] = 0xff;
2.698 _regs[Phy_int_mask] = 0xff;
2.699 _regs[I2c_int_mask] = 0xff;
2.700 + _regs[I2c_phy_int_mask] = 0xff;
2.701 _regs[Cec_int_mask] = 0xff;
2.702 _regs[Vp_int_mask] = 0xff;
2.703 - _regs[I2c_phy_int_mask] = 0xff;
2.704 _regs[Ahb_dma_audio_int_mask] = 0xff;
2.705
2.706 // Enable interrupts.
2.707 @@ -283,35 +704,53 @@
2.708 _regs[Int_mask] = _regs[Int_mask] & ~(Int_mask_wakeup | Int_mask_all);
2.709 }
2.710
2.711 -void Hdmi_jz4780_chip::i2c_init()
2.712 +void Hdmi_jz4780_chip::phy_irq_init()
2.713 {
2.714 // Set PHY interrupt polarities.
2.715
2.716 - _regs[I2c_phy_int_config0] = I2c_int_config0_done_polarity;
2.717 - _regs[I2c_phy_int_config1] = I2c_int_config1_nack_polarity |
2.718 - I2c_int_config1_arb_polarity;
2.719 + _regs[Phy_polarity] = Phy_status_all;
2.720 +
2.721 + // Enable/unmask second-level interrupts.
2.722 +
2.723 + _regs[Phy_mask] = _regs[Phy_mask] & ~(Phy_status_all);
2.724 +
2.725 + // Clear pending interrupts.
2.726 +
2.727 + _regs[Phy_int_status] = Phy_int_status_all;
2.728 +
2.729 + // Enable/unmask interrupts.
2.730
2.731 + _regs[Phy_int_mask] = _regs[Phy_int_mask] & ~(Phy_int_status_all);
2.732 +}
2.733 +
2.734 +
2.735 +
2.736 +// I2C support.
2.737 +
2.738 +void Hdmi_jz4780_chip::i2c_init(uint32_t reset, uint32_t divider,
2.739 + uint32_t config0, uint32_t config1,
2.740 + uint32_t status, uint32_t mask)
2.741 +{
2.742 // Software reset.
2.743
2.744 - _regs[I2c_software_reset] = 0;
2.745 + _regs[reset] = 0;
2.746
2.747 // Standard mode (100kHz).
2.748
2.749 - _regs[I2c_divider] = 0;
2.750 + _regs[divider] = 0;
2.751
2.752 // Set interrupt polarities.
2.753
2.754 - _regs[I2c_int_config0] = I2c_int_config0_done_polarity;
2.755 - _regs[I2c_int_config1] = I2c_int_config1_nack_polarity |
2.756 - I2c_int_config1_arb_polarity;
2.757 + _regs[config0] = I2c_int_config0_done_polarity;
2.758 + _regs[config1] = I2c_int_config1_nack_polarity | I2c_int_config1_arb_polarity;
2.759
2.760 // Clear and mask/mute interrupts.
2.761
2.762 - _regs[I2c_int_status] = I2c_int_status_done | I2c_int_status_error;
2.763 - _regs[I2c_int_mask] = I2c_int_status_done | I2c_int_status_error;
2.764 + _regs[status] = I2c_int_status_done | I2c_int_status_error;
2.765 + _regs[mask] = I2c_int_status_done | I2c_int_status_error;
2.766 }
2.767
2.768 -long Hdmi_jz4780_chip::i2c_wait()
2.769 +long Hdmi_jz4780_chip::i2c_wait(uint32_t status)
2.770 {
2.771 long err;
2.772 uint8_t int_status;
2.773 @@ -325,7 +764,7 @@
2.774 if (err)
2.775 return err;
2.776
2.777 - int_status = _regs[I2c_int_status];
2.778 + int_status = _regs[status];
2.779
2.780 // Test for an error condition.
2.781
2.782 @@ -334,7 +773,7 @@
2.783
2.784 // Acknowledge the interrupt.
2.785
2.786 - _regs[I2c_int_status] = int_status;
2.787 + _regs[status] = int_status;
2.788
2.789 } while (!(int_status & I2c_int_status_done));
2.790
2.791 @@ -360,7 +799,7 @@
2.792
2.793 // Wait and then read.
2.794
2.795 - err = i2c_wait();
2.796 + err = i2c_wait(I2c_int_status);
2.797 if (err)
2.798 break;
2.799
2.800 @@ -374,6 +813,45 @@
2.801 return i;
2.802 }
2.803
2.804 +int Hdmi_jz4780_chip::i2c_phy_write(uint8_t address, uint16_t value)
2.805 +{
2.806 + i2c_phy_set_address(address);
2.807 + return i2c_phy_write(&value, 1);
2.808 +}
2.809 +
2.810 +int Hdmi_jz4780_chip::i2c_phy_write(uint16_t *buf, unsigned int length)
2.811 +{
2.812 + unsigned int i;
2.813 + long err;
2.814 +
2.815 + // Unmask interrupts.
2.816 +
2.817 + _regs[I2c_phy_int_mask] = 0;
2.818 +
2.819 + for (i = 0; i < length; i++)
2.820 + {
2.821 + // Increment the device register.
2.822 +
2.823 + _regs[I2c_phy_register] = _device_register++;
2.824 + _regs[I2c_phy_operation] = I2c_operation_write;
2.825 +
2.826 + // Write and then wait.
2.827 +
2.828 + _regs[I2c_phy_data_out1] = (buf[i] >> 8) & 0xff;
2.829 + _regs[I2c_phy_data_out0] = buf[i] & 0xff;
2.830 +
2.831 + err = i2c_wait(I2c_phy_int_status);
2.832 + if (err)
2.833 + break;
2.834 + }
2.835 +
2.836 + // Mask interrupts again.
2.837 +
2.838 + _regs[I2c_phy_int_mask] = I2c_int_status_done | I2c_int_status_error;
2.839 +
2.840 + return i;
2.841 +}
2.842 +
2.843 void Hdmi_jz4780_chip::i2c_set_address(uint8_t address)
2.844 {
2.845 _regs[I2c_device_address] = address;
2.846 @@ -381,6 +859,18 @@
2.847 i2c_set_register(0);
2.848 }
2.849
2.850 +void Hdmi_jz4780_chip::i2c_phy_set_address(uint8_t address)
2.851 +{
2.852 + // The Linux drivers seem to set the clear field when changing the PHY device
2.853 + // address, presumably because some manual says so.
2.854 +
2.855 + _regs[Phy_test0] = _regs[Phy_test0] | Phy_test0_clear_mask;
2.856 + _regs[I2c_phy_device_address] = address;
2.857 + _regs[Phy_test0] = _regs[Phy_test0] & ~Phy_test0_clear_mask;
2.858 +
2.859 + i2c_phy_set_register(0);
2.860 +}
2.861 +
2.862 void Hdmi_jz4780_chip::i2c_set_segment(uint8_t segment)
2.863 {
2.864 _regs[I2c_segment_address] = 0x30;
2.865 @@ -394,25 +884,197 @@
2.866 _device_register = device_register;
2.867 }
2.868
2.869 -void Hdmi_jz4780_chip::hotplug_init()
2.870 +void Hdmi_jz4780_chip::i2c_phy_set_register(uint8_t device_register)
2.871 +{
2.872 + _phy_device_register = device_register;
2.873 +}
2.874 +
2.875 +
2.876 +
2.877 +// PHY operations.
2.878 +
2.879 +void Hdmi_jz4780_chip::phy_enable_powerdown(bool enable)
2.880 +{
2.881 + reg_update(Phy_config, Phy_config_powerdown_disable, !enable);
2.882 +}
2.883 +
2.884 +void Hdmi_jz4780_chip::phy_enable_tmds(bool enable)
2.885 +{
2.886 + reg_update(Phy_config, Phy_config_tmds, enable);
2.887 +}
2.888 +
2.889 +void Hdmi_jz4780_chip::phy_enable_svsret(bool enable)
2.890 {
2.891 - // Set PHY interrupt polarities.
2.892 + reg_update(Phy_config, Phy_config_svsret, enable);
2.893 +}
2.894 +
2.895 +void Hdmi_jz4780_chip::phy_enable_gen2_powerdown(bool enable)
2.896 +{
2.897 + reg_update(Phy_config, Phy_config_gen2_powerdown, enable);
2.898 +}
2.899 +
2.900 +void Hdmi_jz4780_chip::phy_enable_gen2_tx_power(bool enable)
2.901 +{
2.902 + reg_update(Phy_config, Phy_config_gen2_tx_power, enable);
2.903 +}
2.904 +
2.905 +void Hdmi_jz4780_chip::phy_enable_interface(bool enable)
2.906 +{
2.907 + reg_update(Phy_config, Phy_config_select_data_enable_polarity, enable);
2.908 + reg_update(Phy_config, Phy_config_select_interface_control, !enable);
2.909 +}
2.910 +
2.911 +// Configure the PHY. Various things not supported by the JZ4780 PHY are ignored
2.912 +// such as the TDMS clock ratio (dependent on HDMI 2 and content scrambling).
2.913 +
2.914 +long Hdmi_jz4780_chip::phy_configure()
2.915 +{
2.916 + long err;
2.917
2.918 - _regs[Phy_polarity] = Phy_status_hotplug_detect | Phy_status_rx_sense_all;
2.919 + phy_power_off();
2.920 +
2.921 + if (_phy_def->svsret)
2.922 + phy_enable_svsret(true);
2.923 +
2.924 + phy_reset();
2.925 +
2.926 + _regs[Main_heac_phy_reset] = Main_heac_phy_reset_assert;
2.927 +
2.928 + i2c_phy_set_address(I2c_phy_device_phy_gen2);
2.929 +
2.930 + if (_phy_def->configure)
2.931 + {
2.932 + err = phy_configure_specific();
2.933 + if (err)
2.934 + return err;
2.935 + }
2.936 +
2.937 + // NOTE: TMDS clock delay here in Linux driver.
2.938 +
2.939 + phy_power_on();
2.940
2.941 - // Enable/unmask second-level interrupts.
2.942 + return L4_EOK;
2.943 +}
2.944 +
2.945 +// Configure for the JZ4780 specifically.
2.946 +
2.947 +long Hdmi_jz4780_chip::phy_configure_specific()
2.948 +{
2.949 + const struct Phy_mpll_config *m = phy_mpll_config;
2.950 + const struct Phy_curr_ctrl *c = phy_curr_ctrl;
2.951 + const struct Phy_config *p = phy_config;
2.952 + unsigned long pixelclock = get_pixelclock();
2.953 +
2.954 + // Find MPLL, CURR_CTRL and PHY configuration settings appropriate for the
2.955 + // pixel clock frequency.
2.956 +
2.957 + while (m->pixelclock && (pixelclock > m->pixelclock))
2.958 + m++;
2.959 +
2.960 + while (c->pixelclock && (pixelclock > c->pixelclock))
2.961 + c++;
2.962 +
2.963 + while (p->pixelclock && (pixelclock > p->pixelclock))
2.964 + p++;
2.965 +
2.966 + printf("MPLL for %ld; CURR_CTRL for %ld; PHY for %ld\n", m->pixelclock, c->pixelclock, p->pixelclock);
2.967
2.968 - _regs[Phy_mask] = _regs[Phy_mask] & ~(Phy_status_hotplug_detect | Phy_status_rx_sense_all);
2.969 + if (!m->pixelclock || !c->pixelclock || !p->pixelclock)
2.970 + return -L4_EINVAL;
2.971 +
2.972 + // Using values for 8bpc from the tables.
2.973 +
2.974 + // Initialise MPLL.
2.975 +
2.976 + i2c_phy_write(I2c_phy_3d_tx_cpce_ctrl, m->res[Phy_resolution_8bpc].cpce);
2.977 + i2c_phy_write(I2c_phy_3d_tx_gmp_ctrl, m->res[Phy_resolution_8bpc].gmp);
2.978 +
2.979 + // Initialise CURRCTRL.
2.980 +
2.981 + i2c_phy_write(I2c_phy_3d_tx_cpce_ctrl, c->curr[Phy_resolution_8bpc]);
2.982 +
2.983 + // Initialise PHY_CONFIG.
2.984 +
2.985 + i2c_phy_write(I2c_phy_3d_tx_pll_phby_ctrl, 0);
2.986 + i2c_phy_write(I2c_phy_3d_tx_msm_ctrl, Msm_ctrl_clock_output_select_fb);
2.987 +
2.988 + i2c_phy_write(I2c_phy_3d_tx_term, p->term);
2.989 + i2c_phy_write(I2c_phy_3d_tx_clock_symbol_ctrl, p->symbol);
2.990 + i2c_phy_write(I2c_phy_3d_tx_vlevel_ctrl, p->vlevel);
2.991
2.992 - // Clear pending interrupts.
2.993 + // Override and disable clock termination.
2.994 +
2.995 + i2c_phy_write(I2c_phy_3d_tx_clock_cal_ctrl, Clock_cal_ctrl_override);
2.996 +
2.997 + return L4_EOK;
2.998 +}
2.999 +
2.1000 +long Hdmi_jz4780_chip::phy_init()
2.1001 +{
2.1002 + printf("phy_init...\n");
2.1003 +
2.1004 + long err;
2.1005 + int i;
2.1006 +
2.1007 + // Initialisation repeated for HDMI PHY specification reasons.
2.1008 +
2.1009 + for (i = 0; i < 2; i++)
2.1010 + {
2.1011 + phy_enable_interface(true);
2.1012 + err = phy_configure();
2.1013 + if (err)
2.1014 + return err;
2.1015 + }
2.1016
2.1017 - _regs[Phy_int_status] = Phy_int_status_hotplug_detect | Phy_int_status_rx_sense_all;
2.1018 + return L4_EOK;
2.1019 +}
2.1020 +
2.1021 +void Hdmi_jz4780_chip::phy_reset()
2.1022 +{
2.1023 + _regs[Main_reset] = 1;
2.1024 + _regs[Main_reset] = 0;
2.1025 +}
2.1026 +
2.1027 +void Hdmi_jz4780_chip::phy_power_off()
2.1028 +{
2.1029 + printf("phy_power_off...\n");
2.1030 +
2.1031 + if (_phy_def && (_phy_def->gen == 1))
2.1032 + {
2.1033 + phy_enable_tmds(false);
2.1034 + phy_enable_powerdown(true);
2.1035 + return;
2.1036 + }
2.1037 +
2.1038 + phy_enable_gen2_tx_power(false);
2.1039 +
2.1040 + wait_for_tx_phy_lock(0);
2.1041
2.1042 - // Enable/unmask interrupts.
2.1043 + phy_enable_gen2_powerdown(true);
2.1044 +}
2.1045 +
2.1046 +void Hdmi_jz4780_chip::phy_power_on()
2.1047 +{
2.1048 + printf("phy_power_on...\n");
2.1049
2.1050 - _regs[Phy_int_mask] = _regs[Phy_int_mask] & ~(Phy_int_status_hotplug_detect | Phy_int_status_rx_sense_all);
2.1051 + if (_phy_def && (_phy_def->gen == 1))
2.1052 + {
2.1053 + phy_enable_powerdown(false);
2.1054 + phy_enable_tmds(false);
2.1055 + phy_enable_tmds(true);
2.1056 + return;
2.1057 + }
2.1058 +
2.1059 + phy_enable_gen2_tx_power(true);
2.1060 + phy_enable_gen2_powerdown(false);
2.1061 +
2.1062 + wait_for_tx_phy_lock(1);
2.1063 }
2.1064
2.1065 +
2.1066 +
2.1067 +// Hotplug detection.
2.1068 +
2.1069 bool Hdmi_jz4780_chip::connected()
2.1070 {
2.1071 return (_regs[Phy_status] & Phy_status_hotplug_detect) != 0;
2.1072 @@ -420,8 +1082,19 @@
2.1073
2.1074 long Hdmi_jz4780_chip::wait_for_connection()
2.1075 {
2.1076 + return wait_for_phy_irq(Phy_int_status_hotplug_detect, Phy_status_hotplug_detect,
2.1077 + Phy_status_hotplug_detect);
2.1078 +}
2.1079 +
2.1080 +// General PHY interrupt handling.
2.1081 +
2.1082 +long Hdmi_jz4780_chip::wait_for_phy_irq(uint32_t int_status_flags,
2.1083 + uint32_t status_flags,
2.1084 + uint32_t status_values)
2.1085 +{
2.1086 long err;
2.1087 - uint8_t int_status, polarity;
2.1088 + uint8_t int_status, status;
2.1089 + uint8_t status_unchanged = ~(status_values) & status_flags;
2.1090 l4_msgtag_t tag;
2.1091
2.1092 do
2.1093 @@ -435,27 +1108,310 @@
2.1094 // Obtain the details.
2.1095
2.1096 int_status = _regs[Phy_int_status];
2.1097 - polarity = _regs[Phy_polarity];
2.1098 + status = _regs[Phy_status];
2.1099
2.1100 // Acknowledge the interrupt.
2.1101
2.1102 - _regs[Phy_int_status] = int_status;
2.1103 + _regs[Phy_int_status] = int_status_flags;
2.1104 +
2.1105 + // Continue without a handled event.
2.1106 + // An event is handled when detected and when the status differs from
2.1107 + // the unchanged state.
2.1108 +
2.1109 + printf("Status: %x versus %x\n", status & status_flags, status_unchanged);
2.1110 +
2.1111 + } while (!((int_status & int_status_flags) &&
2.1112 + ((status & status_flags) ^ status_unchanged)));
2.1113 +
2.1114 + return L4_EOK;
2.1115 +}
2.1116 +
2.1117 +// Wait for TX_PHY_LOCK to become high or low.
2.1118 +
2.1119 +long Hdmi_jz4780_chip::wait_for_tx_phy_lock(int level)
2.1120 +{
2.1121 + if (!!(_regs[Phy_status] & Phy_status_tx_phy_lock) == level)
2.1122 + return L4_EOK;
2.1123 +
2.1124 + return wait_for_phy_irq(Phy_int_status_tx_phy_lock, Phy_status_tx_phy_lock,
2.1125 + level ? Phy_status_tx_phy_lock : Phy_status_none);
2.1126 +}
2.1127 +
2.1128 +
2.1129 +
2.1130 +// Output setup operations.
2.1131 +
2.1132 +long Hdmi_jz4780_chip::enable(unsigned long pixelclock)
2.1133 +{
2.1134 + _pixelclock = pixelclock;
2.1135 +
2.1136 + // Disable frame composer overflow interrupts.
2.1137 +
2.1138 + enable_overflow_irq(false);
2.1139
2.1140 - // Continue without a hotplug event indicating connection.
2.1141 + // NOTE: Here, CEA modes are normally detected and thus the output encoding.
2.1142 + // NOTE: Instead, a fixed RGB output encoding and format is used.
2.1143 + // NOTE: Meanwhile, the input encoding and format will also be fixed to a RGB
2.1144 + // NOTE: representation.
2.1145 +
2.1146 + // _bits_per_channel = 8;
2.1147 + // _data_enable_polarity = true;
2.1148 +
2.1149 + // HDMI initialisation "step B.1": video frame initialisation.
2.1150 +
2.1151 + frame_init();
2.1152 +
2.1153 + // HDMI initialisation "step B.2": PHY initialisation.
2.1154 +
2.1155 + long err = phy_init();
2.1156 + if (err)
2.1157 + return err;
2.1158
2.1159 - } while (!((int_status & Phy_int_status_hotplug_detect) &&
2.1160 - (polarity & Phy_status_hotplug_detect)));
2.1161 + // HDMI initialisation "step B.3": video signal initialisation.
2.1162 +
2.1163 + data_path_init();
2.1164 +
2.1165 + // With audio, various clock updates are needed.
2.1166 +
2.1167 + // NOTE: DVI mode is being assumed for now, for simplicity.
2.1168 +
2.1169 + // In non-DVI mode, the AVI, vendor-specific infoframe and regular infoframe
2.1170 + // are set up.
2.1171 +
2.1172 + packet_init();
2.1173 + csc_init();
2.1174 + sample_init();
2.1175 + hdcp_init();
2.1176 +
2.1177 + // Enable frame composer overflow interrupts.
2.1178 +
2.1179 + enable_overflow_irq(true);
2.1180
2.1181 return L4_EOK;
2.1182 }
2.1183
2.1184 +void Hdmi_jz4780_chip::enable_overflow_irq(bool enable)
2.1185 +{
2.1186 + reg_update(Fc_int_mask2, Fc_int_status2_overflow, !enable);
2.1187 +}
2.1188 +
2.1189 +void Hdmi_jz4780_chip::frame_init()
2.1190 +{
2.1191 + printf("frame_init...\n");
2.1192 +
2.1193 + // Initialise the video configuration. This is rather like the initialisation
2.1194 + // of the LCD controller. The sync and data enable polarities are set up, plus
2.1195 + // extras like HDCP, DVI mode, progressive/interlace.
2.1196 + // NOTE: Here, the JZ4740-specific configuration is used to store the picture
2.1197 + // NOTE: properties, but a neutral structure should be adopted.
2.1198 +
2.1199 + uint8_t config = 0;
2.1200 +
2.1201 + config |= (_panel->config & Jz4740_lcd_hsync_negative)
2.1202 + ? Fc_video_config_hsync_active_low
2.1203 + : Fc_video_config_hsync_active_high;
2.1204 +
2.1205 + config |= (_panel->config & Jz4740_lcd_vsync_negative)
2.1206 + ? Fc_video_config_vsync_active_low
2.1207 + : Fc_video_config_vsync_active_high;
2.1208 +
2.1209 + config |= (_panel->config & Jz4740_lcd_de_negative)
2.1210 + ? Fc_video_config_data_enable_active_low
2.1211 + : Fc_video_config_data_enable_active_high;
2.1212 +
2.1213 + // NOTE: Only supporting DVI mode so far.
2.1214 +
2.1215 + config |= Fc_video_config_dvi_mode;
2.1216 +
2.1217 + // NOTE: Not supporting HDCP.
2.1218 +
2.1219 + config |= Fc_video_config_hdcp_keepout_inactive;
2.1220 +
2.1221 + // NOTE: Only supporting progressive scan so far.
2.1222 +
2.1223 + config |= Fc_video_config_progressive;
2.1224 + config |= Fc_video_config_osc_active_low;
2.1225 +
2.1226 + _regs[Fc_video_config] = config;
2.1227 +
2.1228 + printf("Fc_video_config (%x) = %x\n", Fc_video_config, (uint8_t) _regs[Fc_video_config]);
2.1229 +
2.1230 + // Then, the frame characteristics (visible area, sync pulse) are set. Indeed,
2.1231 + // the frame area details should be practically the same as those used by the
2.1232 + // LCD controller.
2.1233 +
2.1234 + uint16_t hblank = _panel->line_start + _panel->line_end + _panel->hsync,
2.1235 + vblank = _panel->frame_start + _panel->frame_end + _panel->vsync,
2.1236 + hsync_delay = _panel->line_end,
2.1237 + vsync_delay = _panel->frame_end,
2.1238 + hsync_width = _panel->hsync,
2.1239 + vsync_height = _panel->vsync;
2.1240 +
2.1241 + _regs[Fc_horizontal_active_width1] = (_panel->width >> 8) & 0xff;
2.1242 + _regs[Fc_horizontal_active_width0] = _panel->width & 0xff;
2.1243 +
2.1244 + _regs[Fc_horizontal_blank_width1] = (hblank >> 8) & 0xff;
2.1245 + _regs[Fc_horizontal_blank_width0] = hblank & 0xff;
2.1246 +
2.1247 + _regs[Fc_vertical_active_height1] = (_panel->height >> 8) & 0xff;
2.1248 + _regs[Fc_vertical_active_height0] = _panel->height & 0xff;
2.1249 +
2.1250 + _regs[Fc_vertical_blank_height] = vblank & 0xff;
2.1251 +
2.1252 + _regs[Fc_hsync_delay1] = (hsync_delay >> 8) & 0xff;
2.1253 + _regs[Fc_hsync_delay0] = hsync_delay & 0xff;
2.1254 +
2.1255 + _regs[Fc_vsync_delay] = vsync_delay & 0xff;
2.1256 +
2.1257 + _regs[Fc_hsync_width1] = (hsync_width >> 8) & 0xff;
2.1258 + _regs[Fc_hsync_width0] = hsync_width & 0xff;
2.1259 +
2.1260 + _regs[Fc_vsync_height] = vsync_height & 0xff;
2.1261 +}
2.1262 +
2.1263 +void Hdmi_jz4780_chip::data_path_init()
2.1264 +{
2.1265 + printf("data_path_init...\n");
2.1266 +
2.1267 + // Initialise the path of the video data. Here, the elements of the data
2.1268 + // stream are defined such as the control period duration, data channel
2.1269 + // characteristics, pixel and TMDS clocks, and the involvement of colour space
2.1270 + // conversion.
2.1271 +
2.1272 + // Control period minimum duration.
2.1273 +
2.1274 + _regs[Fc_control_duration] = 12;
2.1275 + _regs[Fc_ex_control_duration] = 32;
2.1276 + _regs[Fc_ex_control_space] = 1;
2.1277 +
2.1278 + // Set to fill TMDS data channels.
2.1279 +
2.1280 + _regs[Fc_channel0_preamble] = 0x0b;
2.1281 + _regs[Fc_channel1_preamble] = 0x16;
2.1282 + _regs[Fc_channel2_preamble] = 0x21;
2.1283 +
2.1284 + // Apparent two-stage clock activation.
2.1285 +
2.1286 + uint8_t clock_disable = Main_clock_disable_hdcp |
2.1287 + Main_clock_disable_csc |
2.1288 + Main_clock_disable_audio |
2.1289 + Main_clock_disable_prep |
2.1290 + Main_clock_disable_tmds;
2.1291 +
2.1292 + // Activate the pixel clock.
2.1293 +
2.1294 + _regs[Main_clock_disable] = clock_disable;
2.1295 +
2.1296 + // Then activate the TMDS clock.
2.1297 +
2.1298 + clock_disable &= ~(Main_clock_disable_tmds);
2.1299 + _regs[Main_clock_disable] = clock_disable;
2.1300 +
2.1301 + // NOTE: Bypass colour space conversion for now.
2.1302 +
2.1303 + _regs[Main_flow_control] = Main_flow_control_csc_inactive;
2.1304 +}
2.1305 +
2.1306 +void Hdmi_jz4780_chip::packet_init()
2.1307 +{
2.1308 + printf("packet_init...\n");
2.1309 +
2.1310 + // Initialise the video packet details.
2.1311 + // NOTE: With 24bpp RGB output only for now, no pixel repetition.
2.1312 +
2.1313 + int colour_depth = 4;
2.1314 +
2.1315 + _regs[Packet_pixel_repeater] =
2.1316 + ((colour_depth << Packet_pixel_repeater_depth_offset) &
2.1317 + Packet_pixel_repeater_depth_mask);
2.1318 +
2.1319 + _regs[Packet_remap] = Packet_remap_ycc422_16bit;
2.1320 +
2.1321 + reg_fill_field(Packet_stuffing, Packet_stuffing_pr |
2.1322 + Packet_stuffing_default_phase |
2.1323 + Packet_stuffing_pp |
2.1324 + Packet_stuffing_ycc422);
2.1325 +
2.1326 + // Disable pixel repeater.
2.1327 +
2.1328 + reg_update_field(Packet_config, Packet_config_pr_enable |
2.1329 + Packet_config_bypass_select_packetizer |
2.1330 + Packet_config_bypass_enable |
2.1331 + Packet_config_pp_enable |
2.1332 + Packet_config_ycc422_enable |
2.1333 + Packet_config_output_selector_mask,
2.1334 + Packet_config_bypass_select_packetizer |
2.1335 + Packet_config_bypass_enable |
2.1336 + Packet_config_output_selector_bypass);
2.1337 +}
2.1338 +
2.1339 +void Hdmi_jz4780_chip::csc_init()
2.1340 +{
2.1341 + printf("csc_init...\n");
2.1342 +
2.1343 + // Initialise the colour space conversion details.
2.1344 + // NOTE: No conversion will be done yet (see data_path_init).
2.1345 +
2.1346 + _regs[Csc_config] = Csc_config_interpolation_disable |
2.1347 + Csc_config_decimation_disable;
2.1348 +
2.1349 + // NOTE: Use 8bpc (24bpp) for now.
2.1350 +
2.1351 + reg_update_field(Csc_scale, Csc_scale_colour_depth_mask, Csc_scale_colour_depth_24bpp);
2.1352 +
2.1353 + // NOTE: Coefficients should be set here.
2.1354 +}
2.1355 +
2.1356 +void Hdmi_jz4780_chip::sample_init()
2.1357 +{
2.1358 + printf("sample_init...\n");
2.1359 +
2.1360 + // Initialise the mapping of video input data.
2.1361 + // NOTE: With 24bpp RGB input only for now.
2.1362 +
2.1363 + int colour_format = 0x01;
2.1364 +
2.1365 + // Data enable inactive.
2.1366 +
2.1367 + _regs[Sample_video_config] = (colour_format & Sample_video_config_mapping_mask);
2.1368 +
2.1369 + // Transmission stuffing when data enable is inactive.
2.1370 +
2.1371 + _regs[Sample_video_stuffing] = Sample_video_stuffing_bdb_data |
2.1372 + Sample_video_stuffing_rcr_data |
2.1373 + Sample_video_stuffing_gy_data;
2.1374 +
2.1375 + _regs[Sample_gy_data0] = 0;
2.1376 + _regs[Sample_gy_data1] = 0;
2.1377 + _regs[Sample_rcr_data0] = 0;
2.1378 + _regs[Sample_rcr_data1] = 0;
2.1379 + _regs[Sample_bcb_data0] = 0;
2.1380 + _regs[Sample_bcb_data1] = 0;
2.1381 +}
2.1382 +
2.1383 +void Hdmi_jz4780_chip::hdcp_init()
2.1384 +{
2.1385 + printf("hdcp_init...\n");
2.1386 +
2.1387 + // Initialise HDCP registers, mostly turning things off.
2.1388 +
2.1389 + reg_update(Hdcp_config0, Hdcp_config0_rxdetect_enable, false);
2.1390 +
2.1391 + reg_update(Hdcp_video_polarity,
2.1392 + Hdcp_video_polarity_data_enable_active_high,
2.1393 + !(_panel->config & Jz4740_lcd_de_negative));
2.1394 +
2.1395 + reg_update(Hdcp_config1, Hdcp_config1_encryption_disable, true);
2.1396 +}
2.1397 +
2.1398
2.1399
2.1400 // C language interface functions.
2.1401
2.1402 -void *jz4780_hdmi_init(l4_addr_t start, l4_addr_t end, l4_cap_idx_t irq)
2.1403 +void *jz4780_hdmi_init(l4_addr_t start, l4_addr_t end, l4_cap_idx_t irq,
2.1404 + struct Jz4740_lcd_panel *panel)
2.1405 {
2.1406 - return (void *) new Hdmi_jz4780_chip(start, end, irq);
2.1407 + return (void *) new Hdmi_jz4780_chip(start, end, irq, panel);
2.1408 }
2.1409
2.1410 void jz4780_hdmi_get_version(void *hdmi, uint8_t *major, uint16_t *minor)
2.1411 @@ -463,6 +1419,11 @@
2.1412 static_cast<Hdmi_jz4780_chip *>(hdmi)->get_version(major, minor);
2.1413 }
2.1414
2.1415 +void jz4780_hdmi_get_phy_capabilities(void *hdmi, const struct Phy_capabilities **phy_def)
2.1416 +{
2.1417 + static_cast<Hdmi_jz4780_chip *>(hdmi)->get_phy_capabilities(phy_def);
2.1418 +}
2.1419 +
2.1420 int jz4780_hdmi_i2c_read(void *hdmi, uint8_t *buf, unsigned int length)
2.1421 {
2.1422 return static_cast<Hdmi_jz4780_chip *>(hdmi)->i2c_read(buf, length);
2.1423 @@ -492,3 +1453,8 @@
2.1424 {
2.1425 return static_cast<Hdmi_jz4780_chip *>(hdmi)->wait_for_connection();
2.1426 }
2.1427 +
2.1428 +long jz4780_hdmi_enable(void *hdmi, unsigned long pixelclock)
2.1429 +{
2.1430 + return static_cast<Hdmi_jz4780_chip *>(hdmi)->enable(pixelclock);
2.1431 +}