1.1 --- a/pkg/devices/lib/cpm/include/cpm-common.h Mon Oct 30 17:25:00 2023 +0100
1.2 +++ b/pkg/devices/lib/cpm/include/cpm-common.h Fri Nov 03 18:09:49 2023 +0100
1.3 @@ -322,6 +322,7 @@
1.4 {
1.5 Field _multiplier, _input_divider, _output_divider0, _output_divider1;
1.6 double _intermediate_min, _intermediate_max;
1.7 + bool _adjust_by_one;
1.8
1.9 // General frequency modifiers.
1.10
1.11 @@ -338,10 +339,12 @@
1.12
1.13 explicit Divider_pll(Field multiplier, Field input_divider,
1.14 Field output_divider0, Field output_divider1,
1.15 - double intermediate_min, double intermediate_max)
1.16 + double intermediate_min, double intermediate_max,
1.17 + bool adjust_by_one)
1.18 : _multiplier(multiplier), _input_divider(input_divider),
1.19 _output_divider0(output_divider0), _output_divider1(output_divider1),
1.20 - _intermediate_min(intermediate_min), _intermediate_max(intermediate_max)
1.21 + _intermediate_min(intermediate_min), _intermediate_max(intermediate_max),
1.22 + _adjust_by_one(adjust_by_one)
1.23 {
1.24 }
1.25
1.26 @@ -349,10 +352,12 @@
1.27
1.28 explicit Divider_pll(Field multiplier, Field input_divider,
1.29 Field output_divider,
1.30 - double intermediate_min, double intermediate_max)
1.31 + double intermediate_min, double intermediate_max,
1.32 + bool adjust_by_one)
1.33 : _multiplier(multiplier), _input_divider(input_divider),
1.34 _output_divider0(output_divider), _output_divider1(Field::undefined),
1.35 - _intermediate_min(intermediate_min), _intermediate_max(intermediate_max)
1.36 + _intermediate_min(intermediate_min), _intermediate_max(intermediate_max),
1.37 + _adjust_by_one(adjust_by_one)
1.38 {
1.39 }
1.40
2.1 --- a/pkg/devices/lib/cpm/include/cpm.h Mon Oct 30 17:25:00 2023 +0100
2.2 +++ b/pkg/devices/lib/cpm/include/cpm.h Fri Nov 03 18:09:49 2023 +0100
2.3 @@ -73,12 +73,12 @@
2.4
2.5 // Source frequencies.
2.6
2.7 - uint32_t get_source_frequency(enum Clock_identifiers clock);
2.8 + uint64_t get_source_frequency(enum Clock_identifiers clock);
2.9
2.10 // Output clock frequencies.
2.11
2.12 - uint32_t get_frequency(enum Clock_identifiers clock);
2.13 - int set_frequency(enum Clock_identifiers clock, uint32_t frequency);
2.14 + uint64_t get_frequency(enum Clock_identifiers clock);
2.15 + int set_frequency(enum Clock_identifiers clock, uint64_t frequency);
2.16 };
2.17
2.18 #endif /* __cplusplus */
3.1 --- a/pkg/devices/lib/cpm/src/chip.cc Mon Oct 30 17:25:00 2023 +0100
3.2 +++ b/pkg/devices/lib/cpm/src/chip.cc Fri Nov 03 18:09:49 2023 +0100
3.3 @@ -115,7 +115,7 @@
3.4 clk->set_source(_cpm_regs, source);
3.5 }
3.6
3.7 -uint32_t
3.8 +uint64_t
3.9 Cpm_chip::get_source_frequency(enum Clock_identifiers clock)
3.10 {
3.11 Clock_active *clk = dynamic_cast<Clock_active *>(_clocks[clock]);
3.12 @@ -126,14 +126,14 @@
3.13 return 0;
3.14 }
3.15
3.16 -uint32_t
3.17 +uint64_t
3.18 Cpm_chip::get_frequency(enum Clock_identifiers clock)
3.19 {
3.20 return _clocks[clock]->get_frequency(_cpm_regs);
3.21 }
3.22
3.23 int
3.24 -Cpm_chip::set_frequency(enum Clock_identifiers clock, uint32_t frequency)
3.25 +Cpm_chip::set_frequency(enum Clock_identifiers clock, uint64_t frequency)
3.26 {
3.27 Clock_divided_base *clk = dynamic_cast<Clock_divided_base *>(_clocks[clock]);
3.28
4.1 --- a/pkg/devices/lib/cpm/src/common.cc Mon Oct 30 17:25:00 2023 +0100
4.2 +++ b/pkg/devices/lib/cpm/src/common.cc Fri Nov 03 18:09:49 2023 +0100
4.3 @@ -405,22 +405,28 @@
4.4 }
4.5 }
4.6
4.7 -#define zero_as_one(X) ((X) ? (X) : 1)
4.8
4.9
4.10 +#define zero_as_one(X) ((X) ? (X) : 1)
4.11
4.12 // Feedback multiplier.
4.13
4.14 uint32_t
4.15 Divider_pll::get_multiplier(Cpm_regs ®s)
4.16 {
4.17 - return zero_as_one(_multiplier.get_field(regs));
4.18 + if (_adjust_by_one)
4.19 + return _multiplier.get_field(regs) + 1;
4.20 + else
4.21 + return zero_as_one(_multiplier.get_field(regs));
4.22 }
4.23
4.24 void
4.25 Divider_pll::set_multiplier(Cpm_regs ®s, uint32_t multiplier)
4.26 {
4.27 - _multiplier.set_field(regs, multiplier);
4.28 + if (_adjust_by_one)
4.29 + _multiplier.set_field(regs, multiplier - 1);
4.30 + else
4.31 + _multiplier.set_field(regs, multiplier);
4.32 }
4.33
4.34 // Input divider.
4.35 @@ -428,13 +434,19 @@
4.36 uint32_t
4.37 Divider_pll::get_input_divider(Cpm_regs ®s)
4.38 {
4.39 - return zero_as_one(_input_divider.get_field(regs));
4.40 + if (_adjust_by_one)
4.41 + return _input_divider.get_field(regs) + 1;
4.42 + else
4.43 + return zero_as_one(_input_divider.get_field(regs));
4.44 }
4.45
4.46 void
4.47 Divider_pll::set_input_divider(Cpm_regs ®s, uint32_t divider)
4.48 {
4.49 - _input_divider.set_field(regs, divider);
4.50 + if (_adjust_by_one)
4.51 + _input_divider.set_field(regs, divider - 1);
4.52 + else
4.53 + _input_divider.set_field(regs, divider);
4.54 }
4.55
4.56 // Output dividers.
4.57 @@ -442,9 +454,20 @@
4.58 uint32_t
4.59 Divider_pll::get_output_divider(Cpm_regs ®s)
4.60 {
4.61 - uint32_t d0 = zero_as_one(_output_divider0.get_field(regs));
4.62 - uint32_t d1 = _output_divider1.is_defined() ?
4.63 - zero_as_one(_output_divider1.get_field(regs)) : 1;
4.64 + uint32_t d0, d1;
4.65 +
4.66 + if (_adjust_by_one)
4.67 + {
4.68 + d0 = _output_divider0.get_field(regs) + 1;
4.69 + d1 = _output_divider1.is_defined() ?
4.70 + _output_divider1.get_field(regs) + 1 : 1;
4.71 + }
4.72 + else
4.73 + {
4.74 + d0 = zero_as_one(_output_divider0.get_field(regs));
4.75 + d1 = _output_divider1.is_defined() ?
4.76 + zero_as_one(_output_divider1.get_field(regs)) : 1;
4.77 + }
4.78
4.79 return d0 * d1;
4.80 }
4.81 @@ -463,7 +486,10 @@
4.82
4.83 if (!_output_divider1.is_defined())
4.84 {
4.85 - _output_divider0.set_field(regs, divider);
4.86 + if (_adjust_by_one)
4.87 + _output_divider0.set_field(regs, divider);
4.88 + else
4.89 + _output_divider0.set_field(regs, divider - 1);
4.90 return;
4.91 }
4.92
4.93 @@ -481,8 +507,16 @@
4.94 d1 = divider / d0;
4.95 }
4.96
4.97 - _output_divider0.set_field(regs, d0);
4.98 - _output_divider1.set_field(regs, d1);
4.99 + if (_adjust_by_one)
4.100 + {
4.101 + _output_divider0.set_field(regs, d0 - 1);
4.102 + _output_divider1.set_field(regs, d1 - 1);
4.103 + }
4.104 + else
4.105 + {
4.106 + _output_divider0.set_field(regs, d0);
4.107 + _output_divider1.set_field(regs, d1);
4.108 + }
4.109 }
4.110
4.111 uint64_t
5.1 --- a/pkg/devices/lib/cpm/src/jz4780.cc Mon Oct 30 17:25:00 2023 +0100
5.2 +++ b/pkg/devices/lib/cpm/src/jz4780.cc Fri Nov 03 18:09:49 2023 +0100
5.3 @@ -90,7 +90,7 @@
5.4 Clock_source_lcd1 (Divider_lcd1, 3, 30), // LPCS
5.5 Clock_source_msc (Divider_msc0, 3, 30), // MPCS
5.6 Clock_source_pcm (Divider_pcm, 7, 29), // PCMS, PCMPCS
5.7 - Clock_source_ssi (Divider_ssi, 1, 30), // SPCS
5.8 + Clock_source_ssi (Divider_ssi, 3, 30), // SCS, SPCS
5.9 Clock_source_uhc (Divider_uhc, 3, 30), // UHCS
5.10 Clock_source_vpu (Divider_vpu, 3, 30), // VCS
5.11
5.12 @@ -166,7 +166,7 @@
5.13 Clock_gate_mac (Clock_gate0, 1, 23, true), // MAC
5.14 Clock_gate_gps (Clock_gate0, 1, 22, true), // GPS
5.15 Clock_gate_dma (Clock_gate0, 1, 21, true), // PDMA
5.16 - Clock_gate_ssi2 (Clock_gate0, 1, 20, true), // SSI2
5.17 + //Clock_gate_ssi2 (Clock_gate0, 1, 20, true), // SSI2
5.18 Clock_gate_ssi1 (Clock_gate0, 1, 19, true), // SSI1
5.19 Clock_gate_uart3 (Clock_gate0, 1, 18, true), // UART3
5.20 Clock_gate_uart2 (Clock_gate0, 1, 17, true), // UART2
5.21 @@ -357,9 +357,7 @@
5.22
5.23 clock_ssi0((Source(mux_clock_ssi)), Control(Clock_gate_ssi0)),
5.24
5.25 - clock_ssi1((Source(mux_clock_ssi)), Control(Clock_gate_ssi1)),
5.26 -
5.27 - clock_ssi2((Source(mux_clock_ssi)), Control(Clock_gate_ssi2));
5.28 + clock_ssi1((Source(mux_clock_ssi)), Control(Clock_gate_ssi1));
5.29
5.30 static Clock_divided
5.31 clock_bch(Source(mux_core, Clock_source_bch),
5.32 @@ -441,25 +439,29 @@
5.33 Control_pll(Pll_enable_A, Pll_stable_A, Pll_bypass_A),
5.34 Divider_pll(Pll_multiplier_A, Pll_input_division_A,
5.35 Pll_output_division_A,
5.36 - jz4780_pll_intermediate_min, jz4780_pll_intermediate_max)),
5.37 + jz4780_pll_intermediate_min, jz4780_pll_intermediate_max,
5.38 + true)),
5.39
5.40 clock_pll_E(Source(mux_external),
5.41 Control_pll(Pll_enable_E, Pll_stable_E, Pll_bypass_E),
5.42 Divider_pll(Pll_multiplier_E, Pll_input_division_E,
5.43 Pll_output_division_E,
5.44 - jz4780_pll_intermediate_min, jz4780_pll_intermediate_max)),
5.45 + jz4780_pll_intermediate_min, jz4780_pll_intermediate_max,
5.46 + true)),
5.47
5.48 clock_pll_M(Source(mux_external),
5.49 Control_pll(Pll_enable_M, Pll_stable_M, Pll_bypass_M),
5.50 Divider_pll(Pll_multiplier_M, Pll_input_division_M,
5.51 Pll_output_division_M,
5.52 - jz4780_pll_intermediate_min, jz4780_pll_intermediate_max)),
5.53 + jz4780_pll_intermediate_min, jz4780_pll_intermediate_max,
5.54 + true)),
5.55
5.56 clock_pll_V(Source(mux_external),
5.57 Control_pll(Pll_enable_V, Pll_stable_V, Pll_bypass_V),
5.58 Divider_pll(Pll_multiplier_V, Pll_input_division_V,
5.59 Pll_output_division_V,
5.60 - jz4780_pll_intermediate_min, jz4780_pll_intermediate_max));
5.61 + jz4780_pll_intermediate_min, jz4780_pll_intermediate_max,
5.62 + true));
5.63
5.64
5.65
5.66 @@ -521,7 +523,7 @@
5.67 &clock_ssi,
5.68 &clock_ssi0,
5.69 &clock_ssi1,
5.70 - &clock_ssi2,
5.71 + &clock_none, // Clock_ssi2
5.72 &clock_none, // Clock_timer
5.73 &clock_uart0,
5.74 &clock_uart1,
6.1 --- a/pkg/devices/lib/cpm/src/x1600.cc Mon Oct 30 17:25:00 2023 +0100
6.2 +++ b/pkg/devices/lib/cpm/src/x1600.cc Fri Nov 03 18:09:49 2023 +0100
6.3 @@ -381,19 +381,22 @@
6.4 Control_pll(Pll_enable_A, Pll_stable_A, Pll_bypass_A),
6.5 Divider_pll(Pll_multiplier_A, Pll_input_division_A,
6.6 Pll_output_division0_A, Pll_output_division1_A,
6.7 - x1600_pll_intermediate_min, x1600_pll_intermediate_max)),
6.8 + x1600_pll_intermediate_min, x1600_pll_intermediate_max,
6.9 + false)),
6.10
6.11 clock_pll_E(Source(mux_external),
6.12 Control_pll(Pll_enable_E, Pll_stable_E, Pll_bypass_E),
6.13 Divider_pll(Pll_multiplier_E, Pll_input_division_E,
6.14 Pll_output_division0_E, Pll_output_division1_E,
6.15 - x1600_pll_intermediate_min, x1600_pll_intermediate_max)),
6.16 + x1600_pll_intermediate_min, x1600_pll_intermediate_max,
6.17 + false)),
6.18
6.19 clock_pll_M(Source(mux_external),
6.20 Control_pll(Pll_enable_M, Pll_stable_M, Pll_bypass_M),
6.21 Divider_pll(Pll_multiplier_M, Pll_input_division_M,
6.22 Pll_output_division0_M, Pll_output_division1_M,
6.23 - x1600_pll_intermediate_min, x1600_pll_intermediate_max));
6.24 + x1600_pll_intermediate_min, x1600_pll_intermediate_max,
6.25 + false));
6.26
6.27
6.28