1.1 --- a/pkg/devices/lib/i2c/src/x1600.cc Fri Oct 13 00:49:21 2023 +0200
1.2 +++ b/pkg/devices/lib/i2c/src/x1600.cc Sat Oct 14 01:53:25 2023 +0200
1.3 @@ -173,6 +173,12 @@
1.4 : _cpm(cpm), _frequency(frequency)
1.5 {
1.6 _regs = new Hw::Mmio_register_block<32>(start);
1.7 +
1.8 + // NOTE: Previously located in set_target.
1.9 +
1.10 + disable();
1.11 + set_frequency();
1.12 + enable();
1.13 }
1.14
1.15 // Enable the channel.
1.16 @@ -223,10 +229,14 @@
1.17 : (i2c_clk <= 400 ? I2c_speed_fast
1.18 : I2c_speed_high);
1.19
1.20 - _regs[I2c_control] = _regs[I2c_control] | (speed << I2c_speed_bit) |
1.21 - I2c_disable_slave |
1.22 - I2c_enable_restart |
1.23 - I2c_enable_master;
1.24 + // NOTE: Permit broader configuration elsewhere.
1.25 +
1.26 + _regs[I2c_control] = (speed << I2c_speed_bit) |
1.27 + I2c_disable_slave |
1.28 + I2c_enable_restart |
1.29 + I2c_enable_master;
1.30 +
1.31 + printf("I2c_control = %02x\n", (uint32_t) _regs[I2c_control]);
1.32
1.33 // According to the programming manual, if the PCLK period is T{I2C_DEV_CLK}
1.34 // then the I2C clock period is...
1.35 @@ -383,16 +393,13 @@
1.36 I2c_x1600_channel::set_target(uint8_t address)
1.37 {
1.38 //printf("set_target: %x\n", address);
1.39 - disable();
1.40 - set_frequency();
1.41 _regs[I2c_target_address] = address & I2c_target_7bits;
1.42 - enable();
1.43 init_parameters();
1.44 //printf("I2c_enable_status: %x\n", (uint32_t) _regs[I2c_enable_status]);
1.45 //printf("I2c_status: %x\n", (uint32_t) _regs[I2c_status]);
1.46 //printf("Int_mask: %x\n", (uint32_t) _regs[Int_mask]);
1.47 //printf("Int_status: %x\n", (uint32_t) _regs[Int_status]);
1.48 - printf("Int_raw_status: %x\n", (uint32_t) _regs[Int_raw_status]);
1.49 + //printf("Int_raw_status: %x\n", (uint32_t) _regs[Int_raw_status]);
1.50 }
1.51
1.52
1.53 @@ -483,7 +490,7 @@
1.54 int
1.55 I2c_x1600_channel::write_done()
1.56 {
1.57 - return _reqpos == _total;
1.58 + return (_reqpos == _total) && !have_output();
1.59 }
1.60
1.61 unsigned
1.62 @@ -612,11 +619,15 @@
1.63 _fail = 0;
1.64 _stop = stop;
1.65
1.66 + printf("Int_raw_status: %x\n", (uint32_t) _regs[Int_raw_status]);
1.67 + printf("Trans_abort_status: %x\n", (uint32_t) _regs[Trans_abort_status]);
1.68 printf("start_read: %d\n", total);
1.69
1.70 - _regs[Int_mask] = Int_rx_full | // read condition (reading needed)
1.71 - Int_rx_of | // abort condition
1.72 - Int_tx_abort; // abort condition
1.73 + reset_flags();
1.74 +
1.75 + _regs[Int_mask] = Int_rx_full | // read condition (reading needed)
1.76 + Int_rx_of | // abort condition
1.77 + Int_tx_abort; // general abort condition
1.78
1.79 // Perform initial read requests.
1.80
1.81 @@ -630,6 +641,8 @@
1.82 printf("Int_raw_status: %x\n", (uint32_t) _regs[Int_raw_status]);
1.83 printf("Trans_abort_status: %x\n", (uint32_t) _regs[Trans_abort_status]);
1.84
1.85 + // Test for the general transfer abort condition.
1.86 +
1.87 if (read_failed() || write_failed())
1.88 {
1.89 _fail = 1;
1.90 @@ -656,8 +669,12 @@
1.91 _fail = 0;
1.92 _stop = stop;
1.93
1.94 + printf("Int_raw_status: %x\n", (uint32_t) _regs[Int_raw_status]);
1.95 + printf("Trans_abort_status: %x\n", (uint32_t) _regs[Trans_abort_status]);
1.96 printf("start_write: %d\n", total);
1.97
1.98 + reset_flags();
1.99 +
1.100 // Enable interrupts for further writes.
1.101
1.102 _regs[Int_mask] = Int_tx_empty | // write condition (writing needed)