1.1 --- a/pkg/devices/lib/cpm/include/cpm-common.h Thu Dec 14 22:49:02 2023 +0100
1.2 +++ b/pkg/devices/lib/cpm/include/cpm-common.h Fri Dec 15 18:10:13 2023 +0100
1.3 @@ -63,6 +63,7 @@
1.4 uint32_t mask;
1.5 uint8_t bit;
1.6 bool defined;
1.7 + uint32_t adjustment;
1.8 uint32_t _asserted = 0, _deasserted = 0;
1.9
1.10 public:
1.11 @@ -72,8 +73,8 @@
1.12 }
1.13
1.14 explicit Field(uint32_t reg, uint32_t mask, uint32_t bit,
1.15 - bool inverted = false)
1.16 - : reg(reg), mask(mask), bit(bit), defined(true)
1.17 + bool inverted = false, uint32_t adjustment = 0)
1.18 + : reg(reg), mask(mask), bit(bit), defined(true), adjustment(adjustment)
1.19 {
1.20 if (inverted)
1.21 _deasserted = mask;
1.22 @@ -347,7 +348,6 @@
1.23 {
1.24 Field _multiplier, _input_divider, _output_divider0, _output_divider1;
1.25 double _intermediate_min, _intermediate_max;
1.26 - bool _adjust_by_one;
1.27
1.28 // General frequency modifiers.
1.29
1.30 @@ -364,12 +364,10 @@
1.31
1.32 explicit Divider_pll(Field multiplier, Field input_divider,
1.33 Field output_divider0, Field output_divider1,
1.34 - double intermediate_min, double intermediate_max,
1.35 - bool adjust_by_one)
1.36 + double intermediate_min, double intermediate_max)
1.37 : _multiplier(multiplier), _input_divider(input_divider),
1.38 _output_divider0(output_divider0), _output_divider1(output_divider1),
1.39 - _intermediate_min(intermediate_min), _intermediate_max(intermediate_max),
1.40 - _adjust_by_one(adjust_by_one)
1.41 + _intermediate_min(intermediate_min), _intermediate_max(intermediate_max)
1.42 {
1.43 }
1.44
1.45 @@ -377,12 +375,10 @@
1.46
1.47 explicit Divider_pll(Field multiplier, Field input_divider,
1.48 Field output_divider,
1.49 - double intermediate_min, double intermediate_max,
1.50 - bool adjust_by_one)
1.51 + double intermediate_min, double intermediate_max)
1.52 : _multiplier(multiplier), _input_divider(input_divider),
1.53 _output_divider0(output_divider), _output_divider1(Field::undefined),
1.54 - _intermediate_min(intermediate_min), _intermediate_max(intermediate_max),
1.55 - _adjust_by_one(adjust_by_one)
1.56 + _intermediate_min(intermediate_min), _intermediate_max(intermediate_max)
1.57 {
1.58 }
1.59
2.1 --- a/pkg/devices/lib/cpm/src/common.cc Thu Dec 14 22:49:02 2023 +0100
2.2 +++ b/pkg/devices/lib/cpm/src/common.cc Fri Dec 15 18:10:13 2023 +0100
2.3 @@ -63,7 +63,7 @@
2.4 Field::get_field(Cpm_regs ®s)
2.5 {
2.6 if (defined)
2.7 - return regs.get_field(reg, mask, bit);
2.8 + return regs.get_field(reg, mask, bit) + adjustment;
2.9 else
2.10 return 0;
2.11 }
2.12 @@ -72,7 +72,7 @@
2.13 Field::set_field(Cpm_regs ®s, uint32_t value)
2.14 {
2.15 if (defined)
2.16 - regs.set_field(reg, mask, bit, value);
2.17 + regs.set_field(reg, mask, bit, value >= adjustment ? value - adjustment : 0);
2.18 }
2.19
2.20 // Undefined field.
2.21 @@ -451,19 +451,13 @@
2.22 uint32_t
2.23 Divider_pll::get_multiplier(Cpm_regs ®s)
2.24 {
2.25 - if (_adjust_by_one)
2.26 - return _multiplier.get_field(regs) + 1;
2.27 - else
2.28 - return zero_as_one(_multiplier.get_field(regs));
2.29 + return zero_as_one(_multiplier.get_field(regs));
2.30 }
2.31
2.32 void
2.33 Divider_pll::set_multiplier(Cpm_regs ®s, uint32_t multiplier)
2.34 {
2.35 - if (_adjust_by_one)
2.36 - _multiplier.set_field(regs, multiplier - 1);
2.37 - else
2.38 - _multiplier.set_field(regs, multiplier);
2.39 + _multiplier.set_field(regs, multiplier);
2.40 }
2.41
2.42 // Input divider.
2.43 @@ -471,19 +465,13 @@
2.44 uint32_t
2.45 Divider_pll::get_input_divider(Cpm_regs ®s)
2.46 {
2.47 - if (_adjust_by_one)
2.48 - return _input_divider.get_field(regs) + 1;
2.49 - else
2.50 - return zero_as_one(_input_divider.get_field(regs));
2.51 + return zero_as_one(_input_divider.get_field(regs));
2.52 }
2.53
2.54 void
2.55 Divider_pll::set_input_divider(Cpm_regs ®s, uint32_t divider)
2.56 {
2.57 - if (_adjust_by_one)
2.58 - _input_divider.set_field(regs, divider - 1);
2.59 - else
2.60 - _input_divider.set_field(regs, divider);
2.61 + _input_divider.set_field(regs, divider);
2.62 }
2.63
2.64 // Output dividers.
2.65 @@ -493,18 +481,9 @@
2.66 {
2.67 uint32_t d0, d1;
2.68
2.69 - if (_adjust_by_one)
2.70 - {
2.71 - d0 = _output_divider0.get_field(regs) + 1;
2.72 - d1 = _output_divider1.is_defined() ?
2.73 - _output_divider1.get_field(regs) + 1 : 1;
2.74 - }
2.75 - else
2.76 - {
2.77 - d0 = zero_as_one(_output_divider0.get_field(regs));
2.78 - d1 = _output_divider1.is_defined() ?
2.79 - zero_as_one(_output_divider1.get_field(regs)) : 1;
2.80 - }
2.81 + d0 = zero_as_one(_output_divider0.get_field(regs));
2.82 + d1 = _output_divider1.is_defined() ?
2.83 + zero_as_one(_output_divider1.get_field(regs)) : 1;
2.84
2.85 return d0 * d1;
2.86 }
2.87 @@ -523,10 +502,7 @@
2.88
2.89 if (!_output_divider1.is_defined())
2.90 {
2.91 - if (_adjust_by_one)
2.92 - _output_divider0.set_field(regs, divider);
2.93 - else
2.94 - _output_divider0.set_field(regs, divider - 1);
2.95 + _output_divider0.set_field(regs, divider);
2.96 return;
2.97 }
2.98
2.99 @@ -544,16 +520,8 @@
2.100 d1 = divider / d0;
2.101 }
2.102
2.103 - if (_adjust_by_one)
2.104 - {
2.105 - _output_divider0.set_field(regs, d0 - 1);
2.106 - _output_divider1.set_field(regs, d1 - 1);
2.107 - }
2.108 - else
2.109 - {
2.110 - _output_divider0.set_field(regs, d0);
2.111 - _output_divider1.set_field(regs, d1);
2.112 - }
2.113 + _output_divider0.set_field(regs, d0);
2.114 + _output_divider1.set_field(regs, d1);
2.115 }
2.116
2.117 uint64_t
3.1 --- a/pkg/devices/lib/cpm/src/jz4780.cc Thu Dec 14 22:49:02 2023 +0100
3.2 +++ b/pkg/devices/lib/cpm/src/jz4780.cc Fri Dec 15 18:10:13 2023 +0100
3.3 @@ -220,20 +220,22 @@
3.4 Pll_bypass_M (Pll_control_M, 1, 1), // MPLL_BP
3.5 Pll_bypass_V (Pll_control_V, 1, 1), // VPLL_BP
3.6
3.7 - Pll_multiplier_A (Pll_control_A, 0x1fff, 19), // APLLM
3.8 - Pll_multiplier_E (Pll_control_E, 0x1fff, 19), // EPLLM
3.9 - Pll_multiplier_M (Pll_control_M, 0x1fff, 19), // MPLLM
3.10 - Pll_multiplier_V (Pll_control_V, 0x1fff, 19), // VPLLM
3.11 + // Multipliers and dividers yield 1-based values.
3.12 +
3.13 + Pll_multiplier_A (Pll_control_A, 0x1fff, 19, 1), // APLLM
3.14 + Pll_multiplier_E (Pll_control_E, 0x1fff, 19, 1), // EPLLM
3.15 + Pll_multiplier_M (Pll_control_M, 0x1fff, 19, 1), // MPLLM
3.16 + Pll_multiplier_V (Pll_control_V, 0x1fff, 19, 1), // VPLLM
3.17
3.18 - Pll_input_division_A (Pll_control_A, 0x3f, 13), // APLLN
3.19 - Pll_input_division_E (Pll_control_E, 0x3f, 13), // EPLLN
3.20 - Pll_input_division_M (Pll_control_M, 0x3f, 13), // MPLLN
3.21 - Pll_input_division_V (Pll_control_V, 0x3f, 13), // VPLLN
3.22 + Pll_input_division_A (Pll_control_A, 0x3f, 13, 1), // APLLN
3.23 + Pll_input_division_E (Pll_control_E, 0x3f, 13, 1), // EPLLN
3.24 + Pll_input_division_M (Pll_control_M, 0x3f, 13, 1), // MPLLN
3.25 + Pll_input_division_V (Pll_control_V, 0x3f, 13, 1), // VPLLN
3.26
3.27 - Pll_output_division_A (Pll_control_A, 0x0f, 9), // APLLOD
3.28 - Pll_output_division_E (Pll_control_E, 0x0f, 9), // EPLLOD
3.29 - Pll_output_division_M (Pll_control_M, 0x0f, 9), // MPLLOD
3.30 - Pll_output_division_V (Pll_control_V, 0x0f, 9); // VPLLOD
3.31 + Pll_output_division_A (Pll_control_A, 0x0f, 9, 1), // APLLOD
3.32 + Pll_output_division_E (Pll_control_E, 0x0f, 9, 1), // EPLLOD
3.33 + Pll_output_division_M (Pll_control_M, 0x0f, 9, 1), // MPLLOD
3.34 + Pll_output_division_V (Pll_control_V, 0x0f, 9, 1); // VPLLOD
3.35
3.36
3.37
3.38 @@ -457,29 +459,25 @@
3.39 Control_pll(Pll_enable_A, Pll_stable_A, Pll_bypass_A),
3.40 Divider_pll(Pll_multiplier_A, Pll_input_division_A,
3.41 Pll_output_division_A,
3.42 - jz4780_pll_intermediate_min, jz4780_pll_intermediate_max,
3.43 - true)),
3.44 + jz4780_pll_intermediate_min, jz4780_pll_intermediate_max)),
3.45
3.46 clock_pll_E(Source(mux_external),
3.47 Control_pll(Pll_enable_E, Pll_stable_E, Pll_bypass_E),
3.48 Divider_pll(Pll_multiplier_E, Pll_input_division_E,
3.49 Pll_output_division_E,
3.50 - jz4780_pll_intermediate_min, jz4780_pll_intermediate_max,
3.51 - true)),
3.52 + jz4780_pll_intermediate_min, jz4780_pll_intermediate_max)),
3.53
3.54 clock_pll_M(Source(mux_external),
3.55 Control_pll(Pll_enable_M, Pll_stable_M, Pll_bypass_M),
3.56 Divider_pll(Pll_multiplier_M, Pll_input_division_M,
3.57 Pll_output_division_M,
3.58 - jz4780_pll_intermediate_min, jz4780_pll_intermediate_max,
3.59 - true)),
3.60 + jz4780_pll_intermediate_min, jz4780_pll_intermediate_max)),
3.61
3.62 clock_pll_V(Source(mux_external),
3.63 Control_pll(Pll_enable_V, Pll_stable_V, Pll_bypass_V),
3.64 Divider_pll(Pll_multiplier_V, Pll_input_division_V,
3.65 Pll_output_division_V,
3.66 - jz4780_pll_intermediate_min, jz4780_pll_intermediate_max,
3.67 - true));
3.68 + jz4780_pll_intermediate_min, jz4780_pll_intermediate_max));
3.69
3.70
3.71
4.1 --- a/pkg/devices/lib/cpm/src/x1600.cc Thu Dec 14 22:49:02 2023 +0100
4.2 +++ b/pkg/devices/lib/cpm/src/x1600.cc Fri Dec 15 18:10:13 2023 +0100
4.3 @@ -403,22 +403,19 @@
4.4 Control_pll(Pll_enable_A, Pll_stable_A, Pll_bypass_A),
4.5 Divider_pll(Pll_multiplier_A, Pll_input_division_A,
4.6 Pll_output_division0_A, Pll_output_division1_A,
4.7 - x1600_pll_intermediate_min, x1600_pll_intermediate_max,
4.8 - false)),
4.9 + x1600_pll_intermediate_min, x1600_pll_intermediate_max)),
4.10
4.11 clock_pll_E(Source(mux_external),
4.12 Control_pll(Pll_enable_E, Pll_stable_E, Pll_bypass_E),
4.13 Divider_pll(Pll_multiplier_E, Pll_input_division_E,
4.14 Pll_output_division0_E, Pll_output_division1_E,
4.15 - x1600_pll_intermediate_min, x1600_pll_intermediate_max,
4.16 - false)),
4.17 + x1600_pll_intermediate_min, x1600_pll_intermediate_max)),
4.18
4.19 clock_pll_M(Source(mux_external),
4.20 Control_pll(Pll_enable_M, Pll_stable_M, Pll_bypass_M),
4.21 Divider_pll(Pll_multiplier_M, Pll_input_division_M,
4.22 Pll_output_division0_M, Pll_output_division1_M,
4.23 - x1600_pll_intermediate_min, x1600_pll_intermediate_max,
4.24 - false));
4.25 + x1600_pll_intermediate_min, x1600_pll_intermediate_max));
4.26
4.27
4.28