4.1 --- a/pkg/devices/lib/cpm/src/x1600.cc Tue Oct 24 17:15:40 2023 +0200
4.2 +++ b/pkg/devices/lib/cpm/src/x1600.cc Tue Oct 24 17:18:36 2023 +0200
4.3 @@ -98,7 +98,8 @@
4.4 Clock_source_cdbus (Divider_cdbus, 3, 30), // CDCS
4.5 Clock_source_cim (Divider_cim, 3, 30), // CIMPCS
4.6 Clock_source_ddr (Divider_ddr, 3, 30), // DCS
4.7 - Clock_source_i2s (Divider0_i2s0, 1, 30), // I2PCS
4.8 + Clock_source_i2s0 (Divider0_i2s0, 1, 30), // I2PCS
4.9 + Clock_source_i2s1 (Divider0_i2s1, 1, 30), // I2PCS
4.10 Clock_source_lcd (Divider_lcd, 3, 30), // LPCS
4.11 Clock_source_mac (Divider_mac, 3, 30), // MACPCS
4.12 Clock_source_msc0 (Divider_msc0, 3, 30), // MPCS
4.13 @@ -126,7 +127,8 @@
4.14 Clock_change_enable_ahb2 (Clock_control, 1, 20),
4.15 Clock_change_enable_ddr (Divider_ddr, 1, 29),
4.16 Clock_change_enable_mac (Divider_mac, 1, 29),
4.17 - // Clock_change_enable_i2s (Divider0_i2s0, 1, 29), // CE_I2S may not be change enable
4.18 + Clock_gate_i2s0 (Divider0_i2s0, 1, 29), // CE_I2S is gate, not change enable
4.19 + Clock_gate_i2s1 (Divider0_i2s1, 1, 29), // CE_I2S is gate, not change enable
4.20 Clock_change_enable_lcd (Divider_lcd, 1, 29),
4.21 Clock_change_enable_msc0 (Divider_msc0, 1, 29),
4.22 Clock_change_enable_msc1 (Divider_msc1, 1, 29),
4.23 @@ -167,45 +169,45 @@
4.24 Clock_divider_i2s1_n_auto (Divider1_i2s1, 1, 31), // I2S_NEN
4.25 Clock_divider_i2s1_d_auto (Divider1_i2s1, 1, 30), // I2S_DEN
4.26
4.27 - Clock_gate_main (Clock_control, 1, 23), // GATE_SCLKA
4.28 - Clock_gate_ddr (Clock_gate0, 1, 31), // DDR
4.29 - Clock_gate_ahb0 (Clock_gate0, 1, 29), // AHB0
4.30 - Clock_gate_apb0 (Clock_gate0, 1, 28), // APB0
4.31 - Clock_gate_rtc (Clock_gate0, 1, 27), // RTC
4.32 - Clock_gate_aes (Clock_gate0, 1, 24), // AES
4.33 - Clock_gate_lcd_pixel (Clock_gate0, 1, 23), // LCD
4.34 - Clock_gate_cim (Clock_gate0, 1, 22), // CIM
4.35 - Clock_gate_dma (Clock_gate0, 1, 21), // PDMA
4.36 - Clock_gate_ost (Clock_gate0, 1, 20), // OST
4.37 - Clock_gate_ssi0 (Clock_gate0, 1, 19), // SSI0
4.38 - Clock_gate_timer (Clock_gate0, 1, 18), // TCU
4.39 - Clock_gate_dtrng (Clock_gate0, 1, 17), // DTRNG
4.40 - Clock_gate_uart2 (Clock_gate0, 1, 16), // UART2
4.41 - Clock_gate_uart1 (Clock_gate0, 1, 15), // UART1
4.42 - Clock_gate_uart0 (Clock_gate0, 1, 14), // UART0
4.43 - Clock_gate_sadc (Clock_gate0, 1, 13), // SADC
4.44 - Clock_gate_audio (Clock_gate0, 1, 11), // AUDIO
4.45 - Clock_gate_ssi_slv (Clock_gate0, 1, 10), // SSI_SLV
4.46 - Clock_gate_i2c1 (Clock_gate0, 1, 8), // I2C1
4.47 - Clock_gate_i2c0 (Clock_gate0, 1, 7), // I2C0
4.48 - Clock_gate_msc1 (Clock_gate0, 1, 5), // MSC1
4.49 - Clock_gate_msc0 (Clock_gate0, 1, 4), // MSC0
4.50 - Clock_gate_otg (Clock_gate0, 1, 3), // OTG
4.51 - Clock_gate_sfc (Clock_gate0, 1, 2), // SFC
4.52 - Clock_gate_efuse (Clock_gate0, 1, 1), // EFUSE
4.53 - Clock_gate_nemc (Clock_gate0, 1, 0), // NEMC
4.54 - Clock_gate_arb (Clock_gate1, 1, 30), // ARB
4.55 - Clock_gate_mipi_csi (Clock_gate1, 1, 28), // MIPI_CSI
4.56 - Clock_gate_intc (Clock_gate1, 1, 26), // INTC
4.57 - Clock_gate_gmac0 (Clock_gate1, 1, 23), // GMAC0
4.58 - Clock_gate_uart3 (Clock_gate1, 1, 16), // UART3
4.59 - Clock_gate_i2s0_tx (Clock_gate1, 1, 9), // I2S0_dev_tclk
4.60 - Clock_gate_i2s0_rx (Clock_gate1, 1, 8), // I2S0_dev_rclk
4.61 - Clock_gate_hash (Clock_gate1, 1, 6), // HASH
4.62 - Clock_gate_pwm (Clock_gate1, 1, 5), // PWM
4.63 - Clock_gate_cdbus (Clock_gate1, 1, 2), // CDBUS
4.64 - Clock_gate_can1 (Clock_gate1, 1, 1), // CAN1
4.65 - Clock_gate_can0 (Clock_gate1, 1, 0), // CAN0
4.66 + Clock_gate_main (Clock_control, 1, 23, true), // GATE_SCLKA
4.67 + Clock_gate_ddr (Clock_gate0, 1, 31, true), // DDR
4.68 + Clock_gate_ahb0 (Clock_gate0, 1, 29, true), // AHB0
4.69 + Clock_gate_apb0 (Clock_gate0, 1, 28, true), // APB0
4.70 + Clock_gate_rtc (Clock_gate0, 1, 27, true), // RTC
4.71 + Clock_gate_aes (Clock_gate0, 1, 24, true), // AES
4.72 + Clock_gate_lcd_pixel (Clock_gate0, 1, 23, true), // LCD
4.73 + Clock_gate_cim (Clock_gate0, 1, 22, true), // CIM
4.74 + Clock_gate_dma (Clock_gate0, 1, 21, true), // PDMA
4.75 + Clock_gate_ost (Clock_gate0, 1, 20, true), // OST
4.76 + Clock_gate_ssi0 (Clock_gate0, 1, 19, true), // SSI0
4.77 + Clock_gate_timer (Clock_gate0, 1, 18, true), // TCU
4.78 + Clock_gate_dtrng (Clock_gate0, 1, 17, true), // DTRNG
4.79 + Clock_gate_uart2 (Clock_gate0, 1, 16, true), // UART2
4.80 + Clock_gate_uart1 (Clock_gate0, 1, 15, true), // UART1
4.81 + Clock_gate_uart0 (Clock_gate0, 1, 14, true), // UART0
4.82 + Clock_gate_sadc (Clock_gate0, 1, 13, true), // SADC
4.83 + Clock_gate_audio (Clock_gate0, 1, 11, true), // AUDIO
4.84 + Clock_gate_ssi_slv (Clock_gate0, 1, 10, true), // SSI_SLV
4.85 + Clock_gate_i2c1 (Clock_gate0, 1, 8, true), // I2C1
4.86 + Clock_gate_i2c0 (Clock_gate0, 1, 7, true), // I2C0
4.87 + Clock_gate_msc1 (Clock_gate0, 1, 5, true), // MSC1
4.88 + Clock_gate_msc0 (Clock_gate0, 1, 4, true), // MSC0
4.89 + Clock_gate_otg (Clock_gate0, 1, 3, true), // OTG
4.90 + Clock_gate_sfc (Clock_gate0, 1, 2, true), // SFC
4.91 + Clock_gate_efuse (Clock_gate0, 1, 1, true), // EFUSE
4.92 + Clock_gate_nemc (Clock_gate0, 1, 0, true), // NEMC
4.93 + Clock_gate_arb (Clock_gate1, 1, 30, true), // ARB
4.94 + Clock_gate_mipi_csi (Clock_gate1, 1, 28, true), // MIPI_CSI
4.95 + Clock_gate_intc (Clock_gate1, 1, 26, true), // INTC
4.96 + Clock_gate_gmac0 (Clock_gate1, 1, 23, true), // GMAC0
4.97 + Clock_gate_uart3 (Clock_gate1, 1, 16, true), // UART3
4.98 + Clock_gate_i2s0_tx (Clock_gate1, 1, 9, true), // I2S0_dev_tclk
4.99 + Clock_gate_i2s0_rx (Clock_gate1, 1, 8, true), // I2S0_dev_rclk
4.100 + Clock_gate_hash (Clock_gate1, 1, 6, true), // HASH
4.101 + Clock_gate_pwm (Clock_gate1, 1, 5, true), // PWM
4.102 + Clock_gate_cdbus (Clock_gate1, 1, 2, true), // CDBUS
4.103 + Clock_gate_can1 (Clock_gate1, 1, 1, true), // CAN1
4.104 + Clock_gate_can0 (Clock_gate1, 1, 0, true), // CAN0
4.105
4.106 Pll_enable_A (Pll_control_A, 1, 0), // APLLEN
4.107 Pll_enable_E (Pll_control_E, 1, 0), // EPLLEN
4.108 @@ -249,7 +251,9 @@
4.109 mux_core (3, Clocks(Clock_none, Clock_main, Clock_pll_M)),
4.110 mux_bus (4, Clocks(Clock_main, Clock_pll_M, Clock_pll_E, Clock_external)),
4.111 mux_dev (3, Clocks(Clock_main, Clock_pll_M, Clock_pll_E)),
4.112 - mux_i2s (2, Clocks(Clock_main, Clock_pll_E));
4.113 + mux_i2s (2, Clocks(Clock_main, Clock_pll_E)),
4.114 + mux_i2s0_rx (Clock_i2s0),
4.115 + mux_i2s0_tx (Clock_i2s1);
4.116
4.117
4.118
4.119 @@ -262,7 +266,9 @@
4.120 // Note the use of extra parentheses due to the annoying C++ "most vexing parse"
4.121 // problem. See: https://en.wikipedia.org/wiki/Most_vexing_parse
4.122
4.123 -static Clock clock_dma((Source(mux_hclock2)), (Control(Clock_gate_dma))),
4.124 +static Clock clock_audio((Source(mux_hclock2)), (Control(Clock_gate_audio))),
4.125 +
4.126 + clock_dma((Source(mux_hclock2)), (Control(Clock_gate_dma))),
4.127
4.128 clock_i2c((Source(mux_pclock)), (Control(Clock_gate_i2c0))),
4.129
4.130 @@ -270,6 +276,10 @@
4.131
4.132 clock_i2c1((Source(mux_pclock)), (Control(Clock_gate_i2c1))),
4.133
4.134 + clock_i2s0(Source(mux_i2s, Clock_source_i2s0), Control(Clock_gate_i2s0)),
4.135 +
4.136 + clock_i2s1(Source(mux_i2s, Clock_source_i2s1), Control(Clock_gate_i2s1)),
4.137 +
4.138 clock_main(Source(mux_main, Clock_source_main), Control(Clock_gate_main)),
4.139
4.140 clock_mipi_csi((Source(mux_hclock0)), Control(Clock_gate_mipi_csi)),
4.141 @@ -360,13 +370,13 @@
4.142 Divider(Clock_divider_ssi));
4.143
4.144 static Clock_divided_i2s
4.145 - clock_i2s0_rx(Source(mux_i2s, Clock_source_i2s),
4.146 + clock_i2s0_rx(Source(mux_i2s0_rx),
4.147 Control(Clock_gate_i2s0_rx),
4.148 Divider_i2s(Clock_divider_i2s0_m, Clock_divider_i2s0_n,
4.149 Clock_divider_i2s0_d, Clock_divider_i2s0_n_auto,
4.150 Clock_divider_i2s0_d_auto)),
4.151
4.152 - clock_i2s0_tx(Source(mux_i2s, Clock_source_i2s),
4.153 + clock_i2s0_tx(Source(mux_i2s0_tx),
4.154 Control(Clock_gate_i2s0_tx),
4.155 Divider_i2s(Clock_divider_i2s1_m, Clock_divider_i2s1_n,
4.156 Clock_divider_i2s1_d, Clock_divider_i2s1_n_auto,
4.157 @@ -392,6 +402,7 @@
4.158 // Clock register.
4.159
4.160 static Clock_base *clocks[Clock_identifier_count] = {
4.161 + &clock_audio,
4.162 &clock_none, // Clock_aic_bitclk
4.163 &clock_none, // Clock_aic_pclk
4.164 &clock_can0,
4.165 @@ -409,9 +420,12 @@
4.166 &clock_i2c,
4.167 &clock_i2c0,
4.168 &clock_i2c1,
4.169 - &clock_none, // Clock_i2s
4.170 + &clock_i2s0, // supplies i2s0_rx
4.171 &clock_i2s0_rx,
4.172 &clock_i2s0_tx,
4.173 + &clock_i2s1, // supplies i2s0_tx
4.174 + &clock_none, // Clock_i2s1_rx
4.175 + &clock_none, // Clock_i2s1_tx
4.176 &clock_none, // Clock_kbc
4.177 &clock_none, // Clock_lcd
4.178 &clock_lcd_pixel,