3.1 --- a/pkg/devices/lib/cpm/src/x1600.cc Mon Sep 18 00:41:04 2023 +0200
3.2 +++ b/pkg/devices/lib/cpm/src/x1600.cc Mon Sep 18 02:21:50 2023 +0200
3.3 @@ -248,105 +248,108 @@
3.4
3.5 // Clock instances.
3.6
3.7 -static Clock_passive clock_external;
3.8 +static Clock_null clock_none;
3.9 +
3.10 +static Clock_passive clock_external;
3.11
3.12 -static Clock_null clock_none;
3.13 +// Note the use of extra parentheses due to the annoying C++ "most vexing parse"
3.14 +// problem. See: https://en.wikipedia.org/wiki/Most_vexing_parse
3.15
3.16 -static Clock clock_ahb2_apb(Source(mux_core, Clock_source_hclock2)),
3.17 +static Clock clock_ahb2_apb(Source(mux_core, Clock_source_hclock2)),
3.18
3.19 - clock_can0(Source(mux_bus, Clock_source_can0),
3.20 - Control(Clock_gate_can0, Clock_change_enable_can0, Clock_busy_can0),
3.21 - Divider(Clock_divider_can0)),
3.22 -
3.23 - clock_can1(Source(mux_bus, Clock_source_can1),
3.24 - Control(Clock_gate_can1, Clock_change_enable_can1, Clock_busy_can1),
3.25 - Divider(Clock_divider_can1)),
3.26 -
3.27 - clock_cdbus(Source(mux_dev, Clock_source_cdbus),
3.28 - Control(Clock_gate_cdbus, Clock_change_enable_cdbus, Clock_busy_cdbus),
3.29 - Divider(Clock_divider_cdbus)),
3.30 -
3.31 - clock_cim(Source(mux_dev, Clock_source_cim),
3.32 - Control(Clock_gate_cim, Clock_change_enable_cim, Clock_busy_cim),
3.33 - Divider(Clock_divider_cim)),
3.34 -
3.35 - clock_cpu(Source(mux_core, Clock_source_cpu),
3.36 - Control(Field::undefined, Clock_change_enable_cpu, Clock_busy_cpu),
3.37 - Divider(Clock_divider_cpu)),
3.38 -
3.39 - clock_ddr(Source(mux_core, Clock_source_ddr),
3.40 - Control(Clock_gate_ddr, Clock_change_enable_ddr, Clock_busy_ddr),
3.41 - Divider(Clock_divider_ddr)),
3.42 -
3.43 - clock_dma(Source(mux_pclock), Control(Clock_gate_dma), Divider::undefined),
3.44 -
3.45 - clock_hclock0(Source(mux_core, Clock_source_hclock0),
3.46 - Control(Clock_gate_ahb0, Clock_change_enable_ahb0),
3.47 - Divider(Clock_divider_hclock0)),
3.48 -
3.49 - clock_hclock2(Source(mux_ahb2_apb),
3.50 - Control(Clock_gate_apb0, Clock_change_enable_ahb2),
3.51 - Divider(Clock_divider_hclock2)),
3.52 -
3.53 - clock_i2c(Source(mux_pclock), Control(Clock_gate_i2c0), Divider::undefined),
3.54 -
3.55 - clock_i2c0(Source(mux_pclock), Control(Clock_gate_i2c0), Divider::undefined),
3.56 -
3.57 - clock_i2c1(Source(mux_pclock), Control(Clock_gate_i2c1), Divider::undefined),
3.58 -
3.59 - clock_lcd_pixel(Source(mux_dev, Clock_source_lcd),
3.60 - Control(Clock_gate_lcd_pixel, Clock_change_enable_lcd, Clock_busy_lcd),
3.61 - Divider(Clock_divider_lcd)),
3.62 + clock_dma((Source(mux_pclock)), (Control(Clock_gate_dma))),
3.63 +
3.64 + clock_i2c((Source(mux_pclock)), (Control(Clock_gate_i2c0))),
3.65 +
3.66 + clock_i2c0((Source(mux_pclock)), (Control(Clock_gate_i2c0))),
3.67 +
3.68 + clock_i2c1((Source(mux_pclock)), (Control(Clock_gate_i2c1))),
3.69 +
3.70 + clock_main(Source(mux_core, Clock_source_main),
3.71 + Control(Clock_gate_main)),
3.72 +
3.73 + clock_timer((Source(mux_pclock)), (Control(Clock_gate_timer))),
3.74 +
3.75 + clock_uart0((Source(mux_external)), (Control(Clock_gate_uart0))),
3.76 +
3.77 + clock_uart1((Source(mux_external)), (Control(Clock_gate_uart1))),
3.78 +
3.79 + clock_uart2((Source(mux_external)), (Control(Clock_gate_uart2))),
3.80 +
3.81 + clock_uart3((Source(mux_external)), (Control(Clock_gate_uart3)));
3.82
3.83 - clock_mac(Source(mux_dev, Clock_source_mac),
3.84 - Control(Clock_gate_gmac0, Clock_change_enable_mac, Clock_busy_mac),
3.85 - Divider(Clock_divider_mac)),
3.86 -
3.87 - clock_main(Source(mux_core, Clock_source_main),
3.88 - Control(Clock_gate_main)),
3.89 -
3.90 - clock_msc(Source(mux_dev, Clock_source_msc0),
3.91 - Control(Clock_gate_msc0, Clock_change_enable_msc0, Clock_busy_msc0),
3.92 - Divider(Clock_divider_msc0)),
3.93 -
3.94 - clock_msc0(Source(mux_dev, Clock_source_msc0),
3.95 - Control(Clock_gate_msc0, Clock_change_enable_msc0, Clock_busy_msc0),
3.96 - Divider(Clock_divider_msc0)),
3.97 -
3.98 - clock_msc1(Source(mux_dev, Clock_source_msc1),
3.99 - Control(Clock_gate_msc1, Clock_change_enable_msc1, Clock_busy_msc1),
3.100 - Divider(Clock_divider_msc1)),
3.101 -
3.102 - clock_pclock(Source(mux_ahb2_apb),
3.103 - Control(Clock_gate_apb0, Field::undefined, Field::undefined),
3.104 - Divider(Clock_divider_pclock)),
3.105 -
3.106 - clock_pwm(Source(mux_dev, Clock_source_pwm),
3.107 - Control(Clock_gate_pwm, Clock_change_enable_pwm, Clock_busy_pwm),
3.108 - Divider(Clock_divider_pwm)),
3.109 -
3.110 - clock_pwm0(Source(mux_dev, Clock_source_pwm),
3.111 - Control(Clock_gate_pwm, Clock_change_enable_pwm, Clock_busy_pwm),
3.112 - Divider(Clock_divider_pwm)),
3.113 -
3.114 - clock_sfc(Source(mux_dev, Clock_source_sfc),
3.115 - Control(Clock_gate_sfc, Clock_change_enable_sfc, Clock_busy_sfc),
3.116 - Divider(Clock_divider_sfc)),
3.117 -
3.118 - clock_ssi(Source(mux_dev, Clock_source_ssi),
3.119 - Control(Clock_gate_ssi0, Clock_change_enable_ssi, Clock_busy_ssi),
3.120 - Divider(Clock_divider_ssi)),
3.121 -
3.122 - clock_timer(Source(mux_pclock), Control(Clock_gate_timer), Divider::undefined),
3.123 -
3.124 - clock_uart0(Source(mux_external), Control(Clock_gate_uart0), Divider::undefined),
3.125 -
3.126 - clock_uart1(Source(mux_external), Control(Clock_gate_uart1), Divider::undefined),
3.127 -
3.128 - clock_uart2(Source(mux_external), Control(Clock_gate_uart2), Divider::undefined),
3.129 -
3.130 - clock_uart3(Source(mux_external), Control(Clock_gate_uart3), Divider::undefined);
3.131 -
3.132 +static Clock_divided clock_can0(Source(mux_bus, Clock_source_can0),
3.133 + Control(Clock_gate_can0, Clock_change_enable_can0, Clock_busy_can0),
3.134 + Divider(Clock_divider_can0)),
3.135 +
3.136 + clock_can1(Source(mux_bus, Clock_source_can1),
3.137 + Control(Clock_gate_can1, Clock_change_enable_can1, Clock_busy_can1),
3.138 + Divider(Clock_divider_can1)),
3.139 +
3.140 + clock_cdbus(Source(mux_dev, Clock_source_cdbus),
3.141 + Control(Clock_gate_cdbus, Clock_change_enable_cdbus, Clock_busy_cdbus),
3.142 + Divider(Clock_divider_cdbus)),
3.143 +
3.144 + clock_cim(Source(mux_dev, Clock_source_cim),
3.145 + Control(Clock_gate_cim, Clock_change_enable_cim, Clock_busy_cim),
3.146 + Divider(Clock_divider_cim)),
3.147 +
3.148 + clock_cpu(Source(mux_core, Clock_source_cpu),
3.149 + Control(Field::undefined, Clock_change_enable_cpu, Clock_busy_cpu),
3.150 + Divider(Clock_divider_cpu)),
3.151 +
3.152 + clock_ddr(Source(mux_core, Clock_source_ddr),
3.153 + Control(Clock_gate_ddr, Clock_change_enable_ddr, Clock_busy_ddr),
3.154 + Divider(Clock_divider_ddr)),
3.155 +
3.156 + clock_hclock0(Source(mux_core, Clock_source_hclock0),
3.157 + Control(Clock_gate_ahb0, Clock_change_enable_ahb0),
3.158 + Divider(Clock_divider_hclock0)),
3.159 +
3.160 + clock_hclock2(Source(mux_ahb2_apb),
3.161 + Control(Clock_gate_apb0, Clock_change_enable_ahb2),
3.162 + Divider(Clock_divider_hclock2)),
3.163 +
3.164 + clock_lcd_pixel(Source(mux_dev, Clock_source_lcd),
3.165 + Control(Clock_gate_lcd_pixel, Clock_change_enable_lcd, Clock_busy_lcd),
3.166 + Divider(Clock_divider_lcd)),
3.167 +
3.168 + clock_mac(Source(mux_dev, Clock_source_mac),
3.169 + Control(Clock_gate_gmac0, Clock_change_enable_mac, Clock_busy_mac),
3.170 + Divider(Clock_divider_mac)),
3.171 +
3.172 + clock_msc(Source(mux_dev, Clock_source_msc0),
3.173 + Control(Clock_gate_msc0, Clock_change_enable_msc0, Clock_busy_msc0),
3.174 + Divider(Clock_divider_msc0)),
3.175 +
3.176 + clock_msc0(Source(mux_dev, Clock_source_msc0),
3.177 + Control(Clock_gate_msc0, Clock_change_enable_msc0, Clock_busy_msc0),
3.178 + Divider(Clock_divider_msc0)),
3.179 +
3.180 + clock_msc1(Source(mux_dev, Clock_source_msc1),
3.181 + Control(Clock_gate_msc1, Clock_change_enable_msc1, Clock_busy_msc1),
3.182 + Divider(Clock_divider_msc1)),
3.183 +
3.184 + clock_pclock((Source(mux_ahb2_apb)),
3.185 + (Control(Clock_gate_apb0)),
3.186 + (Divider(Clock_divider_pclock))),
3.187 +
3.188 + clock_pwm(Source(mux_dev, Clock_source_pwm),
3.189 + Control(Clock_gate_pwm, Clock_change_enable_pwm, Clock_busy_pwm),
3.190 + Divider(Clock_divider_pwm)),
3.191 +
3.192 + clock_pwm0(Source(mux_dev, Clock_source_pwm),
3.193 + Control(Clock_gate_pwm, Clock_change_enable_pwm, Clock_busy_pwm),
3.194 + Divider(Clock_divider_pwm)),
3.195 +
3.196 + clock_sfc(Source(mux_dev, Clock_source_sfc),
3.197 + Control(Clock_gate_sfc, Clock_change_enable_sfc, Clock_busy_sfc),
3.198 + Divider(Clock_divider_sfc)),
3.199 +
3.200 + clock_ssi(Source(mux_dev, Clock_source_ssi),
3.201 + Control(Clock_gate_ssi0, Clock_change_enable_ssi, Clock_busy_ssi),
3.202 + Divider(Clock_divider_ssi));
3.203 +
3.204 static Clock_divided_i2s clock_i2s0_rx(Source(mux_i2s, Clock_source_i2s),
3.205 Control(Clock_gate_i2s0_rx, Clock_change_enable_i2s),
3.206 Divider_i2s(Clock_divider_i2s0_m, Clock_divider_i2s0_n,
3.207 @@ -357,20 +360,20 @@
3.208 Divider_i2s(Clock_divider_i2s1_m, Clock_divider_i2s1_n,
3.209 Clock_divider_i2s1_d));
3.210
3.211 -static Pll clock_pll_A(Source(mux_external),
3.212 - Control_pll(Pll_enable_A, Pll_stable_A, Pll_bypass_A),
3.213 - Divider_pll(Pll_multiplier_A, Pll_input_division_A,
3.214 - Pll_output_division0_A, Pll_output_division1_A)),
3.215 +static Pll clock_pll_A(Source(mux_external),
3.216 + Control_pll(Pll_enable_A, Pll_stable_A, Pll_bypass_A),
3.217 + Divider_pll(Pll_multiplier_A, Pll_input_division_A,
3.218 + Pll_output_division0_A, Pll_output_division1_A)),
3.219
3.220 - clock_pll_E(Source(mux_external),
3.221 - Control_pll(Pll_enable_E, Pll_stable_E, Pll_bypass_E),
3.222 - Divider_pll(Pll_multiplier_E, Pll_input_division_E,
3.223 - Pll_output_division0_E, Pll_output_division1_E)),
3.224 + clock_pll_E(Source(mux_external),
3.225 + Control_pll(Pll_enable_E, Pll_stable_E, Pll_bypass_E),
3.226 + Divider_pll(Pll_multiplier_E, Pll_input_division_E,
3.227 + Pll_output_division0_E, Pll_output_division1_E)),
3.228
3.229 - clock_pll_M(Source(mux_external),
3.230 - Control_pll(Pll_enable_M, Pll_stable_M, Pll_bypass_M),
3.231 - Divider_pll(Pll_multiplier_M, Pll_input_division_M,
3.232 - Pll_output_division0_M, Pll_output_division1_M));
3.233 + clock_pll_M(Source(mux_external),
3.234 + Control_pll(Pll_enable_M, Pll_stable_M, Pll_bypass_M),
3.235 + Divider_pll(Pll_multiplier_M, Pll_input_division_M,
3.236 + Pll_output_division0_M, Pll_output_division1_M));
3.237
3.238
3.239
3.240 @@ -473,7 +476,7 @@
3.241 int
3.242 Cpm_x1600_chip::get_parameters(enum Clock_identifiers clock, uint32_t parameters[])
3.243 {
3.244 - Clock_divided *clk = dynamic_cast<Clock_divided *>(clocks[clock]);
3.245 + Clock_divided_base *clk = dynamic_cast<Clock_divided_base *>(clocks[clock]);
3.246
3.247 if (clk != NULL)
3.248 return clk->get_parameters(_cpm_regs, parameters);
3.249 @@ -484,7 +487,7 @@
3.250 void
3.251 Cpm_x1600_chip::set_parameters(enum Clock_identifiers clock, uint32_t parameters[])
3.252 {
3.253 - Clock_divided *clk = dynamic_cast<Clock_divided *>(clocks[clock]);
3.254 + Clock_divided_base *clk = dynamic_cast<Clock_divided_base *>(clocks[clock]);
3.255
3.256 if (clk != NULL)
3.257 clk->set_parameters(_cpm_regs, parameters);
3.258 @@ -540,7 +543,7 @@
3.259
3.260 // Switch to the MPLL and attempt to set the divider.
3.261
3.262 - Clock *lcd = dynamic_cast<Clock *>(clocks[Clock_lcd_pixel]);
3.263 + Clock_divided_base *lcd = dynamic_cast<Clock_divided_base *>(clocks[Clock_lcd_pixel]);
3.264 Clock_base *pll = clocks[Clock_pll_M];
3.265
3.266 if (lcd != NULL)