NanoPayload

Annotated stage2/cpu_op.S

191:174153b3fcbc
188:010e441bc874
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2016-05-04 Paul Boddie file changeset files shortlog Added definitions for register fields.
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/*
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 * CPU-specific routines originally from U-Boot.
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 * See: uboot-xburst/files/arch/mips/cpu/xburst/cpu.c
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 * See: u-boot/arch/mips/include/asm/cacheops.h
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 *
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 * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
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 * Copyright (C) 2015, 2016 Paul Boddie <paul@boddie.org.uk>
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 *
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 * This program is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU General Public License as
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 * published by the Free Software Foundation; either version 2 of
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 * the License, or (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 *
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 * You should have received a copy of the GNU General Public License
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 * along with this program; if not, write to the Free Software
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 * Foundation, Inc., 51 Franklin Street, Fifth Floor,
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 * Boston, MA  02110-1301, USA
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 */
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#include "mips.h"
 
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#include "paging.h"
 
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#include "sdram.h"
 
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.text
 
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.globl flush_icache_tag
 
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.globl flush_icache_region
 
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.globl flush_icache_config
 
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.globl flush_dcache_region
 
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.globl handle_error_level
 
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.globl enable_interrupts
 
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.globl init_interrupts
 
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.globl invoke_task
 
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.globl configure_tlb
 
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.globl map_page_set_index
 
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.globl map_page_index_op
 
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.globl map_page_op
 
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.set noreorder
 
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flush_icache_tag:
 
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	mtc0 $zero, CP0_TAGLO
 
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	mtc0 $zero, CP0_TAGHI
 
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	jr $ra
 
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	nop
 
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flush_icache_region:
 
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	cache Index_Store_Tag_I, 0($a0)
 
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	jr $ra
 
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	nop
 
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flush_icache_config:
 
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	move $t3, $zero
 
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	mfc0 $t3, CP0_CONFIG, 7
 
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	nop
 
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	ori $t3, 2
 
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	mtc0 $t3, CP0_CONFIG, 7
 
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	jr $ra
 
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	nop
 
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flush_dcache_region:
 
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	cache Index_Writeback_Inv_D, 0($a0)
 
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	jr $ra
 
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	nop
 
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handle_error_level:
 
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	mfc0 $t3, CP0_STATUS
 
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	li $t4, ~STATUS_ERL
 
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	and $t3, $t3, $t4
 
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	mtc0 $t3, CP0_STATUS
 
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	jr $ra
 
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	nop
 
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enable_interrupts:
 
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	mfc0 $t3, CP0_STATUS
 
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	ori $t3, $t3, STATUS_IRQ | STATUS_IE
 
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	mtc0 $t3, CP0_STATUS
 
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	jr $ra
 
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	nop
 
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init_interrupts:
 
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	/* Set exception registers. */
 
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	mtc0 $zero, CP0_WATCHLO
 
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	li $t3, CAUSE_IV	/* IV = 1 (use 0x80000200 for interrupts) */
 
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	mtc0 $t3, CP0_CAUSE
 
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	mfc0 $t4, CP0_STATUS
 
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	li $t3, ~STATUS_BEV
 
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	and $t3, $t3, $t4
 
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	mtc0 $t3, CP0_STATUS
 
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	jr $ra
 
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	nop
 
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/* (u8 asid, u32 *base, u32 *stack_pointer) */
 
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invoke_task:
 
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	mtc0 $a0, CP0_ENTRYHI
 
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	nop
 
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	move $t4, $a2		/* use arguments before they are overwritten */
 
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	lw $sp, 0($t4)		/* set the stack pointer */
 
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	move $t3, $a1		/* load parameters from the stored registers */
 
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	lw $a0, 16($t3)
 
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	lw $a1, 20($t3)
 
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	lw $a2, 24($t3)
 
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	lw $a3, 28($t3)
 
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	lw $t9, 100($t3)
 
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	lw $gp, 104($t3)
 
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	mtc0 $t9, CP0_EPC
 
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	mfc0 $t3, CP0_STATUS
 
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	ori $t3, $t3, STATUS_EXL
 
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	mtc0 $t3, CP0_STATUS
 
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	eret
 
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	nop
 
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configure_tlb:
 
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	mtc0 $zero, CP0_CONTEXT
 
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	mtc0 $zero, CP0_WIRED	/* first random entry is zero */
 
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	mfc0 $v0, CP0_CONFIG	/* return the limit */
 
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	jr $ra
 
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	nop
 
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/* (u32 index) */
 
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map_page_set_index:
 
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	mtc0 $a0, CP0_INDEX
 
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	jr $ra
 
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	nop
 
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/* (u32 lower, u32 upper, u32 start, u32 pagemask) */
 
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map_page_index_op:
 
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	jal map_page_op_setup
 
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	nop
 
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	tlbwi
 
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	jr $ra
 
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	nop
 
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/* (u32 lower, u32 upper, u32 start, u32 pagemask) */
 
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map_page_op:
 
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	jal map_page_op_setup
 
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	nop
 
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	tlbwr
 
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	jr $ra
 
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	nop
 
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/* (u32 lower, u32 upper, u32 start, u32 pagemask) */
 
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map_page_op_setup:
 
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	mtc0 $a3, CP0_PAGEMASK
 
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	/* Set physical address. */
 
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	mtc0 $a0, CP0_ENTRYLO0
 
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	mtc0 $a1, CP0_ENTRYLO1
 
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	/* Set virtual address. */
 
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	mtc0 $a2, CP0_ENTRYHI
 
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	jr $ra
 
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	nop
 
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.set reorder