paul@43 | 1 | /* |
paul@43 | 2 | * Include file for Ingenic Semiconductor's JZ4730 CPU. |
paul@43 | 3 | * |
paul@43 | 4 | * Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc. |
paul@63 | 5 | * Copyright (C) 2009 Qi Hardware Inc. |
paul@43 | 6 | * Author: Xiangfu Liu <xiangfu@sharism.cc> |
paul@43 | 7 | * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk> |
paul@43 | 8 | * |
paul@43 | 9 | * This program is free software; you can redistribute it and/or |
paul@43 | 10 | * modify it under the terms of the GNU General Public License as |
paul@43 | 11 | * published by the Free Software Foundation; either version 2 of |
paul@43 | 12 | * the License, or (at your option) any later version. |
paul@43 | 13 | * |
paul@43 | 14 | * This program is distributed in the hope that it will be useful, |
paul@43 | 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@43 | 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@43 | 17 | * GNU General Public License for more details. |
paul@43 | 18 | * |
paul@43 | 19 | * You should have received a copy of the GNU General Public License |
paul@43 | 20 | * along with this program; if not, write to the Free Software |
paul@43 | 21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@43 | 22 | * Boston, MA 02110-1301, USA |
paul@43 | 23 | */ |
paul@43 | 24 | |
paul@43 | 25 | #ifndef __JZ4730_H__ |
paul@43 | 26 | #define __JZ4730_H__ |
paul@43 | 27 | |
paul@43 | 28 | #include "xburst_types.h" |
paul@43 | 29 | |
paul@43 | 30 | /* NOTE: Independent of usbboot parameters. */ |
paul@43 | 31 | |
paul@56 | 32 | #define CONFIG_SYS_CPU_SPEED 336000000 /* CPU clock: 336 MHz */ |
paul@56 | 33 | #define CONFIG_SYS_EXTAL 3686400 /* EXTAL freq: 3.7 MHz */ |
paul@56 | 34 | #define CONFIG_SYS_HZ (CONFIG_SYS_CPU_SPEED / (3*256)) /* incrementer freq */ |
paul@43 | 35 | |
paul@43 | 36 | #define HARB_BASE 0xB3000000 |
paul@43 | 37 | #define EMC_BASE 0xB3010000 |
paul@43 | 38 | #define DMAC_BASE 0xB3020000 |
paul@43 | 39 | #define UHC_BASE 0xB3030000 |
paul@43 | 40 | #define UDC_BASE 0xB3040000 |
paul@43 | 41 | #define LCD_BASE 0xB3050000 |
paul@43 | 42 | #define CIM_BASE 0xB3060000 |
paul@43 | 43 | #define ETH_BASE 0xB3100000 |
paul@43 | 44 | #define NBM_BASE 0xB3F00000 |
paul@43 | 45 | |
paul@43 | 46 | #define CPM_BASE 0xB0000000 |
paul@43 | 47 | #define INTC_BASE 0xB0001000 |
paul@43 | 48 | #define OST_BASE 0xB0002000 |
paul@43 | 49 | #define RTC_BASE 0xB0003000 |
paul@43 | 50 | #define WDT_BASE 0xB0004000 |
paul@43 | 51 | #define GPIO_BASE 0xB0010000 |
paul@43 | 52 | #define AIC_BASE 0xB0020000 |
paul@43 | 53 | #define MSC_BASE 0xB0021000 |
paul@43 | 54 | #define UART0_BASE 0xB0030000 |
paul@43 | 55 | #define UART1_BASE 0xB0031000 |
paul@43 | 56 | #define UART2_BASE 0xB0032000 |
paul@43 | 57 | #define UART3_BASE 0xB0033000 |
paul@43 | 58 | #define FIR_BASE 0xB0040000 |
paul@43 | 59 | #define SCC_BASE 0xB0041000 |
paul@43 | 60 | #define SCC0_BASE 0xB0041000 |
paul@43 | 61 | #define I2C_BASE 0xB0042000 |
paul@43 | 62 | #define SSI_BASE 0xB0043000 |
paul@43 | 63 | #define SCC1_BASE 0xB0044000 |
paul@43 | 64 | #define PWM0_BASE 0xB0050000 |
paul@43 | 65 | #define PWM1_BASE 0xB0051000 |
paul@43 | 66 | #define DES_BASE 0xB0060000 |
paul@43 | 67 | #define UPRT_BASE 0xB0061000 |
paul@43 | 68 | #define KBC_BASE 0xB0062000 |
paul@43 | 69 | |
paul@43 | 70 | |
paul@43 | 71 | |
paul@43 | 72 | |
paul@43 | 73 | /************************************************************************* |
paul@43 | 74 | * MSC |
paul@43 | 75 | *************************************************************************/ |
paul@43 | 76 | #define MSC_STRPCL (MSC_BASE + 0x000) |
paul@43 | 77 | #define MSC_STAT (MSC_BASE + 0x004) |
paul@43 | 78 | #define MSC_CLKRT (MSC_BASE + 0x008) |
paul@43 | 79 | #define MSC_CMDAT (MSC_BASE + 0x00C) |
paul@43 | 80 | #define MSC_RESTO (MSC_BASE + 0x010) |
paul@43 | 81 | #define MSC_RDTO (MSC_BASE + 0x014) |
paul@43 | 82 | #define MSC_BLKLEN (MSC_BASE + 0x018) |
paul@43 | 83 | #define MSC_NOB (MSC_BASE + 0x01C) |
paul@43 | 84 | #define MSC_SNOB (MSC_BASE + 0x020) |
paul@43 | 85 | #define MSC_IMASK (MSC_BASE + 0x024) |
paul@43 | 86 | #define MSC_IREG (MSC_BASE + 0x028) |
paul@43 | 87 | #define MSC_CMD (MSC_BASE + 0x02C) |
paul@43 | 88 | #define MSC_ARG (MSC_BASE + 0x030) |
paul@43 | 89 | #define MSC_RES (MSC_BASE + 0x034) |
paul@43 | 90 | #define MSC_RXFIFO (MSC_BASE + 0x038) |
paul@43 | 91 | #define MSC_TXFIFO (MSC_BASE + 0x03C) |
paul@43 | 92 | |
paul@43 | 93 | #define REG_MSC_STRPCL REG16(MSC_STRPCL) |
paul@43 | 94 | #define REG_MSC_STAT REG32(MSC_STAT) |
paul@43 | 95 | #define REG_MSC_CLKRT REG16(MSC_CLKRT) |
paul@43 | 96 | #define REG_MSC_CMDAT REG32(MSC_CMDAT) |
paul@43 | 97 | #define REG_MSC_RESTO REG16(MSC_RESTO) |
paul@43 | 98 | #define REG_MSC_RDTO REG16(MSC_RDTO) |
paul@43 | 99 | #define REG_MSC_BLKLEN REG16(MSC_BLKLEN) |
paul@43 | 100 | #define REG_MSC_NOB REG16(MSC_NOB) |
paul@43 | 101 | #define REG_MSC_SNOB REG16(MSC_SNOB) |
paul@43 | 102 | #define REG_MSC_IMASK REG16(MSC_IMASK) |
paul@43 | 103 | #define REG_MSC_IREG REG16(MSC_IREG) |
paul@43 | 104 | #define REG_MSC_CMD REG8(MSC_CMD) |
paul@43 | 105 | #define REG_MSC_ARG REG32(MSC_ARG) |
paul@43 | 106 | #define REG_MSC_RES REG16(MSC_RES) |
paul@43 | 107 | #define REG_MSC_RXFIFO REG32(MSC_RXFIFO) |
paul@43 | 108 | #define REG_MSC_TXFIFO REG32(MSC_TXFIFO) |
paul@43 | 109 | |
paul@43 | 110 | /* MSC Clock and Control Register (MSC_STRPCL) */ |
paul@43 | 111 | |
paul@43 | 112 | #define MSC_STRPCL_EXIT_MULTIPLE (1 << 7) |
paul@43 | 113 | #define MSC_STRPCL_EXIT_TRANSFER (1 << 6) |
paul@43 | 114 | #define MSC_STRPCL_START_READWAIT (1 << 5) |
paul@43 | 115 | #define MSC_STRPCL_STOP_READWAIT (1 << 4) |
paul@43 | 116 | #define MSC_STRPCL_RESET (1 << 3) |
paul@43 | 117 | #define MSC_STRPCL_START_OP (1 << 2) |
paul@43 | 118 | #define MSC_STRPCL_CLOCK_CONTROL_BIT 0 |
paul@43 | 119 | #define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT) |
paul@43 | 120 | #define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */ |
paul@43 | 121 | #define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Start MMC/SD clock */ |
paul@43 | 122 | |
paul@43 | 123 | /* MSC Status Register (MSC_STAT) */ |
paul@43 | 124 | |
paul@43 | 125 | #define MSC_STAT_IS_RESETTING (1 << 15) |
paul@43 | 126 | #define MSC_STAT_SDIO_INT_ACTIVE (1 << 14) |
paul@43 | 127 | #define MSC_STAT_PRG_DONE (1 << 13) |
paul@43 | 128 | #define MSC_STAT_DATA_TRAN_DONE (1 << 12) |
paul@43 | 129 | #define MSC_STAT_END_CMD_RES (1 << 11) |
paul@43 | 130 | #define MSC_STAT_DATA_FIFO_AFULL (1 << 10) |
paul@43 | 131 | #define MSC_STAT_IS_READWAIT (1 << 9) |
paul@43 | 132 | #define MSC_STAT_CLK_EN (1 << 8) |
paul@43 | 133 | #define MSC_STAT_DATA_FIFO_FULL (1 << 7) |
paul@43 | 134 | #define MSC_STAT_DATA_FIFO_EMPTY (1 << 6) |
paul@43 | 135 | #define MSC_STAT_CRC_RES_ERR (1 << 5) |
paul@43 | 136 | #define MSC_STAT_CRC_READ_ERROR (1 << 4) |
paul@43 | 137 | #define MSC_STAT_CRC_WRITE_ERROR_BIT 2 |
paul@43 | 138 | #define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT) |
paul@43 | 139 | #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */ |
paul@43 | 140 | #define MSC_STAT_CRC_WRITE_ERROR (1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* Card observed erroneous transmission of data */ |
paul@43 | 141 | #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */ |
paul@43 | 142 | #define MSC_STAT_TIME_OUT_RES (1 << 1) |
paul@43 | 143 | #define MSC_STAT_TIME_OUT_READ (1 << 0) |
paul@43 | 144 | |
paul@43 | 145 | /* MSC Bus Clock Control Register (MSC_CLKRT) */ |
paul@43 | 146 | |
paul@43 | 147 | #define MSC_CLKRT_CLK_RATE_BIT 0 |
paul@43 | 148 | #define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT) |
paul@43 | 149 | #define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT) /* CLK_SRC */ |
paul@43 | 150 | #define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT) /* 1/2 of CLK_SRC */ |
paul@43 | 151 | #define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT) /* 1/4 of CLK_SRC */ |
paul@43 | 152 | #define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT) /* 1/8 of CLK_SRC */ |
paul@43 | 153 | #define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT) /* 1/16 of CLK_SRC */ |
paul@43 | 154 | #define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT) /* 1/32 of CLK_SRC */ |
paul@43 | 155 | #define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT) /* 1/64 of CLK_SRC */ |
paul@43 | 156 | #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT) /* 1/128 of CLK_SRC */ |
paul@43 | 157 | |
paul@43 | 158 | /* MSC Command Sequence Control Register (MSC_CMDAT) */ |
paul@43 | 159 | |
paul@43 | 160 | #define MSC_CMDAT_IO_ABORT (1 << 11) |
paul@43 | 161 | #define MSC_CMDAT_BUS_WIDTH_BIT 9 |
paul@43 | 162 | #define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT) |
paul@43 | 163 | #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) /* 1-bit data bus */ |
paul@43 | 164 | #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) /* 4-bit data bus */ |
paul@43 | 165 | #define CMDAT_BUS_WIDTH1 (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) |
paul@43 | 166 | #define CMDAT_BUS_WIDTH4 (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) |
paul@43 | 167 | #define MSC_CMDAT_DMA_EN (1 << 8) |
paul@43 | 168 | #define MSC_CMDAT_INIT (1 << 7) |
paul@43 | 169 | #define MSC_CMDAT_BUSY (1 << 6) |
paul@43 | 170 | #define MSC_CMDAT_STREAM_BLOCK (1 << 5) |
paul@43 | 171 | #define MSC_CMDAT_WRITE (1 << 4) |
paul@43 | 172 | #define MSC_CMDAT_READ (0 << 4) |
paul@43 | 173 | #define MSC_CMDAT_DATA_EN (1 << 3) |
paul@43 | 174 | #define MSC_CMDAT_RESPONSE_BIT 0 |
paul@43 | 175 | #define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT) |
paul@43 | 176 | #define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) /* No response */ |
paul@43 | 177 | #define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT) /* Format R1 and R1b */ |
paul@43 | 178 | #define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT) /* Format R2 */ |
paul@43 | 179 | #define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT) /* Format R3 */ |
paul@43 | 180 | #define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT) /* Format R4 */ |
paul@43 | 181 | #define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT) /* Format R5 */ |
paul@43 | 182 | #define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT) /* Format R6 */ |
paul@43 | 183 | |
paul@43 | 184 | #define CMDAT_DMA_EN (1 << 8) |
paul@43 | 185 | #define CMDAT_INIT (1 << 7) |
paul@43 | 186 | #define CMDAT_BUSY (1 << 6) |
paul@43 | 187 | #define CMDAT_STREAM (1 << 5) |
paul@43 | 188 | #define CMDAT_WRITE (1 << 4) |
paul@43 | 189 | #define CMDAT_DATA_EN (1 << 3) |
paul@43 | 190 | |
paul@43 | 191 | /* MSC Interrupts Mask Register (MSC_IMASK) */ |
paul@43 | 192 | |
paul@43 | 193 | #define MSC_IMASK_SDIO (1 << 7) |
paul@43 | 194 | #define MSC_IMASK_TXFIFO_WR_REQ (1 << 6) |
paul@43 | 195 | #define MSC_IMASK_RXFIFO_RD_REQ (1 << 5) |
paul@43 | 196 | #define MSC_IMASK_END_CMD_RES (1 << 2) |
paul@43 | 197 | #define MSC_IMASK_PRG_DONE (1 << 1) |
paul@43 | 198 | #define MSC_IMASK_DATA_TRAN_DONE (1 << 0) |
paul@43 | 199 | |
paul@43 | 200 | |
paul@43 | 201 | /* MSC Interrupts Status Register (MSC_IREG) */ |
paul@43 | 202 | |
paul@43 | 203 | #define MSC_IREG_SDIO (1 << 7) |
paul@43 | 204 | #define MSC_IREG_TXFIFO_WR_REQ (1 << 6) |
paul@43 | 205 | #define MSC_IREG_RXFIFO_RD_REQ (1 << 5) |
paul@43 | 206 | #define MSC_IREG_END_CMD_RES (1 << 2) |
paul@43 | 207 | #define MSC_IREG_PRG_DONE (1 << 1) |
paul@43 | 208 | #define MSC_IREG_DATA_TRAN_DONE (1 << 0) |
paul@43 | 209 | |
paul@43 | 210 | /************************************************************************* |
paul@43 | 211 | * RTC |
paul@43 | 212 | *************************************************************************/ |
paul@43 | 213 | #define RTC_RCR (RTC_BASE + 0x00) |
paul@43 | 214 | #define RTC_RSR (RTC_BASE + 0x04) |
paul@43 | 215 | #define RTC_RSAR (RTC_BASE + 0x08) |
paul@43 | 216 | #define RTC_RGR (RTC_BASE + 0x0c) |
paul@43 | 217 | |
paul@43 | 218 | #define REG_RTC_RCR REG32(RTC_RCR) |
paul@43 | 219 | #define REG_RTC_RSR REG32(RTC_RSR) |
paul@43 | 220 | #define REG_RTC_RSAR REG32(RTC_RSAR) |
paul@43 | 221 | #define REG_RTC_RGR REG32(RTC_RGR) |
paul@43 | 222 | |
paul@43 | 223 | #define RTC_RCR_HZ (1 << 6) |
paul@43 | 224 | #define RTC_RCR_HZIE (1 << 5) |
paul@43 | 225 | #define RTC_RCR_AF (1 << 4) |
paul@43 | 226 | #define RTC_RCR_AIE (1 << 3) |
paul@43 | 227 | #define RTC_RCR_AE (1 << 2) |
paul@43 | 228 | #define RTC_RCR_START (1 << 0) |
paul@43 | 229 | |
paul@43 | 230 | #define RTC_RGR_LOCK (1 << 31) |
paul@43 | 231 | #define RTC_RGR_ADJ_BIT 16 |
paul@43 | 232 | #define RTC_RGR_ADJ_MASK (0x3ff << RTC_RGR_ADJ_BIT) |
paul@43 | 233 | #define RTC_RGR_DIV_BIT 0 |
paul@43 | 234 | #define RTC_REG_DIV_MASK (0xff << RTC_RGR_DIV_BIT) |
paul@43 | 235 | |
paul@43 | 236 | |
paul@43 | 237 | |
paul@43 | 238 | |
paul@43 | 239 | /************************************************************************* |
paul@43 | 240 | * FIR |
paul@43 | 241 | *************************************************************************/ |
paul@43 | 242 | #define FIR_TDR (FIR_BASE + 0x000) |
paul@43 | 243 | #define FIR_RDR (FIR_BASE + 0x004) |
paul@43 | 244 | #define FIR_TFLR (FIR_BASE + 0x008) |
paul@43 | 245 | #define FIR_AR (FIR_BASE + 0x00C) |
paul@43 | 246 | #define FIR_CR1 (FIR_BASE + 0x010) |
paul@43 | 247 | #define FIR_CR2 (FIR_BASE + 0x014) |
paul@43 | 248 | #define FIR_SR (FIR_BASE + 0x018) |
paul@43 | 249 | |
paul@43 | 250 | #define REG_FIR_TDR REG8(FIR_TDR) |
paul@43 | 251 | #define REG_FIR_RDR REG8(FIR_RDR) |
paul@43 | 252 | #define REG_FIR_TFLR REG16(FIR_TFLR) |
paul@43 | 253 | #define REG_FIR_AR REG8(FIR_AR) |
paul@43 | 254 | #define REG_FIR_CR1 REG8(FIR_CR1) |
paul@43 | 255 | #define REG_FIR_CR2 REG16(FIR_CR2) |
paul@43 | 256 | #define REG_FIR_SR REG16(FIR_SR) |
paul@43 | 257 | |
paul@43 | 258 | /* FIR Control Register 1 (FIR_CR1) */ |
paul@43 | 259 | |
paul@43 | 260 | #define FIR_CR1_FIRUE (1 << 7) |
paul@43 | 261 | #define FIR_CR1_ACE (1 << 6) |
paul@43 | 262 | #define FIR_CR1_EOUS (1 << 5) |
paul@43 | 263 | #define FIR_CR1_TIIE (1 << 4) |
paul@43 | 264 | #define FIR_CR1_TFIE (1 << 3) |
paul@43 | 265 | #define FIR_CR1_RFIE (1 << 2) |
paul@43 | 266 | #define FIR_CR1_TXE (1 << 1) |
paul@43 | 267 | #define FIR_CR1_RXE (1 << 0) |
paul@43 | 268 | |
paul@43 | 269 | /* FIR Control Register 2 (FIR_CR2) */ |
paul@43 | 270 | |
paul@43 | 271 | #define FIR_CR2_SIPE (1 << 10) |
paul@43 | 272 | #define FIR_CR2_BCRC (1 << 9) |
paul@43 | 273 | #define FIR_CR2_TFLRS (1 << 8) |
paul@43 | 274 | #define FIR_CR2_ISS (1 << 7) |
paul@43 | 275 | #define FIR_CR2_LMS (1 << 6) |
paul@43 | 276 | #define FIR_CR2_TPPS (1 << 5) |
paul@43 | 277 | #define FIR_CR2_RPPS (1 << 4) |
paul@43 | 278 | #define FIR_CR2_TTRG_BIT 2 |
paul@43 | 279 | #define FIR_CR2_TTRG_MASK (0x3 << FIR_CR2_TTRG_BIT) |
paul@43 | 280 | #define FIR_CR2_TTRG_16 (0 << FIR_CR2_TTRG_BIT) /* Transmit Trigger Level is 16 */ |
paul@43 | 281 | #define FIR_CR2_TTRG_32 (1 << FIR_CR2_TTRG_BIT) /* Transmit Trigger Level is 32 */ |
paul@43 | 282 | #define FIR_CR2_TTRG_64 (2 << FIR_CR2_TTRG_BIT) /* Transmit Trigger Level is 64 */ |
paul@43 | 283 | #define FIR_CR2_TTRG_128 (3 << FIR_CR2_TTRG_BIT) /* Transmit Trigger Level is 128 */ |
paul@43 | 284 | #define FIR_CR2_RTRG_BIT 0 |
paul@43 | 285 | #define FIR_CR2_RTRG_MASK (0x3 << FIR_CR2_RTRG_BIT) |
paul@43 | 286 | #define FIR_CR2_RTRG_16 (0 << FIR_CR2_RTRG_BIT) /* Receive Trigger Level is 16 */ |
paul@43 | 287 | #define FIR_CR2_RTRG_32 (1 << FIR_CR2_RTRG_BIT) /* Receive Trigger Level is 32 */ |
paul@43 | 288 | #define FIR_CR2_RTRG_64 (2 << FIR_CR2_RTRG_BIT) /* Receive Trigger Level is 64 */ |
paul@43 | 289 | #define FIR_CR2_RTRG_128 (3 << FIR_CR2_RTRG_BIT) /* Receive Trigger Level is 128 */ |
paul@43 | 290 | |
paul@43 | 291 | /* FIR Status Register (FIR_SR) */ |
paul@43 | 292 | |
paul@43 | 293 | #define FIR_SR_RFW (1 << 12) |
paul@43 | 294 | #define FIR_SR_RFA (1 << 11) |
paul@43 | 295 | #define FIR_SR_TFRTL (1 << 10) |
paul@43 | 296 | #define FIR_SR_RFRTL (1 << 9) |
paul@43 | 297 | #define FIR_SR_URUN (1 << 8) |
paul@43 | 298 | #define FIR_SR_RFTE (1 << 7) |
paul@43 | 299 | #define FIR_SR_ORUN (1 << 6) |
paul@43 | 300 | #define FIR_SR_CRCE (1 << 5) |
paul@43 | 301 | #define FIR_SR_FEND (1 << 4) |
paul@43 | 302 | #define FIR_SR_TFF (1 << 3) |
paul@43 | 303 | #define FIR_SR_RFE (1 << 2) |
paul@43 | 304 | #define FIR_SR_TIDLE (1 << 1) |
paul@43 | 305 | #define FIR_SR_RB (1 << 0) |
paul@43 | 306 | |
paul@43 | 307 | |
paul@43 | 308 | |
paul@43 | 309 | |
paul@43 | 310 | /************************************************************************* |
paul@43 | 311 | * SCC |
paul@43 | 312 | *************************************************************************/ |
paul@43 | 313 | #define SCC_DR(base) ((base) + 0x000) |
paul@43 | 314 | #define SCC_FDR(base) ((base) + 0x004) |
paul@43 | 315 | #define SCC_CR(base) ((base) + 0x008) |
paul@43 | 316 | #define SCC_SR(base) ((base) + 0x00C) |
paul@43 | 317 | #define SCC_TFR(base) ((base) + 0x010) |
paul@43 | 318 | #define SCC_EGTR(base) ((base) + 0x014) |
paul@43 | 319 | #define SCC_ECR(base) ((base) + 0x018) |
paul@43 | 320 | #define SCC_RTOR(base) ((base) + 0x01C) |
paul@43 | 321 | |
paul@43 | 322 | #define REG_SCC_DR(base) REG8(SCC_DR(base)) |
paul@43 | 323 | #define REG_SCC_FDR(base) REG8(SCC_FDR(base)) |
paul@43 | 324 | #define REG_SCC_CR(base) REG32(SCC_CR(base)) |
paul@43 | 325 | #define REG_SCC_SR(base) REG16(SCC_SR(base)) |
paul@43 | 326 | #define REG_SCC_TFR(base) REG16(SCC_TFR(base)) |
paul@43 | 327 | #define REG_SCC_EGTR(base) REG8(SCC_EGTR(base)) |
paul@43 | 328 | #define REG_SCC_ECR(base) REG32(SCC_ECR(base)) |
paul@43 | 329 | #define REG_SCC_RTOR(base) REG8(SCC_RTOR(base)) |
paul@43 | 330 | |
paul@43 | 331 | /* SCC FIFO Data Count Register (SCC_FDR) */ |
paul@43 | 332 | |
paul@43 | 333 | #define SCC_FDR_EMPTY 0x00 |
paul@43 | 334 | #define SCC_FDR_FULL 0x10 |
paul@43 | 335 | |
paul@43 | 336 | /* SCC Control Register (SCC_CR) */ |
paul@43 | 337 | |
paul@43 | 338 | #define SCC_CR_SCCE (1 << 31) |
paul@43 | 339 | #define SCC_CR_TRS (1 << 30) |
paul@43 | 340 | #define SCC_CR_T2R (1 << 29) |
paul@43 | 341 | #define SCC_CR_FDIV_BIT 24 |
paul@43 | 342 | #define SCC_CR_FDIV_MASK (0x3 << SCC_CR_FDIV_BIT) |
paul@43 | 343 | #define SCC_CR_FDIV_1 (0 << SCC_CR_FDIV_BIT) /* SCC_CLK frequency is the same as device clock */ |
paul@43 | 344 | #define SCC_CR_FDIV_2 (1 << SCC_CR_FDIV_BIT) /* SCC_CLK frequency is half of device clock */ |
paul@43 | 345 | #define SCC_CR_FLUSH (1 << 23) |
paul@43 | 346 | #define SCC_CR_TRIG_BIT 16 |
paul@43 | 347 | #define SCC_CR_TRIG_MASK (0x3 << SCC_CR_TRIG_BIT) |
paul@43 | 348 | #define SCC_CR_TRIG_1 (0 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 1 */ |
paul@43 | 349 | #define SCC_CR_TRIG_4 (1 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 4 */ |
paul@43 | 350 | #define SCC_CR_TRIG_8 (2 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 8 */ |
paul@43 | 351 | #define SCC_CR_TRIG_14 (3 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 14 */ |
paul@43 | 352 | #define SCC_CR_TP (1 << 15) |
paul@43 | 353 | #define SCC_CR_CONV (1 << 14) |
paul@43 | 354 | #define SCC_CR_TXIE (1 << 13) |
paul@43 | 355 | #define SCC_CR_RXIE (1 << 12) |
paul@43 | 356 | #define SCC_CR_TENDIE (1 << 11) |
paul@43 | 357 | #define SCC_CR_RTOIE (1 << 10) |
paul@43 | 358 | #define SCC_CR_ECIE (1 << 9) |
paul@43 | 359 | #define SCC_CR_EPIE (1 << 8) |
paul@43 | 360 | #define SCC_CR_RETIE (1 << 7) |
paul@43 | 361 | #define SCC_CR_EOIE (1 << 6) |
paul@43 | 362 | #define SCC_CR_TSEND (1 << 3) |
paul@43 | 363 | #define SCC_CR_PX_BIT 1 |
paul@43 | 364 | #define SCC_CR_PX_MASK (0x3 << SCC_CR_PX_BIT) |
paul@43 | 365 | #define SCC_CR_PX_NOT_SUPPORT (0 << SCC_CR_PX_BIT) /* SCC does not support clock stop */ |
paul@43 | 366 | #define SCC_CR_PX_STOP_LOW (1 << SCC_CR_PX_BIT) /* SCC_CLK stops at state low */ |
paul@43 | 367 | #define SCC_CR_PX_STOP_HIGH (2 << SCC_CR_PX_BIT) /* SCC_CLK stops at state high */ |
paul@43 | 368 | #define SCC_CR_CLKSTP (1 << 0) |
paul@43 | 369 | |
paul@43 | 370 | /* SCC Status Register (SCC_SR) */ |
paul@43 | 371 | |
paul@43 | 372 | #define SCC_SR_TRANS (1 << 15) |
paul@43 | 373 | #define SCC_SR_ORER (1 << 12) |
paul@43 | 374 | #define SCC_SR_RTO (1 << 11) |
paul@43 | 375 | #define SCC_SR_PER (1 << 10) |
paul@43 | 376 | #define SCC_SR_TFTG (1 << 9) |
paul@43 | 377 | #define SCC_SR_RFTG (1 << 8) |
paul@43 | 378 | #define SCC_SR_TEND (1 << 7) |
paul@43 | 379 | #define SCC_SR_RETR_3 (1 << 4) |
paul@43 | 380 | #define SCC_SR_ECNTO (1 << 0) |
paul@43 | 381 | |
paul@43 | 382 | |
paul@43 | 383 | |
paul@43 | 384 | |
paul@43 | 385 | /************************************************************************* |
paul@43 | 386 | * ETH |
paul@43 | 387 | *************************************************************************/ |
paul@43 | 388 | #define ETH_BMR (ETH_BASE + 0x1000) |
paul@43 | 389 | #define ETH_TPDR (ETH_BASE + 0x1004) |
paul@43 | 390 | #define ETH_RPDR (ETH_BASE + 0x1008) |
paul@43 | 391 | #define ETH_RAR (ETH_BASE + 0x100C) |
paul@43 | 392 | #define ETH_TAR (ETH_BASE + 0x1010) |
paul@43 | 393 | #define ETH_SR (ETH_BASE + 0x1014) |
paul@43 | 394 | #define ETH_CR (ETH_BASE + 0x1018) |
paul@43 | 395 | #define ETH_IER (ETH_BASE + 0x101C) |
paul@43 | 396 | #define ETH_MFCR (ETH_BASE + 0x1020) |
paul@43 | 397 | #define ETH_CTAR (ETH_BASE + 0x1050) |
paul@43 | 398 | #define ETH_CRAR (ETH_BASE + 0x1054) |
paul@43 | 399 | #define ETH_MCR (ETH_BASE + 0x0000) |
paul@43 | 400 | #define ETH_MAHR (ETH_BASE + 0x0004) |
paul@43 | 401 | #define ETH_MALR (ETH_BASE + 0x0008) |
paul@43 | 402 | #define ETH_HTHR (ETH_BASE + 0x000C) |
paul@43 | 403 | #define ETH_HTLR (ETH_BASE + 0x0010) |
paul@43 | 404 | #define ETH_MIAR (ETH_BASE + 0x0014) |
paul@43 | 405 | #define ETH_MIDR (ETH_BASE + 0x0018) |
paul@43 | 406 | #define ETH_FCR (ETH_BASE + 0x001C) |
paul@43 | 407 | #define ETH_VTR1 (ETH_BASE + 0x0020) |
paul@43 | 408 | #define ETH_VTR2 (ETH_BASE + 0x0024) |
paul@43 | 409 | #define ETH_WKFR (ETH_BASE + 0x0028) |
paul@43 | 410 | #define ETH_PMTR (ETH_BASE + 0x002C) |
paul@43 | 411 | |
paul@43 | 412 | #define REG_ETH_BMR REG32(ETH_BMR) |
paul@43 | 413 | #define REG_ETH_TPDR REG32(ETH_TPDR) |
paul@43 | 414 | #define REG_ETH_RPDR REG32(ETH_RPDR) |
paul@43 | 415 | #define REG_ETH_RAR REG32(ETH_RAR) |
paul@43 | 416 | #define REG_ETH_TAR REG32(ETH_TAR) |
paul@43 | 417 | #define REG_ETH_SR REG32(ETH_SR) |
paul@43 | 418 | #define REG_ETH_CR REG32(ETH_CR) |
paul@43 | 419 | #define REG_ETH_IER REG32(ETH_IER) |
paul@43 | 420 | #define REG_ETH_MFCR REG32(ETH_MFCR) |
paul@43 | 421 | #define REG_ETH_CTAR REG32(ETH_CTAR) |
paul@43 | 422 | #define REG_ETH_CRAR REG32(ETH_CRAR) |
paul@43 | 423 | #define REG_ETH_MCR REG32(ETH_MCR) |
paul@43 | 424 | #define REG_ETH_MAHR REG32(ETH_MAHR) |
paul@43 | 425 | #define REG_ETH_MALR REG32(ETH_MALR) |
paul@43 | 426 | #define REG_ETH_HTHR REG32(ETH_HTHR) |
paul@43 | 427 | #define REG_ETH_HTLR REG32(ETH_HTLR) |
paul@43 | 428 | #define REG_ETH_MIAR REG32(ETH_MIAR) |
paul@43 | 429 | #define REG_ETH_MIDR REG32(ETH_MIDR) |
paul@43 | 430 | #define REG_ETH_FCR REG32(ETH_FCR) |
paul@43 | 431 | #define REG_ETH_VTR1 REG32(ETH_VTR1) |
paul@43 | 432 | #define REG_ETH_VTR2 REG32(ETH_VTR2) |
paul@43 | 433 | #define REG_ETH_WKFR REG32(ETH_WKFR) |
paul@43 | 434 | #define REG_ETH_PMTR REG32(ETH_PMTR) |
paul@43 | 435 | |
paul@43 | 436 | /* Bus Mode Register (ETH_BMR) */ |
paul@43 | 437 | |
paul@43 | 438 | #define ETH_BMR_DBO (1 << 20) |
paul@43 | 439 | #define ETH_BMR_PBL_BIT 8 |
paul@43 | 440 | #define ETH_BMR_PBL_MASK (0x3f << ETH_BMR_PBL_BIT) |
paul@43 | 441 | #define ETH_BMR_PBL_1 (0x1 << ETH_BMR_PBL_BIT) |
paul@43 | 442 | #define ETH_BMR_PBL_4 (0x4 << ETH_BMR_PBL_BIT) |
paul@43 | 443 | #define ETH_BMR_BLE (1 << 7) |
paul@43 | 444 | #define ETH_BMR_DSL_BIT 2 |
paul@43 | 445 | #define ETH_BMR_DSL_MASK (0x1f << ETH_BMR_DSL_BIT) |
paul@43 | 446 | #define ETH_BMR_DSL_0 (0x0 << ETH_BMR_DSL_BIT) |
paul@43 | 447 | #define ETH_BMR_DSL_1 (0x1 << ETH_BMR_DSL_BIT) |
paul@43 | 448 | #define ETH_BMR_DSL_2 (0x2 << ETH_BMR_DSL_BIT) |
paul@43 | 449 | #define ETH_BMR_DSL_4 (0x4 << ETH_BMR_DSL_BIT) |
paul@43 | 450 | #define ETH_BMR_DSL_8 (0x8 << ETH_BMR_DSL_BIT) |
paul@43 | 451 | #define ETH_BMR_SWR (1 << 0) |
paul@43 | 452 | |
paul@43 | 453 | /* DMA Status Register (ETH_SR) */ |
paul@43 | 454 | |
paul@43 | 455 | #define ETH_SR_EB_BIT 23 |
paul@43 | 456 | #define ETH_SR_EB_MASK (0x7 << ETH_SR_EB_BIT) |
paul@43 | 457 | #define ETH_SR_EB_TX_ABORT (0x1 << ETH_SR_EB_BIT) |
paul@43 | 458 | #define ETH_SR_EB_RX_ABORT (0x2 << ETH_SR_EB_BIT) |
paul@43 | 459 | #define ETH_SR_TS_BIT 20 |
paul@43 | 460 | #define ETH_SR_TS_MASK (0x7 << ETH_SR_TS_BIT) |
paul@43 | 461 | #define ETH_SR_TS_STOP (0x0 << ETH_SR_TS_BIT) |
paul@43 | 462 | #define ETH_SR_TS_FTD (0x1 << ETH_SR_TS_BIT) |
paul@43 | 463 | #define ETH_SR_TS_WEOT (0x2 << ETH_SR_TS_BIT) |
paul@43 | 464 | #define ETH_SR_TS_QDAT (0x3 << ETH_SR_TS_BIT) |
paul@43 | 465 | #define ETH_SR_TS_SUSPEND (0x6 << ETH_SR_TS_BIT) |
paul@43 | 466 | #define ETH_SR_TS_CTD (0x7 << ETH_SR_TS_BIT) |
paul@43 | 467 | #define ETH_SR_RS_BIT 17 |
paul@43 | 468 | #define ETH_SR_RS_MASK (0x7 << ETH_SR_RS_BIT) |
paul@43 | 469 | #define ETH_SR_RS_STOP (0x0 << ETH_SR_RS_BIT) |
paul@43 | 470 | #define ETH_SR_RS_FRD (0x1 << ETH_SR_RS_BIT) |
paul@43 | 471 | #define ETH_SR_RS_CEOR (0x2 << ETH_SR_RS_BIT) |
paul@43 | 472 | #define ETH_SR_RS_WRP (0x3 << ETH_SR_RS_BIT) |
paul@43 | 473 | #define ETH_SR_RS_SUSPEND (0x4 << ETH_SR_RS_BIT) |
paul@43 | 474 | #define ETH_SR_RS_CRD (0x5 << ETH_SR_RS_BIT) |
paul@43 | 475 | #define ETH_SR_RS_FCF (0x6 << ETH_SR_RS_BIT) |
paul@43 | 476 | #define ETH_SR_RS_QRF (0x7 << ETH_SR_RS_BIT) |
paul@43 | 477 | #define ETH_SR_NIS (1 << 16) |
paul@43 | 478 | #define ETH_SR_AIS (1 << 15) |
paul@43 | 479 | #define ETH_SR_ERI (1 << 14) |
paul@43 | 480 | #define ETH_SR_FBE (1 << 13) |
paul@43 | 481 | #define ETH_SR_ETI (1 << 10) |
paul@43 | 482 | #define ETH_SR_RWT (1 << 9) |
paul@43 | 483 | #define ETH_SR_RPS (1 << 8) |
paul@43 | 484 | #define ETH_SR_RU (1 << 7) |
paul@43 | 485 | #define ETH_SR_RI (1 << 6) |
paul@43 | 486 | #define ETH_SR_UNF (1 << 5) |
paul@43 | 487 | #define ETH_SR_TJT (1 << 3) |
paul@43 | 488 | #define ETH_SR_TU (1 << 2) |
paul@43 | 489 | #define ETH_SR_TPS (1 << 1) |
paul@43 | 490 | #define ETH_SR_TI (1 << 0) |
paul@43 | 491 | |
paul@43 | 492 | /* Control (Operation Mode) Register (ETH_CR) */ |
paul@43 | 493 | |
paul@43 | 494 | #define ETH_CR_TTM (1 << 22) |
paul@43 | 495 | #define ETH_CR_SF (1 << 21) |
paul@43 | 496 | #define ETH_CR_TR_BIT 14 |
paul@43 | 497 | #define ETH_CR_TR_MASK (0x3 << ETH_CR_TR_BIT) |
paul@43 | 498 | #define ETH_CR_ST (1 << 13) |
paul@43 | 499 | #define ETH_CR_OSF (1 << 2) |
paul@43 | 500 | #define ETH_CR_SR (1 << 1) |
paul@43 | 501 | |
paul@43 | 502 | /* Interrupt Enable Register (ETH_IER) */ |
paul@43 | 503 | |
paul@43 | 504 | #define ETH_IER_NI (1 << 16) |
paul@43 | 505 | #define ETH_IER_AI (1 << 15) |
paul@43 | 506 | #define ETH_IER_ERE (1 << 14) |
paul@43 | 507 | #define ETH_IER_FBE (1 << 13) |
paul@43 | 508 | #define ETH_IER_ET (1 << 10) |
paul@43 | 509 | #define ETH_IER_RWE (1 << 9) |
paul@43 | 510 | #define ETH_IER_RS (1 << 8) |
paul@43 | 511 | #define ETH_IER_RU (1 << 7) |
paul@43 | 512 | #define ETH_IER_RI (1 << 6) |
paul@43 | 513 | #define ETH_IER_UN (1 << 5) |
paul@43 | 514 | #define ETH_IER_TJ (1 << 3) |
paul@43 | 515 | #define ETH_IER_TU (1 << 2) |
paul@43 | 516 | #define ETH_IER_TS (1 << 1) |
paul@43 | 517 | #define ETH_IER_TI (1 << 0) |
paul@43 | 518 | |
paul@43 | 519 | /* Missed Frame and Buffer Overflow Counter Register (ETH_MFCR) */ |
paul@43 | 520 | |
paul@43 | 521 | #define ETH_MFCR_OVERFLOW_BIT 17 |
paul@43 | 522 | #define ETH_MFCR_OVERFLOW_MASK (0x7ff << ETH_MFCR_OVERFLOW_BIT) |
paul@43 | 523 | #define ETH_MFCR_MFC_BIT 0 |
paul@43 | 524 | #define ETH_MFCR_MFC_MASK (0xffff << ETH_MFCR_MFC_BIT) |
paul@43 | 525 | |
paul@43 | 526 | /* MAC Control Register (ETH_MCR) */ |
paul@43 | 527 | |
paul@43 | 528 | #define ETH_MCR_RA (1 << 31) |
paul@43 | 529 | #define ETH_MCR_HBD (1 << 28) |
paul@43 | 530 | #define ETH_MCR_PS (1 << 27) |
paul@43 | 531 | #define ETH_MCR_DRO (1 << 23) |
paul@43 | 532 | #define ETH_MCR_OM_BIT 21 |
paul@43 | 533 | #define ETH_MCR_OM_MASK (0x3 << ETH_MCR_OM_BIT) |
paul@43 | 534 | #define ETH_MCR_OM_NORMAL (0x0 << ETH_MCR_OM_BIT) |
paul@43 | 535 | #define ETH_MCR_OM_INTERNAL (0x1 << ETH_MCR_OM_BIT) |
paul@43 | 536 | #define ETH_MCR_OM_EXTERNAL (0x2 << ETH_MCR_OM_BIT) |
paul@43 | 537 | #define ETH_MCR_F (1 << 20) |
paul@43 | 538 | #define ETH_MCR_PM (1 << 19) |
paul@43 | 539 | #define ETH_MCR_PR (1 << 18) |
paul@43 | 540 | #define ETH_MCR_IF (1 << 17) |
paul@43 | 541 | #define ETH_MCR_PB (1 << 16) |
paul@43 | 542 | #define ETH_MCR_HO (1 << 15) |
paul@43 | 543 | #define ETH_MCR_HP (1 << 13) |
paul@43 | 544 | #define ETH_MCR_LCC (1 << 12) |
paul@43 | 545 | #define ETH_MCR_DBF (1 << 11) |
paul@43 | 546 | #define ETH_MCR_DTRY (1 << 10) |
paul@43 | 547 | #define ETH_MCR_ASTP (1 << 8) |
paul@43 | 548 | #define ETH_MCR_BOLMT_BIT 6 |
paul@43 | 549 | #define ETH_MCR_BOLMT_MASK (0x3 << ETH_MCR_BOLMT_BIT) |
paul@43 | 550 | #define ETH_MCR_BOLMT_10 (0 << ETH_MCR_BOLMT_BIT) |
paul@43 | 551 | #define ETH_MCR_BOLMT_8 (1 << ETH_MCR_BOLMT_BIT) |
paul@43 | 552 | #define ETH_MCR_BOLMT_4 (2 << ETH_MCR_BOLMT_BIT) |
paul@43 | 553 | #define ETH_MCR_BOLMT_1 (3 << ETH_MCR_BOLMT_BIT) |
paul@43 | 554 | #define ETH_MCR_DC (1 << 5) |
paul@43 | 555 | #define ETH_MCR_TE (1 << 3) |
paul@43 | 556 | #define ETH_MCR_RE (1 << 2) |
paul@43 | 557 | |
paul@43 | 558 | /* MII Address Register (ETH_MIAR) */ |
paul@43 | 559 | |
paul@43 | 560 | #define ETH_MIAR_PHY_ADDR_BIT 11 |
paul@43 | 561 | #define ETH_MIAR_PHY_ADDR_MASK (0x1f << ETH_MIAR_PHY_ADDR_BIT) |
paul@43 | 562 | #define ETH_MIAR_MII_REG_BIT 6 |
paul@43 | 563 | #define ETH_MIAR_MII_REG_MASK (0x1f << ETH_MIAR_MII_REG_BIT) |
paul@43 | 564 | #define ETH_MIAR_MII_WRITE (1 << 1) |
paul@43 | 565 | #define ETH_MIAR_MII_BUSY (1 << 0) |
paul@43 | 566 | |
paul@43 | 567 | /* Flow Control Register (ETH_FCR) */ |
paul@43 | 568 | |
paul@43 | 569 | #define ETH_FCR_PAUSE_TIME_BIT 16 |
paul@43 | 570 | #define ETH_FCR_PAUSE_TIME_MASK (0xffff << ETH_FCR_PAUSE_TIME_BIT) |
paul@43 | 571 | #define ETH_FCR_PCF (1 << 2) |
paul@43 | 572 | #define ETH_FCR_FCE (1 << 1) |
paul@43 | 573 | #define ETH_FCR_BUSY (1 << 0) |
paul@43 | 574 | |
paul@43 | 575 | /* PMT Control and Status Register (ETH_PMTR) */ |
paul@43 | 576 | |
paul@43 | 577 | #define ETH_PMTR_GU (1 << 9) |
paul@43 | 578 | #define ETH_PMTR_RF (1 << 6) |
paul@43 | 579 | #define ETH_PMTR_MF (1 << 5) |
paul@43 | 580 | #define ETH_PMTR_RWK (1 << 2) |
paul@43 | 581 | #define ETH_PMTR_MPK (1 << 1) |
paul@43 | 582 | |
paul@43 | 583 | /* Receive Descriptor 0 (ETH_RD0) Bits */ |
paul@43 | 584 | |
paul@43 | 585 | #define ETH_RD0_OWN (1 << 31) |
paul@43 | 586 | #define ETH_RD0_FF (1 << 30) |
paul@43 | 587 | #define ETH_RD0_FL_BIT 16 |
paul@43 | 588 | #define ETH_RD0_FL_MASK (0x3fff << ETH_RD0_FL_BIT) |
paul@43 | 589 | #define ETH_RD0_ES (1 << 15) |
paul@43 | 590 | #define ETH_RD0_DE (1 << 14) |
paul@43 | 591 | #define ETH_RD0_LE (1 << 12) |
paul@43 | 592 | #define ETH_RD0_RF (1 << 11) |
paul@43 | 593 | #define ETH_RD0_MF (1 << 10) |
paul@43 | 594 | #define ETH_RD0_FD (1 << 9) |
paul@43 | 595 | #define ETH_RD0_LD (1 << 8) |
paul@43 | 596 | #define ETH_RD0_TL (1 << 7) |
paul@43 | 597 | #define ETH_RD0_CS (1 << 6) |
paul@43 | 598 | #define ETH_RD0_FT (1 << 5) |
paul@43 | 599 | #define ETH_RD0_WT (1 << 4) |
paul@43 | 600 | #define ETH_RD0_ME (1 << 3) |
paul@43 | 601 | #define ETH_RD0_DB (1 << 2) |
paul@43 | 602 | #define ETH_RD0_CE (1 << 1) |
paul@43 | 603 | |
paul@43 | 604 | /* Receive Descriptor 1 (ETH_RD1) Bits */ |
paul@43 | 605 | |
paul@43 | 606 | #define ETH_RD1_RER (1 << 25) |
paul@43 | 607 | #define ETH_RD1_RCH (1 << 24) |
paul@43 | 608 | #define ETH_RD1_RBS2_BIT 11 |
paul@43 | 609 | #define ETH_RD1_RBS2_MASK (0x7ff << ETH_RD1_RBS2_BIT) |
paul@43 | 610 | #define ETH_RD1_RBS1_BIT 0 |
paul@43 | 611 | #define ETH_RD1_RBS1_MASK (0x7ff << ETH_RD1_RBS1_BIT) |
paul@43 | 612 | |
paul@43 | 613 | /* Transmit Descriptor 0 (ETH_TD0) Bits */ |
paul@43 | 614 | |
paul@43 | 615 | #define ETH_TD0_OWN (1 << 31) |
paul@43 | 616 | #define ETH_TD0_FA (1 << 15) |
paul@43 | 617 | #define ETH_TD0_LOC (1 << 11) |
paul@43 | 618 | #define ETH_TD0_NC (1 << 10) |
paul@43 | 619 | #define ETH_TD0_LC (1 << 9) |
paul@43 | 620 | #define ETH_TD0_EC (1 << 8) |
paul@43 | 621 | #define ETH_TD0_HBF (1 << 7) |
paul@43 | 622 | #define ETH_TD0_CC_BIT 3 |
paul@43 | 623 | #define ETH_TD0_CC_MASK (0xf << ETH_TD0_CC_BIT) |
paul@43 | 624 | #define ETH_TD0_ED (1 << 2) |
paul@43 | 625 | #define ETH_TD0_UF (1 << 1) |
paul@43 | 626 | #define ETH_TD0_DF (1 << 0) |
paul@43 | 627 | |
paul@43 | 628 | /* Transmit Descriptor 1 (ETH_TD1) Bits */ |
paul@43 | 629 | |
paul@43 | 630 | #define ETH_TD1_IC (1 << 31) |
paul@43 | 631 | #define ETH_TD1_LS (1 << 30) |
paul@43 | 632 | #define ETH_TD1_FS (1 << 29) |
paul@43 | 633 | #define ETH_TD1_AC (1 << 26) |
paul@43 | 634 | #define ETH_TD1_TER (1 << 25) |
paul@43 | 635 | #define ETH_TD1_TCH (1 << 24) |
paul@43 | 636 | #define ETH_TD1_DPD (1 << 23) |
paul@43 | 637 | #define ETH_TD1_TBS2_BIT 11 |
paul@43 | 638 | #define ETH_TD1_TBS2_MASK (0x7ff << ETH_TD1_TBS2_BIT) |
paul@43 | 639 | #define ETH_TD1_TBS1_BIT 0 |
paul@43 | 640 | #define ETH_TD1_TBS1_MASK (0x7ff << ETH_TD1_TBS1_BIT) |
paul@43 | 641 | |
paul@43 | 642 | |
paul@43 | 643 | |
paul@43 | 644 | |
paul@43 | 645 | /************************************************************************* |
paul@43 | 646 | * WDT |
paul@43 | 647 | *************************************************************************/ |
paul@43 | 648 | #define WDT_WTCSR (WDT_BASE + 0x00) |
paul@43 | 649 | #define WDT_WTCNT (WDT_BASE + 0x04) |
paul@43 | 650 | |
paul@43 | 651 | #define REG_WDT_WTCSR REG8(WDT_WTCSR) |
paul@43 | 652 | #define REG_WDT_WTCNT REG32(WDT_WTCNT) |
paul@43 | 653 | |
paul@43 | 654 | #define WDT_WTCSR_START (1 << 4) |
paul@43 | 655 | |
paul@43 | 656 | |
paul@43 | 657 | |
paul@43 | 658 | |
paul@43 | 659 | /************************************************************************* |
paul@43 | 660 | * OST |
paul@43 | 661 | *************************************************************************/ |
paul@43 | 662 | #define OST_TER (OST_BASE + 0x00) |
paul@43 | 663 | #define OST_TRDR(n) (OST_BASE + 0x10 + ((n) * 0x20)) |
paul@43 | 664 | #define OST_TCNT(n) (OST_BASE + 0x14 + ((n) * 0x20)) |
paul@43 | 665 | #define OST_TCSR(n) (OST_BASE + 0x18 + ((n) * 0x20)) |
paul@43 | 666 | #define OST_TCRB(n) (OST_BASE + 0x1c + ((n) * 0x20)) |
paul@43 | 667 | |
paul@43 | 668 | #define REG_OST_TER REG8(OST_TER) |
paul@43 | 669 | #define REG_OST_TRDR(n) REG32(OST_TRDR((n))) |
paul@43 | 670 | #define REG_OST_TCNT(n) REG32(OST_TCNT((n))) |
paul@43 | 671 | #define REG_OST_TCSR(n) REG16(OST_TCSR((n))) |
paul@43 | 672 | #define REG_OST_TCRB(n) REG32(OST_TCRB((n))) |
paul@43 | 673 | |
paul@43 | 674 | #define OST_TCSR_BUSY (1 << 7) |
paul@43 | 675 | #define OST_TCSR_UF (1 << 6) |
paul@43 | 676 | #define OST_TCSR_UIE (1 << 5) |
paul@43 | 677 | #define OST_TCSR_CKS_BIT 0 |
paul@43 | 678 | #define OST_TCSR_CKS_MASK (0x07 << OST_TCSR_CKS_BIT) |
paul@43 | 679 | #define OST_TCSR_CKS_PCLK_4 (0 << OST_TCSR_CKS_BIT) |
paul@43 | 680 | #define OST_TCSR_CKS_PCLK_16 (1 << OST_TCSR_CKS_BIT) |
paul@43 | 681 | #define OST_TCSR_CKS_PCLK_64 (2 << OST_TCSR_CKS_BIT) |
paul@43 | 682 | #define OST_TCSR_CKS_PCLK_256 (3 << OST_TCSR_CKS_BIT) |
paul@43 | 683 | #define OST_TCSR_CKS_RTCCLK (4 << OST_TCSR_CKS_BIT) |
paul@43 | 684 | #define OST_TCSR_CKS_EXTAL (5 << OST_TCSR_CKS_BIT) |
paul@43 | 685 | |
paul@43 | 686 | #define OST_TCSR0 OST_TCSR(0) |
paul@43 | 687 | #define OST_TCSR1 OST_TCSR(1) |
paul@43 | 688 | #define OST_TCSR2 OST_TCSR(2) |
paul@43 | 689 | #define OST_TRDR0 OST_TRDR(0) |
paul@43 | 690 | #define OST_TRDR1 OST_TRDR(1) |
paul@43 | 691 | #define OST_TRDR2 OST_TRDR(2) |
paul@43 | 692 | #define OST_TCNT0 OST_TCNT(0) |
paul@43 | 693 | #define OST_TCNT1 OST_TCNT(1) |
paul@43 | 694 | #define OST_TCNT2 OST_TCNT(2) |
paul@43 | 695 | #define OST_TCRB0 OST_TCRB(0) |
paul@43 | 696 | #define OST_TCRB1 OST_TCRB(1) |
paul@43 | 697 | #define OST_TCRB2 OST_TCRB(2) |
paul@43 | 698 | |
paul@43 | 699 | /************************************************************************* |
paul@43 | 700 | * UART |
paul@43 | 701 | *************************************************************************/ |
paul@43 | 702 | |
paul@43 | 703 | #define IRDA_BASE UART0_BASE |
paul@43 | 704 | #define UART_BASE UART0_BASE |
paul@43 | 705 | #define UART_OFF 0x1000 |
paul@43 | 706 | |
paul@43 | 707 | /* register offset */ |
paul@43 | 708 | #define OFF_RDR (0x00) /* R 8b H'xx */ |
paul@43 | 709 | #define OFF_TDR (0x00) /* W 8b H'xx */ |
paul@43 | 710 | #define OFF_DLLR (0x00) /* RW 8b H'00 */ |
paul@43 | 711 | #define OFF_DLHR (0x04) /* RW 8b H'00 */ |
paul@43 | 712 | #define OFF_IER (0x04) /* RW 8b H'00 */ |
paul@43 | 713 | #define OFF_ISR (0x08) /* R 8b H'01 */ |
paul@43 | 714 | #define OFF_FCR (0x08) /* W 8b H'00 */ |
paul@43 | 715 | #define OFF_LCR (0x0C) /* RW 8b H'00 */ |
paul@43 | 716 | #define OFF_MCR (0x10) /* RW 8b H'00 */ |
paul@43 | 717 | #define OFF_LSR (0x14) /* R 8b H'00 */ |
paul@43 | 718 | #define OFF_MSR (0x18) /* R 8b H'00 */ |
paul@43 | 719 | #define OFF_SPR (0x1C) /* RW 8b H'00 */ |
paul@43 | 720 | #define OFF_MCR (0x10) /* RW 8b H'00 */ |
paul@43 | 721 | #define OFF_SIRCR (0x20) /* RW 8b H'00, UART0 */ |
paul@43 | 722 | |
paul@43 | 723 | /* register address */ |
paul@43 | 724 | #define UART0_RDR (UART0_BASE + OFF_RDR) |
paul@43 | 725 | #define UART0_TDR (UART0_BASE + OFF_TDR) |
paul@43 | 726 | #define UART0_DLLR (UART0_BASE + OFF_DLLR) |
paul@43 | 727 | #define UART0_DLHR (UART0_BASE + OFF_DLHR) |
paul@43 | 728 | #define UART0_IER (UART0_BASE + OFF_IER) |
paul@43 | 729 | #define UART0_ISR (UART0_BASE + OFF_ISR) |
paul@43 | 730 | #define UART0_FCR (UART0_BASE + OFF_FCR) |
paul@43 | 731 | #define UART0_LCR (UART0_BASE + OFF_LCR) |
paul@43 | 732 | #define UART0_MCR (UART0_BASE + OFF_MCR) |
paul@43 | 733 | #define UART0_LSR (UART0_BASE + OFF_LSR) |
paul@43 | 734 | #define UART0_MSR (UART0_BASE + OFF_MSR) |
paul@43 | 735 | #define UART0_SPR (UART0_BASE + OFF_SPR) |
paul@43 | 736 | #define UART0_SIRCR (UART0_BASE + OFF_SIRCR) |
paul@43 | 737 | |
paul@43 | 738 | #define UART1_RDR (UART1_BASE + OFF_RDR) |
paul@43 | 739 | #define UART1_TDR (UART1_BASE + OFF_TDR) |
paul@43 | 740 | #define UART1_DLLR (UART1_BASE + OFF_DLLR) |
paul@43 | 741 | #define UART1_DLHR (UART1_BASE + OFF_DLHR) |
paul@43 | 742 | #define UART1_IER (UART1_BASE + OFF_IER) |
paul@43 | 743 | #define UART1_ISR (UART1_BASE + OFF_ISR) |
paul@43 | 744 | #define UART1_FCR (UART1_BASE + OFF_FCR) |
paul@43 | 745 | #define UART1_LCR (UART1_BASE + OFF_LCR) |
paul@43 | 746 | #define UART1_MCR (UART1_BASE + OFF_MCR) |
paul@43 | 747 | #define UART1_LSR (UART1_BASE + OFF_LSR) |
paul@43 | 748 | #define UART1_MSR (UART1_BASE + OFF_MSR) |
paul@43 | 749 | #define UART1_SPR (UART1_BASE + OFF_SPR) |
paul@43 | 750 | #define UART1_SIRCR (UART1_BASE + OFF_SIRCR) |
paul@43 | 751 | |
paul@43 | 752 | #define UART2_RDR (UART2_BASE + OFF_RDR) |
paul@43 | 753 | #define UART2_TDR (UART2_BASE + OFF_TDR) |
paul@43 | 754 | #define UART2_DLLR (UART2_BASE + OFF_DLLR) |
paul@43 | 755 | #define UART2_DLHR (UART2_BASE + OFF_DLHR) |
paul@43 | 756 | #define UART2_IER (UART2_BASE + OFF_IER) |
paul@43 | 757 | #define UART2_ISR (UART2_BASE + OFF_ISR) |
paul@43 | 758 | #define UART2_FCR (UART2_BASE + OFF_FCR) |
paul@43 | 759 | #define UART2_LCR (UART2_BASE + OFF_LCR) |
paul@43 | 760 | #define UART2_MCR (UART2_BASE + OFF_MCR) |
paul@43 | 761 | #define UART2_LSR (UART2_BASE + OFF_LSR) |
paul@43 | 762 | #define UART2_MSR (UART2_BASE + OFF_MSR) |
paul@43 | 763 | #define UART2_SPR (UART2_BASE + OFF_SPR) |
paul@43 | 764 | #define UART2_SIRCR (UART2_BASE + OFF_SIRCR) |
paul@43 | 765 | |
paul@43 | 766 | #define UART3_RDR (UART3_BASE + OFF_RDR) |
paul@43 | 767 | #define UART3_TDR (UART3_BASE + OFF_TDR) |
paul@43 | 768 | #define UART3_DLLR (UART3_BASE + OFF_DLLR) |
paul@43 | 769 | #define UART3_DLHR (UART3_BASE + OFF_DLHR) |
paul@43 | 770 | #define UART3_IER (UART3_BASE + OFF_IER) |
paul@43 | 771 | #define UART3_ISR (UART3_BASE + OFF_ISR) |
paul@43 | 772 | #define UART3_FCR (UART3_BASE + OFF_FCR) |
paul@43 | 773 | #define UART3_LCR (UART3_BASE + OFF_LCR) |
paul@43 | 774 | #define UART3_MCR (UART3_BASE + OFF_MCR) |
paul@43 | 775 | #define UART3_LSR (UART3_BASE + OFF_LSR) |
paul@43 | 776 | #define UART3_MSR (UART3_BASE + OFF_MSR) |
paul@43 | 777 | #define UART3_SPR (UART3_BASE + OFF_SPR) |
paul@43 | 778 | #define UART3_SIRCR (UART3_BASE + OFF_SIRCR) |
paul@43 | 779 | |
paul@43 | 780 | /* |
paul@43 | 781 | * Define macros for UART_IER |
paul@43 | 782 | * UART Interrupt Enable Register |
paul@43 | 783 | */ |
paul@43 | 784 | #define UART_IER_RIE (1 << 0) /* 0: receive fifo "full" interrupt disable */ |
paul@43 | 785 | #define UART_IER_TIE (1 << 1) /* 0: transmit fifo "empty" interrupt disable */ |
paul@43 | 786 | #define UART_IER_RLIE (1 << 2) /* 0: receive line status interrupt disable */ |
paul@43 | 787 | #define UART_IER_MIE (1 << 3) /* 0: modem status interrupt disable */ |
paul@43 | 788 | #define UART_IER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */ |
paul@43 | 789 | |
paul@43 | 790 | /* |
paul@43 | 791 | * Define macros for UART_ISR |
paul@43 | 792 | * UART Interrupt Status Register |
paul@43 | 793 | */ |
paul@43 | 794 | #define UART_ISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */ |
paul@43 | 795 | #define UART_ISR_IID (7 << 1) /* Source of Interrupt */ |
paul@43 | 796 | #define UART_ISR_IID_MSI (0 << 1) /* Modem status interrupt */ |
paul@43 | 797 | #define UART_ISR_IID_THRI (1 << 1) /* Transmitter holding register empty */ |
paul@43 | 798 | #define UART_ISR_IID_RDI (2 << 1) /* Receiver data interrupt */ |
paul@43 | 799 | #define UART_ISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */ |
paul@43 | 800 | #define UART_ISR_FFMS (3 << 6) /* FIFO mode select, set when UART_FCR.FE is set to 1 */ |
paul@43 | 801 | #define UART_ISR_FFMS_NO_FIFO (0 << 6) |
paul@43 | 802 | #define UART_ISR_FFMS_FIFO_MODE (3 << 6) |
paul@43 | 803 | |
paul@43 | 804 | /* |
paul@43 | 805 | * Define macros for UART_FCR |
paul@43 | 806 | * UART FIFO Control Register |
paul@43 | 807 | */ |
paul@43 | 808 | #define UART_FCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */ |
paul@43 | 809 | #define UART_FCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */ |
paul@43 | 810 | #define UART_FCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */ |
paul@43 | 811 | #define UART_FCR_DMS (1 << 3) /* 0: disable DMA mode */ |
paul@43 | 812 | #define UART_FCR_UUE (1 << 4) /* 0: disable UART */ |
paul@43 | 813 | #define UART_FCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */ |
paul@43 | 814 | #define UART_FCR_RTRG_1 (0 << 6) |
paul@43 | 815 | #define UART_FCR_RTRG_4 (1 << 6) |
paul@43 | 816 | #define UART_FCR_RTRG_8 (2 << 6) |
paul@43 | 817 | #define UART_FCR_RTRG_15 (3 << 6) |
paul@43 | 818 | |
paul@43 | 819 | /* |
paul@43 | 820 | * Define macros for UART_LCR |
paul@43 | 821 | * UART Line Control Register |
paul@43 | 822 | */ |
paul@43 | 823 | #define UART_LCR_WLEN (3 << 0) /* word length */ |
paul@43 | 824 | #define UART_LCR_WLEN_5 (0 << 0) |
paul@43 | 825 | #define UART_LCR_WLEN_6 (1 << 0) |
paul@43 | 826 | #define UART_LCR_WLEN_7 (2 << 0) |
paul@43 | 827 | #define UART_LCR_WLEN_8 (3 << 0) |
paul@43 | 828 | #define UART_LCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 |
paul@43 | 829 | 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ |
paul@43 | 830 | #define UART_LCR_STOP_1 (0 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 |
paul@43 | 831 | 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ |
paul@43 | 832 | #define UART_LCR_STOP_2 (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 |
paul@43 | 833 | 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ |
paul@43 | 834 | |
paul@43 | 835 | #define UART_LCR_PE (1 << 3) /* 0: parity disable */ |
paul@43 | 836 | #define UART_LCR_PROE (1 << 4) /* 0: even parity 1: odd parity */ |
paul@43 | 837 | #define UART_LCR_SPAR (1 << 5) /* 0: sticky parity disable */ |
paul@43 | 838 | #define UART_LCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */ |
paul@43 | 839 | #define UART_LCR_DLAB (1 << 7) /* 0: access UART_RDR/TDR/IER 1: access UART_DLLR/DLHR */ |
paul@43 | 840 | |
paul@43 | 841 | /* |
paul@43 | 842 | * Define macros for UART_LSR |
paul@43 | 843 | * UART Line Status Register |
paul@43 | 844 | */ |
paul@43 | 845 | #define UART_LSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */ |
paul@43 | 846 | #define UART_LSR_ORER (1 << 1) /* 0: no overrun error */ |
paul@43 | 847 | #define UART_LSR_PER (1 << 2) /* 0: no parity error */ |
paul@43 | 848 | #define UART_LSR_FER (1 << 3) /* 0; no framing error */ |
paul@43 | 849 | #define UART_LSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */ |
paul@43 | 850 | #define UART_LSR_TDRQ (1 << 5) /* 1: transmit FIFO half "empty" */ |
paul@43 | 851 | #define UART_LSR_TEMT (1 << 6) /* 1: transmit FIFO and shift registers empty */ |
paul@43 | 852 | #define UART_LSR_RFER (1 << 7) /* 0: no receive error 1: receive error in FIFO mode */ |
paul@43 | 853 | |
paul@43 | 854 | /* |
paul@43 | 855 | * Define macros for UART_MCR |
paul@43 | 856 | * UART Modem Control Register |
paul@43 | 857 | */ |
paul@43 | 858 | #define UART_MCR_DTR (1 << 0) /* 0: DTR_ ouput high */ |
paul@43 | 859 | #define UART_MCR_RTS (1 << 1) /* 0: RTS_ output high */ |
paul@43 | 860 | #define UART_MCR_OUT1 (1 << 2) /* 0: UART_MSR.RI is set to 0 and RI_ input high */ |
paul@43 | 861 | #define UART_MCR_OUT2 (1 << 3) /* 0: UART_MSR.DCD is set to 0 and DCD_ input high */ |
paul@43 | 862 | #define UART_MCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */ |
paul@43 | 863 | #define UART_MCR_MCE (1 << 7) /* 0: modem function is disable */ |
paul@43 | 864 | |
paul@43 | 865 | /* |
paul@43 | 866 | * Define macros for UART_MSR |
paul@43 | 867 | * UART Modem Status Register |
paul@43 | 868 | */ |
paul@43 | 869 | #define UART_MSR_DCTS (1 << 0) /* 0: no change on CTS_ pin since last read of UART_MSR */ |
paul@43 | 870 | #define UART_MSR_DDSR (1 << 1) /* 0: no change on DSR_ pin since last read of UART_MSR */ |
paul@43 | 871 | #define UART_MSR_DRI (1 << 2) /* 0: no change on RI_ pin since last read of UART_MSR */ |
paul@43 | 872 | #define UART_MSR_DDCD (1 << 3) /* 0: no change on DCD_ pin since last read of UART_MSR */ |
paul@43 | 873 | #define UART_MSR_CTS (1 << 4) /* 0: CTS_ pin is high */ |
paul@43 | 874 | #define UART_MSR_DSR (1 << 5) /* 0: DSR_ pin is high */ |
paul@43 | 875 | #define UART_MSR_RI (1 << 6) /* 0: RI_ pin is high */ |
paul@43 | 876 | #define UART_MSR_DCD (1 << 7) /* 0: DCD_ pin is high */ |
paul@43 | 877 | |
paul@43 | 878 | /* |
paul@43 | 879 | * Define macros for SIRCR |
paul@43 | 880 | * Slow IrDA Control Register |
paul@43 | 881 | */ |
paul@43 | 882 | #define SIRCR_TSIRE (1 << 0) /* 0: transmitter is in UART mode 1: IrDA mode */ |
paul@43 | 883 | #define SIRCR_RSIRE (1 << 1) /* 0: receiver is in UART mode 1: IrDA mode */ |
paul@43 | 884 | #define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length |
paul@43 | 885 | 1: 0 pulse width is 1.6us for 115.2Kbps */ |
paul@43 | 886 | #define SIRCR_TXPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */ |
paul@43 | 887 | #define SIRCR_RXPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */ |
paul@43 | 888 | |
paul@43 | 889 | |
paul@43 | 890 | |
paul@43 | 891 | /************************************************************************* |
paul@43 | 892 | * INTC |
paul@43 | 893 | *************************************************************************/ |
paul@43 | 894 | #define INTC_ISR (INTC_BASE + 0x00) |
paul@43 | 895 | #define INTC_IMR (INTC_BASE + 0x04) |
paul@43 | 896 | #define INTC_IMSR (INTC_BASE + 0x08) |
paul@43 | 897 | #define INTC_IMCR (INTC_BASE + 0x0c) |
paul@43 | 898 | #define INTC_IPR (INTC_BASE + 0x10) |
paul@43 | 899 | |
paul@43 | 900 | #define REG_INTC_ISR REG32(INTC_ISR) |
paul@43 | 901 | #define REG_INTC_IMR REG32(INTC_IMR) |
paul@43 | 902 | #define REG_INTC_IMSR REG32(INTC_IMSR) |
paul@43 | 903 | #define REG_INTC_IMCR REG32(INTC_IMCR) |
paul@43 | 904 | #define REG_INTC_IPR REG32(INTC_IPR) |
paul@43 | 905 | |
paul@43 | 906 | #define IRQ_I2C 1 |
paul@43 | 907 | #define IRQ_PS2 2 |
paul@43 | 908 | #define IRQ_UPRT 3 |
paul@43 | 909 | #define IRQ_CORE 4 |
paul@43 | 910 | #define IRQ_UART3 6 |
paul@43 | 911 | #define IRQ_UART2 7 |
paul@43 | 912 | #define IRQ_UART1 8 |
paul@43 | 913 | #define IRQ_UART0 9 |
paul@43 | 914 | #define IRQ_SCC1 10 |
paul@43 | 915 | #define IRQ_SCC0 11 |
paul@43 | 916 | #define IRQ_UDC 12 |
paul@43 | 917 | #define IRQ_UHC 13 |
paul@43 | 918 | #define IRQ_MSC 14 |
paul@43 | 919 | #define IRQ_RTC 15 |
paul@43 | 920 | #define IRQ_FIR 16 |
paul@43 | 921 | #define IRQ_SSI 17 |
paul@43 | 922 | #define IRQ_CIM 18 |
paul@43 | 923 | #define IRQ_ETH 19 |
paul@43 | 924 | #define IRQ_AIC 20 |
paul@43 | 925 | #define IRQ_DMAC 21 |
paul@43 | 926 | #define IRQ_OST2 22 |
paul@43 | 927 | #define IRQ_OST1 23 |
paul@43 | 928 | #define IRQ_OST0 24 |
paul@43 | 929 | #define IRQ_GPIO3 25 |
paul@43 | 930 | #define IRQ_GPIO2 26 |
paul@43 | 931 | #define IRQ_GPIO1 27 |
paul@43 | 932 | #define IRQ_GPIO0 28 |
paul@43 | 933 | #define IRQ_LCD 30 |
paul@43 | 934 | |
paul@43 | 935 | |
paul@43 | 936 | |
paul@43 | 937 | |
paul@43 | 938 | /************************************************************************* |
paul@43 | 939 | * CIM |
paul@43 | 940 | *************************************************************************/ |
paul@43 | 941 | #define CIM_CFG (CIM_BASE + 0x0000) |
paul@43 | 942 | #define CIM_CTRL (CIM_BASE + 0x0004) |
paul@43 | 943 | #define CIM_STATE (CIM_BASE + 0x0008) |
paul@43 | 944 | #define CIM_IID (CIM_BASE + 0x000C) |
paul@43 | 945 | #define CIM_RXFIFO (CIM_BASE + 0x0010) |
paul@43 | 946 | #define CIM_DA (CIM_BASE + 0x0020) |
paul@43 | 947 | #define CIM_FA (CIM_BASE + 0x0024) |
paul@43 | 948 | #define CIM_FID (CIM_BASE + 0x0028) |
paul@43 | 949 | #define CIM_CMD (CIM_BASE + 0x002C) |
paul@43 | 950 | |
paul@43 | 951 | #define REG_CIM_CFG REG32(CIM_CFG) |
paul@43 | 952 | #define REG_CIM_CTRL REG32(CIM_CTRL) |
paul@43 | 953 | #define REG_CIM_STATE REG32(CIM_STATE) |
paul@43 | 954 | #define REG_CIM_IID REG32(CIM_IID) |
paul@43 | 955 | #define REG_CIM_RXFIFO REG32(CIM_RXFIFO) |
paul@43 | 956 | #define REG_CIM_DA REG32(CIM_DA) |
paul@43 | 957 | #define REG_CIM_FA REG32(CIM_FA) |
paul@43 | 958 | #define REG_CIM_FID REG32(CIM_FID) |
paul@43 | 959 | #define REG_CIM_CMD REG32(CIM_CMD) |
paul@43 | 960 | |
paul@43 | 961 | /* CIM Configuration Register (CIM_CFG) */ |
paul@43 | 962 | |
paul@43 | 963 | #define CIM_CFG_INV_DAT (1 << 15) |
paul@43 | 964 | #define CIM_CFG_VSP (1 << 14) |
paul@43 | 965 | #define CIM_CFG_HSP (1 << 13) |
paul@43 | 966 | #define CIM_CFG_PCP (1 << 12) |
paul@43 | 967 | #define CIM_CFG_DUMMY_ZERO (1 << 9) |
paul@43 | 968 | #define CIM_CFG_EXT_VSYNC (1 << 8) |
paul@43 | 969 | #define CIM_CFG_PACK_BIT 4 |
paul@43 | 970 | #define CIM_CFG_PACK_MASK (0x7 << CIM_CFG_PACK_BIT) |
paul@43 | 971 | #define CIM_CFG_PACK_0 (0 << CIM_CFG_PACK_BIT) |
paul@43 | 972 | #define CIM_CFG_PACK_1 (1 << CIM_CFG_PACK_BIT) |
paul@43 | 973 | #define CIM_CFG_PACK_2 (2 << CIM_CFG_PACK_BIT) |
paul@43 | 974 | #define CIM_CFG_PACK_3 (3 << CIM_CFG_PACK_BIT) |
paul@43 | 975 | #define CIM_CFG_PACK_4 (4 << CIM_CFG_PACK_BIT) |
paul@43 | 976 | #define CIM_CFG_PACK_5 (5 << CIM_CFG_PACK_BIT) |
paul@43 | 977 | #define CIM_CFG_PACK_6 (6 << CIM_CFG_PACK_BIT) |
paul@43 | 978 | #define CIM_CFG_PACK_7 (7 << CIM_CFG_PACK_BIT) |
paul@43 | 979 | #define CIM_CFG_DSM_BIT 0 |
paul@43 | 980 | #define CIM_CFG_DSM_MASK (0x3 << CIM_CFG_DSM_BIT) |
paul@43 | 981 | #define CIM_CFG_DSM_CPM (0 << CIM_CFG_DSM_BIT) /* CCIR656 Progressive Mode */ |
paul@43 | 982 | #define CIM_CFG_DSM_CIM (1 << CIM_CFG_DSM_BIT) /* CCIR656 Interlace Mode */ |
paul@43 | 983 | #define CIM_CFG_DSM_GCM (2 << CIM_CFG_DSM_BIT) /* Gated Clock Mode */ |
paul@43 | 984 | #define CIM_CFG_DSM_NGCM (3 << CIM_CFG_DSM_BIT) /* Non-Gated Clock Mode */ |
paul@43 | 985 | |
paul@43 | 986 | /* CIM Control Register (CIM_CTRL) */ |
paul@43 | 987 | |
paul@43 | 988 | #define CIM_CTRL_MCLKDIV_BIT 24 |
paul@43 | 989 | #define CIM_CTRL_MCLKDIV_MASK (0xff << CIM_CTRL_MCLKDIV_BIT) |
paul@43 | 990 | #define CIM_CTRL_FRC_BIT 16 |
paul@43 | 991 | #define CIM_CTRL_FRC_MASK (0xf << CIM_CTRL_FRC_BIT) |
paul@43 | 992 | #define CIM_CTRL_FRC_1 (0x0 << CIM_CTRL_FRC_BIT) /* Sample every frame */ |
paul@43 | 993 | #define CIM_CTRL_FRC_2 (0x1 << CIM_CTRL_FRC_BIT) /* Sample 1/2 frame */ |
paul@43 | 994 | #define CIM_CTRL_FRC_3 (0x2 << CIM_CTRL_FRC_BIT) /* Sample 1/3 frame */ |
paul@43 | 995 | #define CIM_CTRL_FRC_4 (0x3 << CIM_CTRL_FRC_BIT) /* Sample 1/4 frame */ |
paul@43 | 996 | #define CIM_CTRL_FRC_5 (0x4 << CIM_CTRL_FRC_BIT) /* Sample 1/5 frame */ |
paul@43 | 997 | #define CIM_CTRL_FRC_6 (0x5 << CIM_CTRL_FRC_BIT) /* Sample 1/6 frame */ |
paul@43 | 998 | #define CIM_CTRL_FRC_7 (0x6 << CIM_CTRL_FRC_BIT) /* Sample 1/7 frame */ |
paul@43 | 999 | #define CIM_CTRL_FRC_8 (0x7 << CIM_CTRL_FRC_BIT) /* Sample 1/8 frame */ |
paul@43 | 1000 | #define CIM_CTRL_FRC_9 (0x8 << CIM_CTRL_FRC_BIT) /* Sample 1/9 frame */ |
paul@43 | 1001 | #define CIM_CTRL_FRC_10 (0x9 << CIM_CTRL_FRC_BIT) /* Sample 1/10 frame */ |
paul@43 | 1002 | #define CIM_CTRL_FRC_11 (0xA << CIM_CTRL_FRC_BIT) /* Sample 1/11 frame */ |
paul@43 | 1003 | #define CIM_CTRL_FRC_12 (0xB << CIM_CTRL_FRC_BIT) /* Sample 1/12 frame */ |
paul@43 | 1004 | #define CIM_CTRL_FRC_13 (0xC << CIM_CTRL_FRC_BIT) /* Sample 1/13 frame */ |
paul@43 | 1005 | #define CIM_CTRL_FRC_14 (0xD << CIM_CTRL_FRC_BIT) /* Sample 1/14 frame */ |
paul@43 | 1006 | #define CIM_CTRL_FRC_15 (0xE << CIM_CTRL_FRC_BIT) /* Sample 1/15 frame */ |
paul@43 | 1007 | #define CIM_CTRL_FRC_16 (0xF << CIM_CTRL_FRC_BIT) /* Sample 1/16 frame */ |
paul@43 | 1008 | #define CIM_CTRL_VDDM (1 << 13) |
paul@43 | 1009 | #define CIM_CTRL_DMA_SOFM (1 << 12) |
paul@43 | 1010 | #define CIM_CTRL_DMA_EOFM (1 << 11) |
paul@43 | 1011 | #define CIM_CTRL_DMA_STOPM (1 << 10) |
paul@43 | 1012 | #define CIM_CTRL_RXF_TRIGM (1 << 9) |
paul@43 | 1013 | #define CIM_CTRL_RXF_OFM (1 << 8) |
paul@43 | 1014 | #define CIM_CTRL_RXF_TRIG_BIT 4 |
paul@43 | 1015 | #define CIM_CTRL_RXF_TRIG_MASK (0x7 << CIM_CTRL_RXF_TRIG_BIT) |
paul@43 | 1016 | #define CIM_CTRL_RXF_TRIG_4 (0 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 4 */ |
paul@43 | 1017 | #define CIM_CTRL_RXF_TRIG_8 (1 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 8 */ |
paul@43 | 1018 | #define CIM_CTRL_RXF_TRIG_12 (2 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 12 */ |
paul@43 | 1019 | #define CIM_CTRL_RXF_TRIG_16 (3 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 16 */ |
paul@43 | 1020 | #define CIM_CTRL_RXF_TRIG_20 (4 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 20 */ |
paul@43 | 1021 | #define CIM_CTRL_RXF_TRIG_24 (5 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 24 */ |
paul@43 | 1022 | #define CIM_CTRL_RXF_TRIG_28 (6 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 28 */ |
paul@43 | 1023 | #define CIM_CTRL_RXF_TRIG_32 (7 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 32 */ |
paul@43 | 1024 | #define CIM_CTRL_DMA_EN (1 << 2) |
paul@43 | 1025 | #define CIM_CTRL_RXF_RST (1 << 1) |
paul@43 | 1026 | #define CIM_CTRL_ENA (1 << 0) |
paul@43 | 1027 | |
paul@43 | 1028 | /* CIM State Register (CIM_STATE) */ |
paul@43 | 1029 | |
paul@43 | 1030 | #define CIM_STATE_DMA_SOF (1 << 6) |
paul@43 | 1031 | #define CIM_STATE_DMA_EOF (1 << 5) |
paul@43 | 1032 | #define CIM_STATE_DMA_STOP (1 << 4) |
paul@43 | 1033 | #define CIM_STATE_RXF_OF (1 << 3) |
paul@43 | 1034 | #define CIM_STATE_RXF_TRIG (1 << 2) |
paul@43 | 1035 | #define CIM_STATE_RXF_EMPTY (1 << 1) |
paul@43 | 1036 | #define CIM_STATE_VDD (1 << 0) |
paul@43 | 1037 | |
paul@43 | 1038 | /* CIM DMA Command Register (CIM_CMD) */ |
paul@43 | 1039 | |
paul@43 | 1040 | #define CIM_CMD_SOFINT (1 << 31) |
paul@43 | 1041 | #define CIM_CMD_EOFINT (1 << 30) |
paul@43 | 1042 | #define CIM_CMD_STOP (1 << 28) |
paul@43 | 1043 | #define CIM_CMD_LEN_BIT 0 |
paul@43 | 1044 | #define CIM_CMD_LEN_MASK (0xffffff << CIM_CMD_LEN_BIT) |
paul@43 | 1045 | |
paul@43 | 1046 | |
paul@43 | 1047 | |
paul@43 | 1048 | |
paul@43 | 1049 | /************************************************************************* |
paul@43 | 1050 | * PWM |
paul@43 | 1051 | *************************************************************************/ |
paul@43 | 1052 | #define PWM_CTR(n) (PWM##n##_BASE + 0x000) |
paul@43 | 1053 | #define PWM_PER(n) (PWM##n##_BASE + 0x004) |
paul@43 | 1054 | #define PWM_DUT(n) (PWM##n##_BASE + 0x008) |
paul@43 | 1055 | |
paul@43 | 1056 | #define REG_PWM_CTR(n) REG8(PWM_CTR(n)) |
paul@43 | 1057 | #define REG_PWM_PER(n) REG16(PWM_PER(n)) |
paul@43 | 1058 | #define REG_PWM_DUT(n) REG16(PWM_DUT(n)) |
paul@43 | 1059 | |
paul@43 | 1060 | /* PWM Control Register (PWM_CTR) */ |
paul@43 | 1061 | |
paul@43 | 1062 | #define PWM_CTR_EN (1 << 7) |
paul@43 | 1063 | #define PWM_CTR_SD (1 << 6) |
paul@43 | 1064 | #define PWM_CTR_PRESCALE_BIT 0 |
paul@43 | 1065 | #define PWM_CTR_PRESCALE_MASK (0x3f << PWM_CTR_PRESCALE_BIT) |
paul@43 | 1066 | |
paul@43 | 1067 | /* PWM Period Register (PWM_PER) */ |
paul@43 | 1068 | |
paul@43 | 1069 | #define PWM_PER_PERIOD_BIT 0 |
paul@43 | 1070 | #define PWM_PER_PERIOD_MASK (0x3ff << PWM_PER_PERIOD_BIT) |
paul@43 | 1071 | |
paul@43 | 1072 | /* PWM Duty Register (PWM_DUT) */ |
paul@43 | 1073 | |
paul@43 | 1074 | #define PWM_DUT_FDUTY (1 << 10) |
paul@43 | 1075 | #define PWM_DUT_DUTY_BIT 0 |
paul@43 | 1076 | #define PWM_DUT_DUTY_MASK (0x3ff << PWM_DUT_DUTY_BIT) |
paul@43 | 1077 | |
paul@43 | 1078 | |
paul@43 | 1079 | |
paul@43 | 1080 | |
paul@43 | 1081 | /************************************************************************* |
paul@43 | 1082 | * EMC |
paul@43 | 1083 | *************************************************************************/ |
paul@43 | 1084 | #define EMC_BCR (EMC_BASE + 0x00) |
paul@43 | 1085 | #define EMC_SMCR0 (EMC_BASE + 0x10) |
paul@43 | 1086 | #define EMC_SMCR1 (EMC_BASE + 0x14) |
paul@43 | 1087 | #define EMC_SMCR2 (EMC_BASE + 0x18) |
paul@43 | 1088 | #define EMC_SMCR3 (EMC_BASE + 0x1c) |
paul@43 | 1089 | #define EMC_SMCR4 (EMC_BASE + 0x20) |
paul@43 | 1090 | #define EMC_SMCR5 (EMC_BASE + 0x24) |
paul@43 | 1091 | #define EMC_SMCR6 (EMC_BASE + 0x28) |
paul@43 | 1092 | #define EMC_SMCR7 (EMC_BASE + 0x2c) |
paul@43 | 1093 | #define EMC_SACR0 (EMC_BASE + 0x30) |
paul@43 | 1094 | #define EMC_SACR1 (EMC_BASE + 0x34) |
paul@43 | 1095 | #define EMC_SACR2 (EMC_BASE + 0x38) |
paul@43 | 1096 | #define EMC_SACR3 (EMC_BASE + 0x3c) |
paul@43 | 1097 | #define EMC_SACR4 (EMC_BASE + 0x40) |
paul@43 | 1098 | #define EMC_SACR5 (EMC_BASE + 0x44) |
paul@43 | 1099 | #define EMC_SACR6 (EMC_BASE + 0x48) |
paul@43 | 1100 | #define EMC_SACR7 (EMC_BASE + 0x4c) |
paul@43 | 1101 | #define EMC_NFCSR (EMC_BASE + 0x50) |
paul@43 | 1102 | #define EMC_NFECC (EMC_BASE + 0x54) |
paul@43 | 1103 | #define EMC_PCCR1 (EMC_BASE + 0x60) |
paul@43 | 1104 | #define EMC_PCCR2 (EMC_BASE + 0x64) |
paul@43 | 1105 | #define EMC_PCCR3 (EMC_BASE + 0x68) |
paul@43 | 1106 | #define EMC_PCCR4 (EMC_BASE + 0x6c) |
paul@43 | 1107 | #define EMC_DMCR (EMC_BASE + 0x80) |
paul@43 | 1108 | #define EMC_RTCSR (EMC_BASE + 0x84) |
paul@43 | 1109 | #define EMC_RTCNT (EMC_BASE + 0x88) |
paul@43 | 1110 | #define EMC_RTCOR (EMC_BASE + 0x8c) |
paul@43 | 1111 | #define EMC_DMAR1 (EMC_BASE + 0x90) |
paul@43 | 1112 | #define EMC_DMAR2 (EMC_BASE + 0x94) |
paul@43 | 1113 | #define EMC_DMAR3 (EMC_BASE + 0x98) |
paul@43 | 1114 | #define EMC_DMAR4 (EMC_BASE + 0x9c) |
paul@43 | 1115 | |
paul@43 | 1116 | #define EMC_SDMR0 (EMC_BASE + 0xa000) |
paul@43 | 1117 | #define EMC_SDMR1 (EMC_BASE + 0xb000) |
paul@43 | 1118 | #define EMC_SDMR2 (EMC_BASE + 0xc000) |
paul@43 | 1119 | #define EMC_SDMR3 (EMC_BASE + 0xd000) |
paul@43 | 1120 | |
paul@43 | 1121 | /* NAND command/address/data port */ |
paul@43 | 1122 | #define NAND_DATAPORT 0xB4000000 /* read-write area */ |
paul@43 | 1123 | #define NAND_COMMPORT 0xB4040000 /* write only area */ |
paul@43 | 1124 | #define NAND_ADDRPORT 0xB4080000 /* write only area */ |
paul@43 | 1125 | |
paul@43 | 1126 | #define REG_EMC_BCR REG32(EMC_BCR) |
paul@43 | 1127 | #define REG_EMC_SMCR0 REG32(EMC_SMCR0) |
paul@43 | 1128 | #define REG_EMC_SMCR1 REG32(EMC_SMCR1) |
paul@43 | 1129 | #define REG_EMC_SMCR2 REG32(EMC_SMCR2) |
paul@43 | 1130 | #define REG_EMC_SMCR3 REG32(EMC_SMCR3) |
paul@43 | 1131 | #define REG_EMC_SMCR4 REG32(EMC_SMCR4) |
paul@43 | 1132 | #define REG_EMC_SMCR5 REG32(EMC_SMCR5) |
paul@43 | 1133 | #define REG_EMC_SMCR6 REG32(EMC_SMCR6) |
paul@43 | 1134 | #define REG_EMC_SMCR7 REG32(EMC_SMCR7) |
paul@43 | 1135 | #define REG_EMC_SACR0 REG32(EMC_SACR0) |
paul@43 | 1136 | #define REG_EMC_SACR1 REG32(EMC_SACR1) |
paul@43 | 1137 | #define REG_EMC_SACR2 REG32(EMC_SACR2) |
paul@43 | 1138 | #define REG_EMC_SACR3 REG32(EMC_SACR3) |
paul@43 | 1139 | #define REG_EMC_SACR4 REG32(EMC_SACR4) |
paul@43 | 1140 | #define REG_EMC_SACR5 REG32(EMC_SACR5) |
paul@43 | 1141 | #define REG_EMC_SACR6 REG32(EMC_SACR6) |
paul@43 | 1142 | #define REG_EMC_SACR7 REG32(EMC_SACR7) |
paul@43 | 1143 | #define REG_EMC_NFCSR REG32(EMC_NFCSR) |
paul@43 | 1144 | #define REG_EMC_NFECC REG32(EMC_NFECC) |
paul@43 | 1145 | #define REG_EMC_DMCR REG32(EMC_DMCR) |
paul@43 | 1146 | #define REG_EMC_RTCSR REG16(EMC_RTCSR) |
paul@43 | 1147 | #define REG_EMC_RTCNT REG16(EMC_RTCNT) |
paul@43 | 1148 | #define REG_EMC_RTCOR REG16(EMC_RTCOR) |
paul@43 | 1149 | #define REG_EMC_DMAR1 REG32(EMC_DMAR1) |
paul@43 | 1150 | #define REG_EMC_DMAR2 REG32(EMC_DMAR2) |
paul@43 | 1151 | #define REG_EMC_DMAR3 REG32(EMC_DMAR3) |
paul@43 | 1152 | #define REG_EMC_DMAR4 REG32(EMC_DMAR4) |
paul@43 | 1153 | #define REG_EMC_PCCR1 REG32(EMC_PCCR1) |
paul@43 | 1154 | #define REG_EMC_PCCR2 REG32(EMC_PCCR2) |
paul@43 | 1155 | #define REG_EMC_PCCR3 REG32(EMC_PCCR3) |
paul@43 | 1156 | #define REG_EMC_PCCR4 REG32(EMC_PCCR4) |
paul@43 | 1157 | |
paul@43 | 1158 | |
paul@43 | 1159 | #define EMC_BCR_BRE (1 << 1) |
paul@43 | 1160 | |
paul@43 | 1161 | #define EMC_SMCR_STRV_BIT 24 |
paul@43 | 1162 | #define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT) |
paul@43 | 1163 | #define EMC_SMCR_TAW_BIT 20 |
paul@43 | 1164 | #define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT) |
paul@43 | 1165 | #define EMC_SMCR_TBP_BIT 16 |
paul@43 | 1166 | #define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT) |
paul@43 | 1167 | #define EMC_SMCR_TAH_BIT 12 |
paul@43 | 1168 | #define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT) |
paul@43 | 1169 | #define EMC_SMCR_TAS_BIT 8 |
paul@43 | 1170 | #define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT) |
paul@43 | 1171 | #define EMC_SMCR_BW_BIT 6 |
paul@43 | 1172 | #define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT) |
paul@43 | 1173 | #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT) |
paul@43 | 1174 | #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT) |
paul@43 | 1175 | #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT) |
paul@43 | 1176 | #define EMC_SMCR_BCM (1 << 3) |
paul@43 | 1177 | #define EMC_SMCR_BL_BIT 1 |
paul@43 | 1178 | #define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT) |
paul@43 | 1179 | #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT) |
paul@43 | 1180 | #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT) |
paul@43 | 1181 | #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT) |
paul@43 | 1182 | #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT) |
paul@43 | 1183 | #define EMC_SMCR_SMT (1 << 0) |
paul@43 | 1184 | |
paul@43 | 1185 | #define EMC_SACR_BASE_BIT 8 |
paul@43 | 1186 | #define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT) |
paul@43 | 1187 | #define EMC_SACR_MASK_BIT 0 |
paul@43 | 1188 | #define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT) |
paul@43 | 1189 | |
paul@43 | 1190 | #define EMC_NFCSR_RB (1 << 7) |
paul@43 | 1191 | #define EMC_NFCSR_BOOT_SEL_BIT 4 |
paul@43 | 1192 | #define EMC_NFCSR_BOOT_SEL_MASK (0x07 << EMC_NFCSR_BOOT_SEL_BIT) |
paul@43 | 1193 | #define EMC_NFCSR_ERST (1 << 3) |
paul@43 | 1194 | #define EMC_NFCSR_ECCE (1 << 2) |
paul@43 | 1195 | #define EMC_NFCSR_FCE (1 << 1) |
paul@43 | 1196 | #define EMC_NFCSR_NFE (1 << 0) |
paul@43 | 1197 | |
paul@43 | 1198 | #define EMC_NFECC_ECC2_BIT 16 |
paul@43 | 1199 | #define EMC_NFECC_ECC2_MASK (0xff << EMC_NFECC_ECC2_BIT) |
paul@43 | 1200 | #define EMC_NFECC_ECC1_BIT 8 |
paul@43 | 1201 | #define EMC_NFECC_ECC1_MASK (0xff << EMC_NFECC_ECC1_BIT) |
paul@43 | 1202 | #define EMC_NFECC_ECC0_BIT 0 |
paul@43 | 1203 | #define EMC_NFECC_ECC0_MASK (0xff << EMC_NFECC_ECC0_BIT) |
paul@43 | 1204 | |
paul@43 | 1205 | #define EMC_DMCR_BW_BIT 31 |
paul@43 | 1206 | #define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT) |
paul@43 | 1207 | #define EMC_DMCR_BW_32 (0 << EMC_DMCR_BW_BIT) |
paul@43 | 1208 | #define EMC_DMCR_BW_16 (1 << EMC_DMCR_BW_BIT) |
paul@43 | 1209 | #define EMC_DMCR_CA_BIT 26 |
paul@43 | 1210 | #define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT) |
paul@43 | 1211 | #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT) |
paul@43 | 1212 | #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT) |
paul@43 | 1213 | #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT) |
paul@43 | 1214 | #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT) |
paul@43 | 1215 | #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT) |
paul@43 | 1216 | #define EMC_DMCR_RMODE (1 << 25) |
paul@43 | 1217 | #define EMC_DMCR_RFSH (1 << 24) |
paul@43 | 1218 | #define EMC_DMCR_MRSET (1 << 23) |
paul@43 | 1219 | #define EMC_DMCR_RA_BIT 20 |
paul@43 | 1220 | #define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT) |
paul@43 | 1221 | #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT) |
paul@43 | 1222 | #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT) |
paul@43 | 1223 | #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT) |
paul@43 | 1224 | #define EMC_DMCR_BA_BIT 19 |
paul@43 | 1225 | #define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT) |
paul@43 | 1226 | #define EMC_DMCR_BA_2 (0 << EMC_DMCR_BA_BIT) |
paul@43 | 1227 | #define EMC_DMCR_BA_4 (1 << EMC_DMCR_BA_BIT) |
paul@43 | 1228 | #define EMC_DMCR_PDM (1 << 18) |
paul@43 | 1229 | #define EMC_DMCR_EPIN (1 << 17) |
paul@43 | 1230 | #define EMC_DMCR_TRAS_BIT 13 |
paul@43 | 1231 | #define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT) |
paul@43 | 1232 | #define EMC_DMCR_RCD_BIT 11 |
paul@43 | 1233 | #define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT) |
paul@43 | 1234 | #define EMC_DMCR_TPC_BIT 8 |
paul@43 | 1235 | #define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT) |
paul@43 | 1236 | #define EMC_DMCR_TRWL_BIT 5 |
paul@43 | 1237 | #define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT) |
paul@43 | 1238 | #define EMC_DMCR_TRC_BIT 2 |
paul@43 | 1239 | #define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT) |
paul@43 | 1240 | #define EMC_DMCR_TCL_BIT 0 |
paul@43 | 1241 | #define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT) |
paul@43 | 1242 | #define EMC_DMCR_CASL_2 (1 << EMC_DMCR_TCL_BIT) |
paul@43 | 1243 | #define EMC_DMCR_CASL_3 (2 << EMC_DMCR_TCL_BIT) |
paul@43 | 1244 | |
paul@43 | 1245 | #define EMC_RTCSR_CMF (1 << 7) |
paul@43 | 1246 | #define EMC_RTCSR_CKS_BIT 0 |
paul@43 | 1247 | #define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT) |
paul@43 | 1248 | #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT) |
paul@43 | 1249 | #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT) |
paul@43 | 1250 | #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT) |
paul@43 | 1251 | #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT) |
paul@43 | 1252 | #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT) |
paul@43 | 1253 | #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT) |
paul@43 | 1254 | #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT) |
paul@43 | 1255 | #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT) |
paul@43 | 1256 | |
paul@43 | 1257 | #define EMC_DMAR_BASE_BIT 8 |
paul@43 | 1258 | #define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT) |
paul@43 | 1259 | #define EMC_DMAR_MASK_BIT 0 |
paul@43 | 1260 | #define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT) |
paul@43 | 1261 | |
paul@43 | 1262 | #define EMC_SDMR_BM (1 << 9) |
paul@43 | 1263 | #define EMC_SDMR_OM_BIT 7 |
paul@43 | 1264 | #define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT) |
paul@43 | 1265 | #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT) |
paul@43 | 1266 | #define EMC_SDMR_CAS_BIT 4 |
paul@43 | 1267 | #define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT) |
paul@43 | 1268 | #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT) |
paul@43 | 1269 | #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT) |
paul@43 | 1270 | #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT) |
paul@43 | 1271 | #define EMC_SDMR_BT_BIT 3 |
paul@43 | 1272 | #define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT) |
paul@43 | 1273 | #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) |
paul@43 | 1274 | #define EMC_SDMR_BT_INTR (1 << EMC_SDMR_BT_BIT) |
paul@43 | 1275 | #define EMC_SDMR_BL_BIT 0 |
paul@43 | 1276 | #define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT) |
paul@43 | 1277 | #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT) |
paul@43 | 1278 | #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT) |
paul@43 | 1279 | #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT) |
paul@43 | 1280 | #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT) |
paul@43 | 1281 | |
paul@43 | 1282 | #define EMC_SDMR_CAS2_16BIT \ |
paul@43 | 1283 | (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) |
paul@43 | 1284 | #define EMC_SDMR_CAS2_32BIT \ |
paul@43 | 1285 | (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) |
paul@43 | 1286 | #define EMC_SDMR_CAS3_16BIT \ |
paul@43 | 1287 | (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) |
paul@43 | 1288 | #define EMC_SDMR_CAS3_32BIT \ |
paul@43 | 1289 | (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) |
paul@43 | 1290 | |
paul@43 | 1291 | #define EMC_PCCR12_AMW (1 << 31) |
paul@43 | 1292 | #define EMC_PCCR12_AMAS_BIT 28 |
paul@43 | 1293 | #define EMC_PCCR12_AMAS_MASK (0x07 << EMC_PCCR12_AMAS_BIT) |
paul@43 | 1294 | #define EMC_PCCR12_AMAH_BIT 24 |
paul@43 | 1295 | #define EMC_PCCR12_AMAH_MASK (0x07 << EMC_PCCR12_AMAH_BIT) |
paul@43 | 1296 | #define EMC_PCCR12_AMPW_BIT 20 |
paul@43 | 1297 | #define EMC_PCCR12_AMPW_MASK (0x0f << EMC_PCCR12_AMPW_BIT) |
paul@43 | 1298 | #define EMC_PCCR12_AMRT_BIT 16 |
paul@43 | 1299 | #define EMC_PCCR12_AMRT_MASK (0x0f << EMC_PCCR12_AMRT_BIT) |
paul@43 | 1300 | #define EMC_PCCR12_CMW (1 << 15) |
paul@43 | 1301 | #define EMC_PCCR12_CMAS_BIT 12 |
paul@43 | 1302 | #define EMC_PCCR12_CMAS_MASK (0x07 << EMC_PCCR12_CMAS_BIT) |
paul@43 | 1303 | #define EMC_PCCR12_CMAH_BIT 8 |
paul@43 | 1304 | #define EMC_PCCR12_CMAH_MASK (0x07 << EMC_PCCR12_CMAH_BIT) |
paul@43 | 1305 | #define EMC_PCCR12_CMPW_BIT 4 |
paul@43 | 1306 | #define EMC_PCCR12_CMPW_MASK (0x0f << EMC_PCCR12_CMPW_BIT) |
paul@43 | 1307 | #define EMC_PCCR12_CMRT_BIT 0 |
paul@43 | 1308 | #define EMC_PCCR12_CMRT_MASK (0x07 << EMC_PCCR12_CMRT_BIT) |
paul@43 | 1309 | |
paul@43 | 1310 | #define EMC_PCCR34_DRS_BIT 16 |
paul@43 | 1311 | #define EMC_PCCR34_DRS_MASK (0x03 << EMC_PCCR34_DRS_BIT) |
paul@43 | 1312 | #define EMC_PCCR34_DRS_SPKR (1 << EMC_PCCR34_DRS_BIT) |
paul@43 | 1313 | #define EMC_PCCR34_DRS_IOIS16 (2 << EMC_PCCR34_DRS_BIT) |
paul@43 | 1314 | #define EMC_PCCR34_DRS_INPACK (3 << EMC_PCCR34_DRS_BIT) |
paul@43 | 1315 | #define EMC_PCCR34_IOIS16 (1 << 15) |
paul@43 | 1316 | #define EMC_PCCR34_IOW (1 << 14) |
paul@43 | 1317 | #define EMC_PCCR34_TCB_BIT 12 |
paul@43 | 1318 | #define EMC_PCCR34_TCB_MASK (0x03 << EMC_PCCR34_TCB_BIT) |
paul@43 | 1319 | #define EMC_PCCR34_IORT_BIT 8 |
paul@43 | 1320 | #define EMC_PCCR34_IORT_MASK (0x07 << EMC_PCCR34_IORT_BIT) |
paul@43 | 1321 | #define EMC_PCCR34_IOAE_BIT 6 |
paul@43 | 1322 | #define EMC_PCCR34_IOAE_MASK (0x03 << EMC_PCCR34_IOAE_BIT) |
paul@43 | 1323 | #define EMC_PCCR34_IOAE_NONE (0 << EMC_PCCR34_IOAE_BIT) |
paul@43 | 1324 | #define EMC_PCCR34_IOAE_1 (1 << EMC_PCCR34_IOAE_BIT) |
paul@43 | 1325 | #define EMC_PCCR34_IOAE_2 (2 << EMC_PCCR34_IOAE_BIT) |
paul@43 | 1326 | #define EMC_PCCR34_IOAE_5 (3 << EMC_PCCR34_IOAE_BIT) |
paul@43 | 1327 | #define EMC_PCCR34_IOAH_BIT 4 |
paul@43 | 1328 | #define EMC_PCCR34_IOAH_MASK (0x03 << EMC_PCCR34_IOAH_BIT) |
paul@43 | 1329 | #define EMC_PCCR34_IOAH_NONE (0 << EMC_PCCR34_IOAH_BIT) |
paul@43 | 1330 | #define EMC_PCCR34_IOAH_1 (1 << EMC_PCCR34_IOAH_BIT) |
paul@43 | 1331 | #define EMC_PCCR34_IOAH_2 (2 << EMC_PCCR34_IOAH_BIT) |
paul@43 | 1332 | #define EMC_PCCR34_IOAH_5 (3 << EMC_PCCR34_IOAH_BIT) |
paul@43 | 1333 | #define EMC_PCCR34_IOPW_BIT 0 |
paul@43 | 1334 | #define EMC_PCCR34_IOPW_MASK (0x0f << EMC_PCCR34_IOPW_BIT) |
paul@43 | 1335 | |
paul@43 | 1336 | |
paul@43 | 1337 | |
paul@43 | 1338 | |
paul@43 | 1339 | /************************************************************************* |
paul@43 | 1340 | * GPIO |
paul@43 | 1341 | *************************************************************************/ |
paul@43 | 1342 | #define GPIO_GPDR(n) (GPIO_BASE + (0x00 + (n)*0x30)) |
paul@43 | 1343 | #define GPIO_GPDIR(n) (GPIO_BASE + (0x04 + (n)*0x30)) |
paul@43 | 1344 | #define GPIO_GPODR(n) (GPIO_BASE + (0x08 + (n)*0x30)) |
paul@43 | 1345 | #define GPIO_GPPUR(n) (GPIO_BASE + (0x0c + (n)*0x30)) |
paul@43 | 1346 | #define GPIO_GPALR(n) (GPIO_BASE + (0x10 + (n)*0x30)) |
paul@43 | 1347 | #define GPIO_GPAUR(n) (GPIO_BASE + (0x14 + (n)*0x30)) |
paul@43 | 1348 | #define GPIO_GPIDLR(n) (GPIO_BASE + (0x18 + (n)*0x30)) |
paul@43 | 1349 | #define GPIO_GPIDUR(n) (GPIO_BASE + (0x1c + (n)*0x30)) |
paul@43 | 1350 | #define GPIO_GPIER(n) (GPIO_BASE + (0x20 + (n)*0x30)) |
paul@43 | 1351 | #define GPIO_GPIMR(n) (GPIO_BASE + (0x24 + (n)*0x30)) |
paul@43 | 1352 | #define GPIO_GPFR(n) (GPIO_BASE + (0x28 + (n)*0x30)) |
paul@43 | 1353 | |
paul@43 | 1354 | #define REG_GPIO_GPDR(n) REG32(GPIO_GPDR((n))) |
paul@43 | 1355 | #define REG_GPIO_GPDIR(n) REG32(GPIO_GPDIR((n))) |
paul@43 | 1356 | #define REG_GPIO_GPODR(n) REG32(GPIO_GPODR((n))) |
paul@43 | 1357 | #define REG_GPIO_GPPUR(n) REG32(GPIO_GPPUR((n))) |
paul@43 | 1358 | #define REG_GPIO_GPALR(n) REG32(GPIO_GPALR((n))) |
paul@43 | 1359 | #define REG_GPIO_GPAUR(n) REG32(GPIO_GPAUR((n))) |
paul@43 | 1360 | #define REG_GPIO_GPIDLR(n) REG32(GPIO_GPIDLR((n))) |
paul@43 | 1361 | #define REG_GPIO_GPIDUR(n) REG32(GPIO_GPIDUR((n))) |
paul@43 | 1362 | #define REG_GPIO_GPIER(n) REG32(GPIO_GPIER((n))) |
paul@43 | 1363 | #define REG_GPIO_GPIMR(n) REG32(GPIO_GPIMR((n))) |
paul@43 | 1364 | #define REG_GPIO_GPFR(n) REG32(GPIO_GPFR((n))) |
paul@43 | 1365 | |
paul@43 | 1366 | #define GPIO_IRQ_LOLEVEL 0 |
paul@43 | 1367 | #define GPIO_IRQ_HILEVEL 1 |
paul@43 | 1368 | #define GPIO_IRQ_FALLEDG 2 |
paul@43 | 1369 | #define GPIO_IRQ_RAISEDG 3 |
paul@43 | 1370 | |
paul@43 | 1371 | #define IRQ_GPIO_0 48 |
paul@43 | 1372 | #define NUM_GPIO 100 |
paul@43 | 1373 | |
paul@43 | 1374 | #define GPIO_GPDR0 GPIO_GPDR(0) |
paul@43 | 1375 | #define GPIO_GPDR1 GPIO_GPDR(1) |
paul@43 | 1376 | #define GPIO_GPDR2 GPIO_GPDR(2) |
paul@43 | 1377 | #define GPIO_GPDR3 GPIO_GPDR(3) |
paul@43 | 1378 | #define GPIO_GPDIR0 GPIO_GPDIR(0) |
paul@43 | 1379 | #define GPIO_GPDIR1 GPIO_GPDIR(1) |
paul@43 | 1380 | #define GPIO_GPDIR2 GPIO_GPDIR(2) |
paul@43 | 1381 | #define GPIO_GPDIR3 GPIO_GPDIR(3) |
paul@43 | 1382 | #define GPIO_GPODR0 GPIO_GPODR(0) |
paul@43 | 1383 | #define GPIO_GPODR1 GPIO_GPODR(1) |
paul@43 | 1384 | #define GPIO_GPODR2 GPIO_GPODR(2) |
paul@43 | 1385 | #define GPIO_GPODR3 GPIO_GPODR(3) |
paul@43 | 1386 | #define GPIO_GPPUR0 GPIO_GPPUR(0) |
paul@43 | 1387 | #define GPIO_GPPUR1 GPIO_GPPUR(1) |
paul@43 | 1388 | #define GPIO_GPPUR2 GPIO_GPPUR(2) |
paul@43 | 1389 | #define GPIO_GPPUR3 GPIO_GPPUR(3) |
paul@43 | 1390 | #define GPIO_GPALR0 GPIO_GPALR(0) |
paul@43 | 1391 | #define GPIO_GPALR1 GPIO_GPALR(1) |
paul@43 | 1392 | #define GPIO_GPALR2 GPIO_GPALR(2) |
paul@43 | 1393 | #define GPIO_GPALR3 GPIO_GPALR(3) |
paul@43 | 1394 | #define GPIO_GPAUR0 GPIO_GPAUR(0) |
paul@43 | 1395 | #define GPIO_GPAUR1 GPIO_GPAUR(1) |
paul@43 | 1396 | #define GPIO_GPAUR2 GPIO_GPAUR(2) |
paul@43 | 1397 | #define GPIO_GPAUR3 GPIO_GPAUR(3) |
paul@43 | 1398 | #define GPIO_GPIDLR0 GPIO_GPIDLR(0) |
paul@43 | 1399 | #define GPIO_GPIDLR1 GPIO_GPIDLR(1) |
paul@43 | 1400 | #define GPIO_GPIDLR2 GPIO_GPIDLR(2) |
paul@43 | 1401 | #define GPIO_GPIDLR3 GPIO_GPIDLR(3) |
paul@43 | 1402 | #define GPIO_GPIDUR0 GPIO_GPIDUR(0) |
paul@43 | 1403 | #define GPIO_GPIDUR1 GPIO_GPIDUR(1) |
paul@43 | 1404 | #define GPIO_GPIDUR2 GPIO_GPIDUR(2) |
paul@43 | 1405 | #define GPIO_GPIDUR3 GPIO_GPIDUR(3) |
paul@43 | 1406 | #define GPIO_GPIER0 GPIO_GPIER(0) |
paul@43 | 1407 | #define GPIO_GPIER1 GPIO_GPIER(1) |
paul@43 | 1408 | #define GPIO_GPIER2 GPIO_GPIER(2) |
paul@43 | 1409 | #define GPIO_GPIER3 GPIO_GPIER(3) |
paul@43 | 1410 | #define GPIO_GPIMR0 GPIO_GPIMR(0) |
paul@43 | 1411 | #define GPIO_GPIMR1 GPIO_GPIMR(1) |
paul@43 | 1412 | #define GPIO_GPIMR2 GPIO_GPIMR(2) |
paul@43 | 1413 | #define GPIO_GPIMR3 GPIO_GPIMR(3) |
paul@43 | 1414 | #define GPIO_GPFR0 GPIO_GPFR(0) |
paul@43 | 1415 | #define GPIO_GPFR1 GPIO_GPFR(1) |
paul@43 | 1416 | #define GPIO_GPFR2 GPIO_GPFR(2) |
paul@43 | 1417 | #define GPIO_GPFR3 GPIO_GPFR(3) |
paul@43 | 1418 | |
paul@43 | 1419 | |
paul@43 | 1420 | /************************************************************************* |
paul@43 | 1421 | * HARB |
paul@43 | 1422 | *************************************************************************/ |
paul@43 | 1423 | #define HARB_HAPOR (HARB_BASE + 0x000) |
paul@43 | 1424 | #define HARB_HMCTR (HARB_BASE + 0x010) |
paul@43 | 1425 | #define HARB_HME8H (HARB_BASE + 0x014) |
paul@43 | 1426 | #define HARB_HMCR1 (HARB_BASE + 0x018) |
paul@43 | 1427 | #define HARB_HMER2 (HARB_BASE + 0x01C) |
paul@43 | 1428 | #define HARB_HMER3 (HARB_BASE + 0x020) |
paul@43 | 1429 | #define HARB_HMLTR (HARB_BASE + 0x024) |
paul@43 | 1430 | |
paul@43 | 1431 | #define REG_HARB_HAPOR REG32(HARB_HAPOR) |
paul@43 | 1432 | #define REG_HARB_HMCTR REG32(HARB_HMCTR) |
paul@43 | 1433 | #define REG_HARB_HME8H REG32(HARB_HME8H) |
paul@43 | 1434 | #define REG_HARB_HMCR1 REG32(HARB_HMCR1) |
paul@43 | 1435 | #define REG_HARB_HMER2 REG32(HARB_HMER2) |
paul@43 | 1436 | #define REG_HARB_HMER3 REG32(HARB_HMER3) |
paul@43 | 1437 | #define REG_HARB_HMLTR REG32(HARB_HMLTR) |
paul@43 | 1438 | |
paul@43 | 1439 | /* HARB Priority Order Register (HARB_HAPOR) */ |
paul@43 | 1440 | |
paul@43 | 1441 | #define HARB_HAPOR_UCHSEL (1 << 7) |
paul@43 | 1442 | #define HARB_HAPOR_PRIO_BIT 0 |
paul@43 | 1443 | #define HARB_HAPOR_PRIO_MASK (0xf << HARB_HAPOR_PRIO_BIT) |
paul@43 | 1444 | |
paul@43 | 1445 | /* AHB Monitor Control Register (HARB_HMCTR) */ |
paul@43 | 1446 | |
paul@43 | 1447 | #define HARB_HMCTR_HET3_BIT 20 |
paul@43 | 1448 | #define HARB_HMCTR_HET3_MASK (0xf << HARB_HMCTR_HET3_BIT) |
paul@43 | 1449 | #define HARB_HMCTR_HMS3_BIT 16 |
paul@43 | 1450 | #define HARB_HMCTR_HMS3_MASK (0xf << HARB_HMCTR_HMS3_BIT) |
paul@43 | 1451 | #define HARB_HMCTR_HET2_BIT 12 |
paul@43 | 1452 | #define HARB_HMCTR_HET2_MASK (0xf << HARB_HMCTR_HET2_BIT) |
paul@43 | 1453 | #define HARB_HMCTR_HMS2_BIT 8 |
paul@43 | 1454 | #define HARB_HMCTR_HMS2_MASK (0xf << HARB_HMCTR_HMS2_BIT) |
paul@43 | 1455 | #define HARB_HMCTR_HOVF3 (1 << 7) |
paul@43 | 1456 | #define HARB_HMCTR_HOVF2 (1 << 6) |
paul@43 | 1457 | #define HARB_HMCTR_HOVF1 (1 << 5) |
paul@43 | 1458 | #define HARB_HMCTR_HRST (1 << 4) |
paul@43 | 1459 | #define HARB_HMCTR_HEE3 (1 << 2) |
paul@43 | 1460 | #define HARB_HMCTR_HEE2 (1 << 1) |
paul@43 | 1461 | #define HARB_HMCTR_HEE1 (1 << 0) |
paul@43 | 1462 | |
paul@43 | 1463 | /* AHB Monitor Event 8bits High Register (HARB_HME8H) */ |
paul@43 | 1464 | |
paul@43 | 1465 | #define HARB_HME8H_HC8H1_BIT 16 |
paul@43 | 1466 | #define HARB_HME8H_HC8H1_MASK (0xff << HARB_HME8H_HC8H1_BIT) |
paul@43 | 1467 | #define HARB_HME8H_HC8H2_BIT 8 |
paul@43 | 1468 | #define HARB_HME8H_HC8H2_MASK (0xff << HARB_HME8H_HC8H2_BIT) |
paul@43 | 1469 | #define HARB_HME8H_HC8H3_BIT 0 |
paul@43 | 1470 | #define HARB_HME8H_HC8H3_MASK (0xff << HARB_HME8H_HC8H3_BIT) |
paul@43 | 1471 | |
paul@43 | 1472 | /* AHB Monitor Latency Register (HARB_HMLTR) */ |
paul@43 | 1473 | |
paul@43 | 1474 | #define HARB_HMLTR_HLT2_BIT 16 |
paul@43 | 1475 | #define HARB_HMLTR_HLT2_MASK (0xffff << HARB_HMLTR_HLT2_BIT) |
paul@43 | 1476 | #define HARB_HMLTR_HLT3_BIT 0 |
paul@43 | 1477 | #define HARB_HMLTR_HLT3_MASK (0xffff << HARB_HMLTR_HLT3_BIT) |
paul@43 | 1478 | |
paul@43 | 1479 | |
paul@43 | 1480 | |
paul@43 | 1481 | |
paul@43 | 1482 | /************************************************************************* |
paul@43 | 1483 | * I2C |
paul@43 | 1484 | *************************************************************************/ |
paul@43 | 1485 | #define I2C_DR (I2C_BASE + 0x000) |
paul@43 | 1486 | #define I2C_CR (I2C_BASE + 0x004) |
paul@43 | 1487 | #define I2C_SR (I2C_BASE + 0x008) |
paul@43 | 1488 | #define I2C_GR (I2C_BASE + 0x00C) |
paul@43 | 1489 | |
paul@43 | 1490 | #define REG_I2C_DR REG8(I2C_DR) |
paul@43 | 1491 | #define REG_I2C_CR REG8(I2C_CR) |
paul@43 | 1492 | #define REG_I2C_SR REG8(I2C_SR) |
paul@43 | 1493 | #define REG_I2C_GR REG16(I2C_GR) |
paul@43 | 1494 | |
paul@43 | 1495 | /* I2C Control Register (I2C_CR) */ |
paul@43 | 1496 | |
paul@43 | 1497 | #define I2C_CR_IEN (1 << 4) |
paul@43 | 1498 | #define I2C_CR_STA (1 << 3) |
paul@43 | 1499 | #define I2C_CR_STO (1 << 2) |
paul@43 | 1500 | #define I2C_CR_AC (1 << 1) |
paul@43 | 1501 | #define I2C_CR_I2CE (1 << 0) |
paul@43 | 1502 | |
paul@43 | 1503 | /* I2C Status Register (I2C_SR) */ |
paul@43 | 1504 | |
paul@43 | 1505 | #define I2C_SR_STX (1 << 4) |
paul@43 | 1506 | #define I2C_SR_BUSY (1 << 3) |
paul@43 | 1507 | #define I2C_SR_TEND (1 << 2) |
paul@43 | 1508 | #define I2C_SR_DRF (1 << 1) |
paul@43 | 1509 | #define I2C_SR_ACKF (1 << 0) |
paul@43 | 1510 | |
paul@43 | 1511 | |
paul@43 | 1512 | |
paul@43 | 1513 | |
paul@43 | 1514 | /************************************************************************* |
paul@43 | 1515 | * UDC |
paul@43 | 1516 | *************************************************************************/ |
paul@43 | 1517 | #define UDC_EP0InCR (UDC_BASE + 0x00) |
paul@43 | 1518 | #define UDC_EP0InSR (UDC_BASE + 0x04) |
paul@43 | 1519 | #define UDC_EP0InBSR (UDC_BASE + 0x08) |
paul@43 | 1520 | #define UDC_EP0InMPSR (UDC_BASE + 0x0c) |
paul@43 | 1521 | #define UDC_EP0InDesR (UDC_BASE + 0x14) |
paul@43 | 1522 | #define UDC_EP1InCR (UDC_BASE + 0x20) |
paul@43 | 1523 | #define UDC_EP1InSR (UDC_BASE + 0x24) |
paul@43 | 1524 | #define UDC_EP1InBSR (UDC_BASE + 0x28) |
paul@43 | 1525 | #define UDC_EP1InMPSR (UDC_BASE + 0x2c) |
paul@43 | 1526 | #define UDC_EP1InDesR (UDC_BASE + 0x34) |
paul@43 | 1527 | #define UDC_EP2InCR (UDC_BASE + 0x40) |
paul@43 | 1528 | #define UDC_EP2InSR (UDC_BASE + 0x44) |
paul@43 | 1529 | #define UDC_EP2InBSR (UDC_BASE + 0x48) |
paul@43 | 1530 | #define UDC_EP2InMPSR (UDC_BASE + 0x4c) |
paul@43 | 1531 | #define UDC_EP2InDesR (UDC_BASE + 0x54) |
paul@43 | 1532 | #define UDC_EP3InCR (UDC_BASE + 0x60) |
paul@43 | 1533 | #define UDC_EP3InSR (UDC_BASE + 0x64) |
paul@43 | 1534 | #define UDC_EP3InBSR (UDC_BASE + 0x68) |
paul@43 | 1535 | #define UDC_EP3InMPSR (UDC_BASE + 0x6c) |
paul@43 | 1536 | #define UDC_EP3InDesR (UDC_BASE + 0x74) |
paul@43 | 1537 | #define UDC_EP4InCR (UDC_BASE + 0x80) |
paul@43 | 1538 | #define UDC_EP4InSR (UDC_BASE + 0x84) |
paul@43 | 1539 | #define UDC_EP4InBSR (UDC_BASE + 0x88) |
paul@43 | 1540 | #define UDC_EP4InMPSR (UDC_BASE + 0x8c) |
paul@43 | 1541 | #define UDC_EP4InDesR (UDC_BASE + 0x94) |
paul@43 | 1542 | |
paul@43 | 1543 | #define UDC_EP0OutCR (UDC_BASE + 0x200) |
paul@43 | 1544 | #define UDC_EP0OutSR (UDC_BASE + 0x204) |
paul@43 | 1545 | #define UDC_EP0OutPFNR (UDC_BASE + 0x208) |
paul@43 | 1546 | #define UDC_EP0OutMPSR (UDC_BASE + 0x20c) |
paul@43 | 1547 | #define UDC_EP0OutSBPR (UDC_BASE + 0x210) |
paul@43 | 1548 | #define UDC_EP0OutDesR (UDC_BASE + 0x214) |
paul@43 | 1549 | #define UDC_EP5OutCR (UDC_BASE + 0x2a0) |
paul@43 | 1550 | #define UDC_EP5OutSR (UDC_BASE + 0x2a4) |
paul@43 | 1551 | #define UDC_EP5OutPFNR (UDC_BASE + 0x2a8) |
paul@43 | 1552 | #define UDC_EP5OutMPSR (UDC_BASE + 0x2ac) |
paul@43 | 1553 | #define UDC_EP5OutDesR (UDC_BASE + 0x2b4) |
paul@43 | 1554 | #define UDC_EP6OutCR (UDC_BASE + 0x2c0) |
paul@43 | 1555 | #define UDC_EP6OutSR (UDC_BASE + 0x2c4) |
paul@43 | 1556 | #define UDC_EP6OutPFNR (UDC_BASE + 0x2c8) |
paul@43 | 1557 | #define UDC_EP6OutMPSR (UDC_BASE + 0x2cc) |
paul@43 | 1558 | #define UDC_EP6OutDesR (UDC_BASE + 0x2d4) |
paul@43 | 1559 | #define UDC_EP7OutCR (UDC_BASE + 0x2e0) |
paul@43 | 1560 | #define UDC_EP7OutSR (UDC_BASE + 0x2e4) |
paul@43 | 1561 | #define UDC_EP7OutPFNR (UDC_BASE + 0x2e8) |
paul@43 | 1562 | #define UDC_EP7OutMPSR (UDC_BASE + 0x2ec) |
paul@43 | 1563 | #define UDC_EP7OutDesR (UDC_BASE + 0x2f4) |
paul@43 | 1564 | |
paul@43 | 1565 | #define UDC_DevCFGR (UDC_BASE + 0x400) |
paul@43 | 1566 | #define UDC_DevCR (UDC_BASE + 0x404) |
paul@43 | 1567 | #define UDC_DevSR (UDC_BASE + 0x408) |
paul@43 | 1568 | #define UDC_DevIntR (UDC_BASE + 0x40c) |
paul@43 | 1569 | #define UDC_DevIntMR (UDC_BASE + 0x410) |
paul@43 | 1570 | #define UDC_EPIntR (UDC_BASE + 0x414) |
paul@43 | 1571 | #define UDC_EPIntMR (UDC_BASE + 0x418) |
paul@43 | 1572 | |
paul@43 | 1573 | #define UDC_STCMAR (UDC_BASE + 0x500) |
paul@43 | 1574 | #define UDC_EP0InfR (UDC_BASE + 0x504) |
paul@43 | 1575 | #define UDC_EP1InfR (UDC_BASE + 0x508) |
paul@43 | 1576 | #define UDC_EP2InfR (UDC_BASE + 0x50c) |
paul@43 | 1577 | #define UDC_EP3InfR (UDC_BASE + 0x510) |
paul@43 | 1578 | #define UDC_EP4InfR (UDC_BASE + 0x514) |
paul@43 | 1579 | #define UDC_EP5InfR (UDC_BASE + 0x518) |
paul@43 | 1580 | #define UDC_EP6InfR (UDC_BASE + 0x51c) |
paul@43 | 1581 | #define UDC_EP7InfR (UDC_BASE + 0x520) |
paul@43 | 1582 | |
paul@43 | 1583 | #define UDC_TXCONFIRM (UDC_BASE + 0x41C) |
paul@43 | 1584 | #define UDC_TXZLP (UDC_BASE + 0x420) |
paul@43 | 1585 | #define UDC_RXCONFIRM (UDC_BASE + 0x41C) |
paul@43 | 1586 | |
paul@43 | 1587 | #define UDC_RXFIFO (UDC_BASE + 0x800) |
paul@43 | 1588 | #define UDC_TXFIFOEP0 (UDC_BASE + 0x840) |
paul@43 | 1589 | |
paul@43 | 1590 | #define REG_UDC_EP0InCR REG32(UDC_EP0InCR) |
paul@43 | 1591 | #define REG_UDC_EP0InSR REG32(UDC_EP0InSR) |
paul@43 | 1592 | #define REG_UDC_EP0InBSR REG32(UDC_EP0InBSR) |
paul@43 | 1593 | #define REG_UDC_EP0InMPSR REG32(UDC_EP0InMPSR) |
paul@43 | 1594 | #define REG_UDC_EP0InDesR REG32(UDC_EP0InDesR) |
paul@43 | 1595 | #define REG_UDC_EP1InCR REG32(UDC_EP1InCR) |
paul@43 | 1596 | #define REG_UDC_EP1InSR REG32(UDC_EP1InSR) |
paul@43 | 1597 | #define REG_UDC_EP1InBSR REG32(UDC_EP1InBSR) |
paul@43 | 1598 | #define REG_UDC_EP1InMPSR REG32(UDC_EP1InMPSR) |
paul@43 | 1599 | #define REG_UDC_EP1InDesR REG32(UDC_EP1InDesR) |
paul@43 | 1600 | #define REG_UDC_EP2InCR REG32(UDC_EP2InCR) |
paul@43 | 1601 | #define REG_UDC_EP2InSR REG32(UDC_EP2InSR) |
paul@43 | 1602 | #define REG_UDC_EP2InBSR REG32(UDC_EP2InBSR) |
paul@43 | 1603 | #define REG_UDC_EP2InMPSR REG32(UDC_EP2InMPSR) |
paul@43 | 1604 | #define REG_UDC_EP2InDesR REG32(UDC_EP2InDesR) |
paul@43 | 1605 | #define REG_UDC_EP3InCR REG32(UDC_EP3InCR) |
paul@43 | 1606 | #define REG_UDC_EP3InSR REG32(UDC_EP3InSR) |
paul@43 | 1607 | #define REG_UDC_EP3InBSR REG32(UDC_EP3InBSR) |
paul@43 | 1608 | #define REG_UDC_EP3InMPSR REG32(UDC_EP3InMPSR) |
paul@43 | 1609 | #define REG_UDC_EP3InDesR REG32(UDC_EP3InDesR) |
paul@43 | 1610 | #define REG_UDC_EP4InCR REG32(UDC_EP4InCR) |
paul@43 | 1611 | #define REG_UDC_EP4InSR REG32(UDC_EP4InSR) |
paul@43 | 1612 | #define REG_UDC_EP4InBSR REG32(UDC_EP4InBSR) |
paul@43 | 1613 | #define REG_UDC_EP4InMPSR REG32(UDC_EP4InMPSR) |
paul@43 | 1614 | #define REG_UDC_EP4InDesR REG32(UDC_EP4InDesR) |
paul@43 | 1615 | |
paul@43 | 1616 | #define REG_UDC_EP0OutCR REG32(UDC_EP0OutCR) |
paul@43 | 1617 | #define REG_UDC_EP0OutSR REG32(UDC_EP0OutSR) |
paul@43 | 1618 | #define REG_UDC_EP0OutPFNR REG32(UDC_EP0OutPFNR) |
paul@43 | 1619 | #define REG_UDC_EP0OutMPSR REG32(UDC_EP0OutMPSR) |
paul@43 | 1620 | #define REG_UDC_EP0OutSBPR REG32(UDC_EP0OutSBPR) |
paul@43 | 1621 | #define REG_UDC_EP0OutDesR REG32(UDC_EP0OutDesR) |
paul@43 | 1622 | #define REG_UDC_EP5OutCR REG32(UDC_EP5OutCR) |
paul@43 | 1623 | #define REG_UDC_EP5OutSR REG32(UDC_EP5OutSR) |
paul@43 | 1624 | #define REG_UDC_EP5OutPFNR REG32(UDC_EP5OutPFNR) |
paul@43 | 1625 | #define REG_UDC_EP5OutMPSR REG32(UDC_EP5OutMPSR) |
paul@43 | 1626 | #define REG_UDC_EP5OutDesR REG32(UDC_EP5OutDesR) |
paul@43 | 1627 | #define REG_UDC_EP6OutCR REG32(UDC_EP6OutCR) |
paul@43 | 1628 | #define REG_UDC_EP6OutSR REG32(UDC_EP6OutSR) |
paul@43 | 1629 | #define REG_UDC_EP6OutPFNR REG32(UDC_EP6OutPFNR) |
paul@43 | 1630 | #define REG_UDC_EP6OutMPSR REG32(UDC_EP6OutMPSR) |
paul@43 | 1631 | #define REG_UDC_EP6OutDesR REG32(UDC_EP6OutDesR) |
paul@43 | 1632 | #define REG_UDC_EP7OutCR REG32(UDC_EP7OutCR) |
paul@43 | 1633 | #define REG_UDC_EP7OutSR REG32(UDC_EP7OutSR) |
paul@43 | 1634 | #define REG_UDC_EP7OutPFNR REG32(UDC_EP7OutPFNR) |
paul@43 | 1635 | #define REG_UDC_EP7OutMPSR REG32(UDC_EP7OutMPSR) |
paul@43 | 1636 | #define REG_UDC_EP7OutDesR REG32(UDC_EP7OutDesR) |
paul@43 | 1637 | |
paul@43 | 1638 | #define REG_UDC_DevCFGR REG32(UDC_DevCFGR) |
paul@43 | 1639 | #define REG_UDC_DevCR REG32(UDC_DevCR) |
paul@43 | 1640 | #define REG_UDC_DevSR REG32(UDC_DevSR) |
paul@43 | 1641 | #define REG_UDC_DevIntR REG32(UDC_DevIntR) |
paul@43 | 1642 | #define REG_UDC_DevIntMR REG32(UDC_DevIntMR) |
paul@43 | 1643 | #define REG_UDC_EPIntR REG32(UDC_EPIntR) |
paul@43 | 1644 | #define REG_UDC_EPIntMR REG32(UDC_EPIntMR) |
paul@43 | 1645 | |
paul@43 | 1646 | #define REG_UDC_STCMAR REG32(UDC_STCMAR) |
paul@43 | 1647 | #define REG_UDC_EP0InfR REG32(UDC_EP0InfR) |
paul@43 | 1648 | #define REG_UDC_EP1InfR REG32(UDC_EP1InfR) |
paul@43 | 1649 | #define REG_UDC_EP2InfR REG32(UDC_EP2InfR) |
paul@43 | 1650 | #define REG_UDC_EP3InfR REG32(UDC_EP3InfR) |
paul@43 | 1651 | #define REG_UDC_EP4InfR REG32(UDC_EP4InfR) |
paul@43 | 1652 | #define REG_UDC_EP5InfR REG32(UDC_EP5InfR) |
paul@43 | 1653 | #define REG_UDC_EP6InfR REG32(UDC_EP6InfR) |
paul@43 | 1654 | #define REG_UDC_EP7InfR REG32(UDC_EP7InfR) |
paul@43 | 1655 | |
paul@43 | 1656 | #define UDC_DevCFGR_PI (1 << 5) |
paul@43 | 1657 | #define UDC_DevCFGR_SS (1 << 4) |
paul@43 | 1658 | #define UDC_DevCFGR_SP (1 << 3) |
paul@43 | 1659 | #define UDC_DevCFGR_RW (1 << 2) |
paul@43 | 1660 | #define UDC_DevCFGR_SPD_BIT 0 |
paul@43 | 1661 | #define UDC_DevCFGR_SPD_MASK (0x03 << UDC_DevCFGR_SPD_BIT) |
paul@43 | 1662 | #define UDC_DevCFGR_SPD_HS (0 << UDC_DevCFGR_SPD_BIT) |
paul@43 | 1663 | #define UDC_DevCFGR_SPD_LS (2 << UDC_DevCFGR_SPD_BIT) |
paul@43 | 1664 | #define UDC_DevCFGR_SPD_FS (3 << UDC_DevCFGR_SPD_BIT) |
paul@43 | 1665 | |
paul@43 | 1666 | #define UDC_DevCR_DM (1 << 9) |
paul@43 | 1667 | #define UDC_DevCR_BE (1 << 5) |
paul@43 | 1668 | #define UDC_DevCR_RES (1 << 0) |
paul@43 | 1669 | |
paul@43 | 1670 | #define UDC_DevSR_ENUMSPD_BIT 13 |
paul@43 | 1671 | #define UDC_DevSR_ENUMSPD_MASK (0x03 << UDC_DevSR_ENUMSPD_BIT) |
paul@43 | 1672 | #define UDC_DevSR_ENUMSPD_HS (0 << UDC_DevSR_ENUMSPD_BIT) |
paul@43 | 1673 | #define UDC_DevSR_ENUMSPD_LS (2 << UDC_DevSR_ENUMSPD_BIT) |
paul@43 | 1674 | #define UDC_DevSR_ENUMSPD_FS (3 << UDC_DevSR_ENUMSPD_BIT) |
paul@43 | 1675 | #define UDC_DevSR_SUSP (1 << 12) |
paul@43 | 1676 | #define UDC_DevSR_ALT_BIT 8 |
paul@43 | 1677 | #define UDC_DevSR_ALT_MASK (0x0f << UDC_DevSR_ALT_BIT) |
paul@43 | 1678 | #define UDC_DevSR_INTF_BIT 4 |
paul@43 | 1679 | #define UDC_DevSR_INTF_MASK (0x0f << UDC_DevSR_INTF_BIT) |
paul@43 | 1680 | #define UDC_DevSR_CFG_BIT 0 |
paul@43 | 1681 | #define UDC_DevSR_CFG_MASK (0x0f << UDC_DevSR_CFG_BIT) |
paul@43 | 1682 | |
paul@43 | 1683 | #define UDC_DevIntR_ENUM (1 << 6) |
paul@43 | 1684 | #define UDC_DevIntR_SOF (1 << 5) |
paul@43 | 1685 | #define UDC_DevIntR_US (1 << 4) |
paul@43 | 1686 | #define UDC_DevIntR_UR (1 << 3) |
paul@43 | 1687 | #define UDC_DevIntR_SI (1 << 1) |
paul@43 | 1688 | #define UDC_DevIntR_SC (1 << 0) |
paul@43 | 1689 | |
paul@43 | 1690 | #define UDC_EPIntR_OUTEP_BIT 16 |
paul@43 | 1691 | #define UDC_EPIntR_OUTEP_MASK (0xffff << UDC_EPIntR_OUTEP_BIT) |
paul@43 | 1692 | #define UDC_EPIntR_OUTEP0 0x00010000 |
paul@43 | 1693 | #define UDC_EPIntR_OUTEP5 0x00200000 |
paul@43 | 1694 | #define UDC_EPIntR_OUTEP6 0x00400000 |
paul@43 | 1695 | #define UDC_EPIntR_OUTEP7 0x00800000 |
paul@43 | 1696 | #define UDC_EPIntR_INEP_BIT 0 |
paul@43 | 1697 | #define UDC_EPIntR_INEP_MASK (0xffff << UDC_EPIntR_INEP_BIT) |
paul@43 | 1698 | #define UDC_EPIntR_INEP0 0x00000001 |
paul@43 | 1699 | #define UDC_EPIntR_INEP1 0x00000002 |
paul@43 | 1700 | #define UDC_EPIntR_INEP2 0x00000004 |
paul@43 | 1701 | #define UDC_EPIntR_INEP3 0x00000008 |
paul@43 | 1702 | #define UDC_EPIntR_INEP4 0x00000010 |
paul@43 | 1703 | |
paul@43 | 1704 | |
paul@43 | 1705 | #define UDC_EPIntMR_OUTEP_BIT 16 |
paul@43 | 1706 | #define UDC_EPIntMR_OUTEP_MASK (0xffff << UDC_EPIntMR_OUTEP_BIT) |
paul@43 | 1707 | #define UDC_EPIntMR_INEP_BIT 0 |
paul@43 | 1708 | #define UDC_EPIntMR_INEP_MASK (0xffff << UDC_EPIntMR_INEP_BIT) |
paul@43 | 1709 | |
paul@43 | 1710 | #define UDC_EPCR_ET_BIT 4 |
paul@43 | 1711 | #define UDC_EPCR_ET_MASK (0x03 << UDC_EPCR_ET_BIT) |
paul@43 | 1712 | #define UDC_EPCR_ET_CTRL (0 << UDC_EPCR_ET_BIT) |
paul@43 | 1713 | #define UDC_EPCR_ET_ISO (1 << UDC_EPCR_ET_BIT) |
paul@43 | 1714 | #define UDC_EPCR_ET_BULK (2 << UDC_EPCR_ET_BIT) |
paul@43 | 1715 | #define UDC_EPCR_ET_INTR (3 << UDC_EPCR_ET_BIT) |
paul@43 | 1716 | #define UDC_EPCR_SN (1 << 2) |
paul@43 | 1717 | #define UDC_EPCR_F (1 << 1) |
paul@43 | 1718 | #define UDC_EPCR_S (1 << 0) |
paul@43 | 1719 | |
paul@43 | 1720 | #define UDC_EPSR_RXPKTSIZE_BIT 11 |
paul@43 | 1721 | #define UDC_EPSR_RXPKTSIZE_MASK (0x7ff << UDC_EPSR_RXPKTSIZE_BIT) |
paul@43 | 1722 | #define UDC_EPSR_IN (1 << 6) |
paul@43 | 1723 | #define UDC_EPSR_OUT_BIT 4 |
paul@43 | 1724 | #define UDC_EPSR_OUT_MASK (0x03 << UDC_EPSR_OUT_BIT) |
paul@43 | 1725 | #define UDC_EPSR_OUT_NONE (0 << UDC_EPSR_OUT_BIT) |
paul@43 | 1726 | #define UDC_EPSR_OUT_RCVDATA (1 << UDC_EPSR_OUT_BIT) |
paul@43 | 1727 | #define UDC_EPSR_OUT_RCVSETUP (2 << UDC_EPSR_OUT_BIT) |
paul@43 | 1728 | #define UDC_EPSR_PID_BIT 0 |
paul@43 | 1729 | #define UDC_EPSR_PID_MASK (0x0f << UDC_EPSR_PID_BIT) |
paul@43 | 1730 | |
paul@43 | 1731 | #define UDC_EPInfR_MPS_BIT 19 |
paul@43 | 1732 | #define UDC_EPInfR_MPS_MASK (0x3ff << UDC_EPInfR_MPS_BIT) |
paul@43 | 1733 | #define UDC_EPInfR_ALTS_BIT 15 |
paul@43 | 1734 | #define UDC_EPInfR_ALTS_MASK (0x0f << UDC_EPInfR_ALTS_BIT) |
paul@43 | 1735 | #define UDC_EPInfR_IFN_BIT 11 |
paul@43 | 1736 | #define UDC_EPInfR_IFN_MASK (0x0f << UDC_EPInfR_IFN_BIT) |
paul@43 | 1737 | #define UDC_EPInfR_CGN_BIT 7 |
paul@43 | 1738 | #define UDC_EPInfR_CGN_MASK (0x0f << UDC_EPInfR_CGN_BIT) |
paul@43 | 1739 | #define UDC_EPInfR_EPT_BIT 5 |
paul@43 | 1740 | #define UDC_EPInfR_EPT_MASK (0x03 << UDC_EPInfR_EPT_BIT) |
paul@43 | 1741 | #define UDC_EPInfR_EPT_CTRL (0 << UDC_EPInfR_EPT_BIT) |
paul@43 | 1742 | #define UDC_EPInfR_EPT_ISO (1 << UDC_EPInfR_EPT_BIT) |
paul@43 | 1743 | #define UDC_EPInfR_EPT_BULK (2 << UDC_EPInfR_EPT_BIT) |
paul@43 | 1744 | #define UDC_EPInfR_EPT_INTR (3 << UDC_EPInfR_EPT_BIT) |
paul@43 | 1745 | #define UDC_EPInfR_EPD (1 << 4) |
paul@43 | 1746 | #define UDC_EPInfR_EPD_OUT (0 << 4) |
paul@43 | 1747 | #define UDC_EPInfR_EPD_IN (1 << 4) |
paul@43 | 1748 | |
paul@43 | 1749 | #define UDC_EPInfR_EPN_BIT 0 |
paul@43 | 1750 | #define UDC_EPInfR_EPN_MASK (0xf << UDC_EPInfR_EPN_BIT) |
paul@43 | 1751 | |
paul@43 | 1752 | |
paul@43 | 1753 | |
paul@43 | 1754 | |
paul@43 | 1755 | /************************************************************************* |
paul@43 | 1756 | * DMAC |
paul@43 | 1757 | *************************************************************************/ |
paul@43 | 1758 | #define DMAC_DSAR(n) (DMAC_BASE + (0x00 + (n) * 0x20)) |
paul@43 | 1759 | #define DMAC_DDAR(n) (DMAC_BASE + (0x04 + (n) * 0x20)) |
paul@43 | 1760 | #define DMAC_DTCR(n) (DMAC_BASE + (0x08 + (n) * 0x20)) |
paul@43 | 1761 | #define DMAC_DRSR(n) (DMAC_BASE + (0x0c + (n) * 0x20)) |
paul@43 | 1762 | #define DMAC_DCCSR(n) (DMAC_BASE + (0x10 + (n) * 0x20)) |
paul@43 | 1763 | #define DMAC_DMAIPR (DMAC_BASE + 0xf8) |
paul@43 | 1764 | #define DMAC_DMACR (DMAC_BASE + 0xfc) |
paul@43 | 1765 | |
paul@43 | 1766 | #define REG_DMAC_DSAR(n) REG32(DMAC_DSAR((n))) |
paul@43 | 1767 | #define REG_DMAC_DDAR(n) REG32(DMAC_DDAR((n))) |
paul@43 | 1768 | #define REG_DMAC_DTCR(n) REG32(DMAC_DTCR((n))) |
paul@43 | 1769 | #define REG_DMAC_DRSR(n) REG32(DMAC_DRSR((n))) |
paul@43 | 1770 | #define REG_DMAC_DCCSR(n) REG32(DMAC_DCCSR((n))) |
paul@43 | 1771 | #define REG_DMAC_DMAIPR REG32(DMAC_DMAIPR) |
paul@43 | 1772 | #define REG_DMAC_DMACR REG32(DMAC_DMACR) |
paul@43 | 1773 | |
paul@43 | 1774 | #define DMAC_DRSR_RS_BIT 0 |
paul@43 | 1775 | #define DMAC_DRSR_RS_MASK (0x1f << DMAC_DRSR_RS_BIT) |
paul@43 | 1776 | #define DMAC_DRSR_RS_EXTREXTR (0 << DMAC_DRSR_RS_BIT) |
paul@43 | 1777 | #define DMAC_DRSR_RS_PCMCIAOUT (4 << DMAC_DRSR_RS_BIT) |
paul@43 | 1778 | #define DMAC_DRSR_RS_PCMCIAIN (5 << DMAC_DRSR_RS_BIT) |
paul@43 | 1779 | #define DMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT) |
paul@43 | 1780 | #define DMAC_DRSR_RS_DESOUT (10 << DMAC_DRSR_RS_BIT) |
paul@43 | 1781 | #define DMAC_DRSR_RS_DESIN (11 << DMAC_DRSR_RS_BIT) |
paul@43 | 1782 | #define DMAC_DRSR_RS_UART3OUT (14 << DMAC_DRSR_RS_BIT) |
paul@43 | 1783 | #define DMAC_DRSR_RS_UART3IN (15 << DMAC_DRSR_RS_BIT) |
paul@43 | 1784 | #define DMAC_DRSR_RS_UART2OUT (16 << DMAC_DRSR_RS_BIT) |
paul@43 | 1785 | #define DMAC_DRSR_RS_UART2IN (17 << DMAC_DRSR_RS_BIT) |
paul@43 | 1786 | #define DMAC_DRSR_RS_UART1OUT (18 << DMAC_DRSR_RS_BIT) |
paul@43 | 1787 | #define DMAC_DRSR_RS_UART1IN (19 << DMAC_DRSR_RS_BIT) |
paul@43 | 1788 | #define DMAC_DRSR_RS_UART0OUT (20 << DMAC_DRSR_RS_BIT) |
paul@43 | 1789 | #define DMAC_DRSR_RS_UART0IN (21 << DMAC_DRSR_RS_BIT) |
paul@43 | 1790 | #define DMAC_DRSR_RS_SSIOUT (22 << DMAC_DRSR_RS_BIT) |
paul@43 | 1791 | #define DMAC_DRSR_RS_SSIIN (23 << DMAC_DRSR_RS_BIT) |
paul@43 | 1792 | #define DMAC_DRSR_RS_AICOUT (24 << DMAC_DRSR_RS_BIT) |
paul@43 | 1793 | #define DMAC_DRSR_RS_AICIN (25 << DMAC_DRSR_RS_BIT) |
paul@43 | 1794 | #define DMAC_DRSR_RS_MSCOUT (26 << DMAC_DRSR_RS_BIT) |
paul@43 | 1795 | #define DMAC_DRSR_RS_MSCIN (27 << DMAC_DRSR_RS_BIT) |
paul@43 | 1796 | #define DMAC_DRSR_RS_OST2 (28 << DMAC_DRSR_RS_BIT) |
paul@43 | 1797 | |
paul@43 | 1798 | #define DMAC_DCCSR_EACKS (1 << 31) |
paul@43 | 1799 | #define DMAC_DCCSR_EACKM (1 << 30) |
paul@43 | 1800 | #define DMAC_DCCSR_ERDM_BIT 28 |
paul@43 | 1801 | #define DMAC_DCCSR_ERDM_MASK (0x03 << DMAC_DCCSR_ERDM_BIT) |
paul@43 | 1802 | #define DMAC_DCCSR_ERDM_LLEVEL (0 << DMAC_DCCSR_ERDM_BIT) |
paul@43 | 1803 | #define DMAC_DCCSR_ERDM_FEDGE (1 << DMAC_DCCSR_ERDM_BIT) |
paul@43 | 1804 | #define DMAC_DCCSR_ERDM_HLEVEL (2 << DMAC_DCCSR_ERDM_BIT) |
paul@43 | 1805 | #define DMAC_DCCSR_ERDM_REDGE (3 << DMAC_DCCSR_ERDM_BIT) |
paul@43 | 1806 | #define DMAC_DCCSR_EOPM (1 << 27) |
paul@43 | 1807 | #define DMAC_DCCSR_SAM (1 << 23) |
paul@43 | 1808 | #define DMAC_DCCSR_DAM (1 << 22) |
paul@43 | 1809 | #define DMAC_DCCSR_RDIL_BIT 16 |
paul@43 | 1810 | #define DMAC_DCCSR_RDIL_MASK (0x0f << DMAC_DCCSR_RDIL_BIT) |
paul@43 | 1811 | #define DMAC_DCCSR_RDIL_IGN (0 << DMAC_DCCSR_RDIL_BIT) |
paul@43 | 1812 | #define DMAC_DCCSR_RDIL_2 (1 << DMAC_DCCSR_RDIL_BIT) |
paul@43 | 1813 | #define DMAC_DCCSR_RDIL_4 (2 << DMAC_DCCSR_RDIL_BIT) |
paul@43 | 1814 | #define DMAC_DCCSR_RDIL_8 (3 << DMAC_DCCSR_RDIL_BIT) |
paul@43 | 1815 | #define DMAC_DCCSR_RDIL_12 (4 << DMAC_DCCSR_RDIL_BIT) |
paul@43 | 1816 | #define DMAC_DCCSR_RDIL_16 (5 << DMAC_DCCSR_RDIL_BIT) |
paul@43 | 1817 | #define DMAC_DCCSR_RDIL_20 (6 << DMAC_DCCSR_RDIL_BIT) |
paul@43 | 1818 | #define DMAC_DCCSR_RDIL_24 (7 << DMAC_DCCSR_RDIL_BIT) |
paul@43 | 1819 | #define DMAC_DCCSR_RDIL_28 (8 << DMAC_DCCSR_RDIL_BIT) |
paul@43 | 1820 | #define DMAC_DCCSR_RDIL_32 (9 << DMAC_DCCSR_RDIL_BIT) |
paul@43 | 1821 | #define DMAC_DCCSR_RDIL_48 (10 << DMAC_DCCSR_RDIL_BIT) |
paul@43 | 1822 | #define DMAC_DCCSR_RDIL_60 (11 << DMAC_DCCSR_RDIL_BIT) |
paul@43 | 1823 | #define DMAC_DCCSR_RDIL_64 (12 << DMAC_DCCSR_RDIL_BIT) |
paul@43 | 1824 | #define DMAC_DCCSR_RDIL_124 (13 << DMAC_DCCSR_RDIL_BIT) |
paul@43 | 1825 | #define DMAC_DCCSR_RDIL_128 (14 << DMAC_DCCSR_RDIL_BIT) |
paul@43 | 1826 | #define DMAC_DCCSR_RDIL_200 (15 << DMAC_DCCSR_RDIL_BIT) |
paul@43 | 1827 | #define DMAC_DCCSR_SWDH_BIT 14 |
paul@43 | 1828 | #define DMAC_DCCSR_SWDH_MASK (0x03 << DMAC_DCCSR_SWDH_BIT) |
paul@43 | 1829 | #define DMAC_DCCSR_SWDH_32 (0 << DMAC_DCCSR_SWDH_BIT) |
paul@43 | 1830 | #define DMAC_DCCSR_SWDH_8 (1 << DMAC_DCCSR_SWDH_BIT) |
paul@43 | 1831 | #define DMAC_DCCSR_SWDH_16 (2 << DMAC_DCCSR_SWDH_BIT) |
paul@43 | 1832 | #define DMAC_DCCSR_DWDH_BIT 12 |
paul@43 | 1833 | #define DMAC_DCCSR_DWDH_MASK (0x03 << DMAC_DCCSR_DWDH_BIT) |
paul@43 | 1834 | #define DMAC_DCCSR_DWDH_32 (0 << DMAC_DCCSR_DWDH_BIT) |
paul@43 | 1835 | #define DMAC_DCCSR_DWDH_8 (1 << DMAC_DCCSR_DWDH_BIT) |
paul@43 | 1836 | #define DMAC_DCCSR_DWDH_16 (2 << DMAC_DCCSR_DWDH_BIT) |
paul@43 | 1837 | #define DMAC_DCCSR_DS_BIT 8 |
paul@43 | 1838 | #define DMAC_DCCSR_DS_MASK (0x07 << DMAC_DCCSR_DS_BIT) |
paul@43 | 1839 | #define DMAC_DCCSR_DS_32b (0 << DMAC_DCCSR_DS_BIT) |
paul@43 | 1840 | #define DMAC_DCCSR_DS_8b (1 << DMAC_DCCSR_DS_BIT) |
paul@43 | 1841 | #define DMAC_DCCSR_DS_16b (2 << DMAC_DCCSR_DS_BIT) |
paul@43 | 1842 | #define DMAC_DCCSR_DS_16B (3 << DMAC_DCCSR_DS_BIT) |
paul@43 | 1843 | #define DMAC_DCCSR_DS_32B (4 << DMAC_DCCSR_DS_BIT) |
paul@43 | 1844 | #define DMAC_DCCSR_TM (1 << 7) |
paul@43 | 1845 | #define DMAC_DCCSR_AR (1 << 4) |
paul@43 | 1846 | #define DMAC_DCCSR_TC (1 << 3) |
paul@43 | 1847 | #define DMAC_DCCSR_HLT (1 << 2) |
paul@43 | 1848 | #define DMAC_DCCSR_TCIE (1 << 1) |
paul@43 | 1849 | #define DMAC_DCCSR_CHDE (1 << 0) |
paul@43 | 1850 | |
paul@43 | 1851 | #define DMAC_DMAIPR_CINT_BIT 8 |
paul@43 | 1852 | #define DMAC_DMAIPR_CINT_MASK (0xff << DMAC_DMAIPR_CINT_BIT) |
paul@43 | 1853 | |
paul@43 | 1854 | #define DMAC_DMACR_PR_BIT 8 |
paul@43 | 1855 | #define DMAC_DMACR_PR_MASK (0x03 << DMAC_DMACR_PR_BIT) |
paul@43 | 1856 | #define DMAC_DMACR_PR_01234567 (0 << DMAC_DMACR_PR_BIT) |
paul@43 | 1857 | #define DMAC_DMACR_PR_02314675 (1 << DMAC_DMACR_PR_BIT) |
paul@43 | 1858 | #define DMAC_DMACR_PR_20136457 (2 << DMAC_DMACR_PR_BIT) |
paul@43 | 1859 | #define DMAC_DMACR_PR_ROUNDROBIN (3 << DMAC_DMACR_PR_BIT) |
paul@43 | 1860 | #define DMAC_DMACR_HTR (1 << 3) |
paul@43 | 1861 | #define DMAC_DMACR_AER (1 << 2) |
paul@43 | 1862 | #define DMAC_DMACR_DME (1 << 0) |
paul@43 | 1863 | |
paul@43 | 1864 | #define IRQ_DMA_0 32 |
paul@43 | 1865 | #define NUM_DMA 6 |
paul@43 | 1866 | |
paul@43 | 1867 | |
paul@43 | 1868 | /************************************************************************* |
paul@43 | 1869 | * AIC |
paul@43 | 1870 | *************************************************************************/ |
paul@43 | 1871 | #define AIC_FR (AIC_BASE + 0x000) |
paul@43 | 1872 | #define AIC_CR (AIC_BASE + 0x004) |
paul@43 | 1873 | #define AIC_ACCR1 (AIC_BASE + 0x008) |
paul@43 | 1874 | #define AIC_ACCR2 (AIC_BASE + 0x00C) |
paul@43 | 1875 | #define AIC_I2SCR (AIC_BASE + 0x010) |
paul@43 | 1876 | #define AIC_SR (AIC_BASE + 0x014) |
paul@43 | 1877 | #define AIC_ACSR (AIC_BASE + 0x018) |
paul@43 | 1878 | #define AIC_I2SSR (AIC_BASE + 0x01C) |
paul@43 | 1879 | #define AIC_ACCAR (AIC_BASE + 0x020) |
paul@43 | 1880 | #define AIC_ACCDR (AIC_BASE + 0x024) |
paul@43 | 1881 | #define AIC_ACSAR (AIC_BASE + 0x028) |
paul@43 | 1882 | #define AIC_ACSDR (AIC_BASE + 0x02C) |
paul@43 | 1883 | #define AIC_I2SDIV (AIC_BASE + 0x030) |
paul@43 | 1884 | #define AIC_DR (AIC_BASE + 0x034) |
paul@43 | 1885 | |
paul@43 | 1886 | #define REG_AIC_FR REG32(AIC_FR) |
paul@43 | 1887 | #define REG_AIC_CR REG32(AIC_CR) |
paul@43 | 1888 | #define REG_AIC_ACCR1 REG32(AIC_ACCR1) |
paul@43 | 1889 | #define REG_AIC_ACCR2 REG32(AIC_ACCR2) |
paul@43 | 1890 | #define REG_AIC_I2SCR REG32(AIC_I2SCR) |
paul@43 | 1891 | #define REG_AIC_SR REG32(AIC_SR) |
paul@43 | 1892 | #define REG_AIC_ACSR REG32(AIC_ACSR) |
paul@43 | 1893 | #define REG_AIC_I2SSR REG32(AIC_I2SSR) |
paul@43 | 1894 | #define REG_AIC_ACCAR REG32(AIC_ACCAR) |
paul@43 | 1895 | #define REG_AIC_ACCDR REG32(AIC_ACCDR) |
paul@43 | 1896 | #define REG_AIC_ACSAR REG32(AIC_ACSAR) |
paul@43 | 1897 | #define REG_AIC_ACSDR REG32(AIC_ACSDR) |
paul@43 | 1898 | #define REG_AIC_I2SDIV REG32(AIC_I2SDIV) |
paul@43 | 1899 | #define REG_AIC_DR REG32(AIC_DR) |
paul@43 | 1900 | |
paul@43 | 1901 | /* AIC Controller Configuration Register (AIC_FR) */ |
paul@43 | 1902 | |
paul@43 | 1903 | #define AIC_FR_RFTH_BIT 12 |
paul@43 | 1904 | #define AIC_FR_RFTH_MASK (0xf << AIC_FR_RFTH_BIT) |
paul@43 | 1905 | #define AIC_FR_TFTH_BIT 8 |
paul@43 | 1906 | #define AIC_FR_TFTH_MASK (0xf << AIC_FR_TFTH_BIT) |
paul@43 | 1907 | #define AIC_FR_AUSEL (1 << 4) |
paul@43 | 1908 | #define AIC_FR_RST (1 << 3) |
paul@43 | 1909 | #define AIC_FR_BCKD (1 << 2) |
paul@43 | 1910 | #define AIC_FR_SYNCD (1 << 1) |
paul@43 | 1911 | #define AIC_FR_ENB (1 << 0) |
paul@43 | 1912 | |
paul@43 | 1913 | /* AIC Controller Common Control Register (AIC_CR) */ |
paul@43 | 1914 | |
paul@43 | 1915 | #define AIC_CR_RDMS (1 << 15) |
paul@43 | 1916 | #define AIC_CR_TDMS (1 << 14) |
paul@43 | 1917 | #define AIC_CR_FLUSH (1 << 8) |
paul@43 | 1918 | #define AIC_CR_EROR (1 << 6) |
paul@43 | 1919 | #define AIC_CR_ETUR (1 << 5) |
paul@43 | 1920 | #define AIC_CR_ERFS (1 << 4) |
paul@43 | 1921 | #define AIC_CR_ETFS (1 << 3) |
paul@43 | 1922 | #define AIC_CR_ENLBF (1 << 2) |
paul@43 | 1923 | #define AIC_CR_ERPL (1 << 1) |
paul@43 | 1924 | #define AIC_CR_EREC (1 << 0) |
paul@43 | 1925 | |
paul@43 | 1926 | /* AIC Controller AC-link Control Register 1 (AIC_ACCR1) */ |
paul@43 | 1927 | |
paul@43 | 1928 | #define AIC_ACCR1_RS_BIT 16 |
paul@43 | 1929 | #define AIC_ACCR1_RS_MASK (0x3ff << AIC_ACCR1_RS_BIT) |
paul@43 | 1930 | #define AIC_ACCR1_RS_SLOT12 (1 << 25) /* Slot 12 valid bit */ |
paul@43 | 1931 | #define AIC_ACCR1_RS_SLOT11 (1 << 24) /* Slot 11 valid bit */ |
paul@43 | 1932 | #define AIC_ACCR1_RS_SLOT10 (1 << 23) /* Slot 10 valid bit */ |
paul@43 | 1933 | #define AIC_ACCR1_RS_SLOT9 (1 << 22) /* Slot 9 valid bit */ |
paul@43 | 1934 | #define AIC_ACCR1_RS_SLOT8 (1 << 21) /* Slot 8 valid bit */ |
paul@43 | 1935 | #define AIC_ACCR1_RS_SLOT7 (1 << 20) /* Slot 7 valid bit */ |
paul@43 | 1936 | #define AIC_ACCR1_RS_SLOT6 (1 << 19) /* Slot 6 valid bit */ |
paul@43 | 1937 | #define AIC_ACCR1_RS_SLOT5 (1 << 18) /* Slot 5 valid bit */ |
paul@43 | 1938 | #define AIC_ACCR1_RS_SLOT4 (1 << 17) /* Slot 4 valid bit */ |
paul@43 | 1939 | #define AIC_ACCR1_RS_SLOT3 (1 << 16) /* Slot 3 valid bit */ |
paul@43 | 1940 | #define AIC_ACCR1_XS_BIT 0 |
paul@43 | 1941 | #define AIC_ACCR1_XS_MASK (0x3ff << AIC_ACCR1_XS_BIT) |
paul@43 | 1942 | #define AIC_ACCR1_XS_SLOT12 (1 << 9) /* Slot 12 valid bit */ |
paul@43 | 1943 | #define AIC_ACCR1_XS_SLOT11 (1 << 8) /* Slot 11 valid bit */ |
paul@43 | 1944 | #define AIC_ACCR1_XS_SLOT10 (1 << 7) /* Slot 10 valid bit */ |
paul@43 | 1945 | #define AIC_ACCR1_XS_SLOT9 (1 << 6) /* Slot 9 valid bit */ |
paul@43 | 1946 | #define AIC_ACCR1_XS_SLOT8 (1 << 5) /* Slot 8 valid bit */ |
paul@43 | 1947 | #define AIC_ACCR1_XS_SLOT7 (1 << 4) /* Slot 7 valid bit */ |
paul@43 | 1948 | #define AIC_ACCR1_XS_SLOT6 (1 << 3) /* Slot 6 valid bit */ |
paul@43 | 1949 | #define AIC_ACCR1_XS_SLOT5 (1 << 2) /* Slot 5 valid bit */ |
paul@43 | 1950 | #define AIC_ACCR1_XS_SLOT4 (1 << 1) /* Slot 4 valid bit */ |
paul@43 | 1951 | #define AIC_ACCR1_XS_SLOT3 (1 << 0) /* Slot 3 valid bit */ |
paul@43 | 1952 | |
paul@43 | 1953 | /* AIC Controller AC-link Control Register 2 (AIC_ACCR2) */ |
paul@43 | 1954 | |
paul@43 | 1955 | #define AIC_ACCR2_ERSTO (1 << 18) |
paul@43 | 1956 | #define AIC_ACCR2_ESADR (1 << 17) |
paul@43 | 1957 | #define AIC_ACCR2_ECADT (1 << 16) |
paul@43 | 1958 | #define AIC_ACCR2_OASS_BIT 8 |
paul@43 | 1959 | #define AIC_ACCR2_OASS_MASK (0x3 << AIC_ACCR2_OASS_BIT) |
paul@43 | 1960 | #define AIC_ACCR2_OASS_20BIT (0 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 20-bit */ |
paul@43 | 1961 | #define AIC_ACCR2_OASS_18BIT (1 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 18-bit */ |
paul@43 | 1962 | #define AIC_ACCR2_OASS_16BIT (2 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 16-bit */ |
paul@43 | 1963 | #define AIC_ACCR2_OASS_8BIT (3 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 8-bit */ |
paul@43 | 1964 | #define AIC_ACCR2_IASS_BIT 6 |
paul@43 | 1965 | #define AIC_ACCR2_IASS_MASK (0x3 << AIC_ACCR2_IASS_BIT) |
paul@43 | 1966 | #define AIC_ACCR2_IASS_20BIT (0 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 20-bit */ |
paul@43 | 1967 | #define AIC_ACCR2_IASS_18BIT (1 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 18-bit */ |
paul@43 | 1968 | #define AIC_ACCR2_IASS_16BIT (2 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 16-bit */ |
paul@43 | 1969 | #define AIC_ACCR2_IASS_8BIT (3 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 8-bit */ |
paul@43 | 1970 | #define AIC_ACCR2_SO (1 << 3) |
paul@43 | 1971 | #define AIC_ACCR2_SR (1 << 2) |
paul@43 | 1972 | #define AIC_ACCR2_SS (1 << 1) |
paul@43 | 1973 | #define AIC_ACCR2_SA (1 << 0) |
paul@43 | 1974 | |
paul@43 | 1975 | /* AIC Controller I2S/MSB-justified Control Register (AIC_I2SCR) */ |
paul@43 | 1976 | |
paul@43 | 1977 | #define AIC_I2SCR_STPBK (1 << 12) |
paul@43 | 1978 | #define AIC_I2SCR_WL_BIT 1 |
paul@43 | 1979 | #define AIC_I2SCR_WL_MASK (0x7 << AIC_I2SCR_WL_BIT) |
paul@43 | 1980 | #define AIC_I2SCR_WL_24BIT (0 << AIC_I2SCR_WL_BIT) /* Word Length is 24 bit */ |
paul@43 | 1981 | #define AIC_I2SCR_WL_20BIT (1 << AIC_I2SCR_WL_BIT) /* Word Length is 20 bit */ |
paul@43 | 1982 | #define AIC_I2SCR_WL_18BIT (2 << AIC_I2SCR_WL_BIT) /* Word Length is 18 bit */ |
paul@43 | 1983 | #define AIC_I2SCR_WL_16BIT (3 << AIC_I2SCR_WL_BIT) /* Word Length is 16 bit */ |
paul@43 | 1984 | #define AIC_I2SCR_WL_8BIT (4 << AIC_I2SCR_WL_BIT) /* Word Length is 8 bit */ |
paul@43 | 1985 | #define AIC_I2SCR_AMSL (1 << 0) |
paul@43 | 1986 | |
paul@43 | 1987 | /* AIC Controller FIFO Status Register (AIC_SR) */ |
paul@43 | 1988 | |
paul@43 | 1989 | #define AIC_SR_RFL_BIT 24 |
paul@43 | 1990 | #define AIC_SR_RFL_MASK (0x1f << AIC_SR_RFL_BIT) |
paul@43 | 1991 | #define AIC_SR_TFL_BIT 8 |
paul@43 | 1992 | #define AIC_SR_TFL_MASK (0x1f << AIC_SR_TFL_BIT) |
paul@43 | 1993 | #define AIC_SR_ROR (1 << 6) |
paul@43 | 1994 | #define AIC_SR_TUR (1 << 5) |
paul@43 | 1995 | #define AIC_SR_RFS (1 << 4) |
paul@43 | 1996 | #define AIC_SR_TFS (1 << 3) |
paul@43 | 1997 | |
paul@43 | 1998 | /* AIC Controller AC-link Status Register (AIC_ACSR) */ |
paul@43 | 1999 | |
paul@43 | 2000 | #define AIC_ACSR_CRDY (1 << 20) |
paul@43 | 2001 | #define AIC_ACSR_CLPM (1 << 19) |
paul@43 | 2002 | #define AIC_ACSR_RSTO (1 << 18) |
paul@43 | 2003 | #define AIC_ACSR_SADR (1 << 17) |
paul@43 | 2004 | #define AIC_ACSR_CADT (1 << 16) |
paul@43 | 2005 | |
paul@43 | 2006 | /* AIC Controller I2S/MSB-justified Status Register (AIC_I2SSR) */ |
paul@43 | 2007 | |
paul@43 | 2008 | #define AIC_I2SSR_BSY (1 << 2) |
paul@43 | 2009 | |
paul@43 | 2010 | /* AIC Controller AC97 codec Command Address Register (AIC_ACCAR) */ |
paul@43 | 2011 | |
paul@43 | 2012 | #define AIC_ACCAR_CAR_BIT 0 |
paul@43 | 2013 | #define AIC_ACCAR_CAR_MASK (0xfffff << AIC_ACCAR_CAR_BIT) |
paul@43 | 2014 | |
paul@43 | 2015 | /* AIC Controller AC97 codec Command Data Register (AIC_ACCDR) */ |
paul@43 | 2016 | |
paul@43 | 2017 | #define AIC_ACCDR_CDR_BIT 0 |
paul@43 | 2018 | #define AIC_ACCDR_CDR_MASK (0xfffff << AIC_ACCDR_CDR_BIT) |
paul@43 | 2019 | |
paul@43 | 2020 | /* AIC Controller AC97 codec Status Address Register (AIC_ACSAR) */ |
paul@43 | 2021 | |
paul@43 | 2022 | #define AIC_ACSAR_SAR_BIT 0 |
paul@43 | 2023 | #define AIC_ACSAR_SAR_MASK (0xfffff << AIC_ACSAR_SAR_BIT) |
paul@43 | 2024 | |
paul@43 | 2025 | /* AIC Controller AC97 codec Status Data Register (AIC_ACSDR) */ |
paul@43 | 2026 | |
paul@43 | 2027 | #define AIC_ACSDR_SDR_BIT 0 |
paul@43 | 2028 | #define AIC_ACSDR_SDR_MASK (0xfffff << AIC_ACSDR_SDR_BIT) |
paul@43 | 2029 | |
paul@43 | 2030 | /* AIC Controller I2S/MSB-justified Clock Divider Register (AIC_I2SDIV) */ |
paul@43 | 2031 | |
paul@43 | 2032 | #define AIC_I2SDIV_DIV_BIT 0 |
paul@43 | 2033 | #define AIC_I2SDIV_DIV_MASK (0x7f << AIC_I2SDIV_DIV_BIT) |
paul@43 | 2034 | #define AIC_I2SDIV_BITCLK_3072KHZ (0x0C << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 3.072MHz */ |
paul@43 | 2035 | #define AIC_I2SDIV_BITCLK_2836KHZ (0x0D << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 2.836MHz */ |
paul@43 | 2036 | #define AIC_I2SDIV_BITCLK_1418KHZ (0x1A << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.418MHz */ |
paul@43 | 2037 | #define AIC_I2SDIV_BITCLK_1024KHZ (0x24 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.024MHz */ |
paul@43 | 2038 | #define AIC_I2SDIV_BITCLK_7089KHZ (0x34 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 708.92KHz */ |
paul@43 | 2039 | #define AIC_I2SDIV_BITCLK_512KHZ (0x48 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 512.00KHz */ |
paul@43 | 2040 | |
paul@43 | 2041 | |
paul@43 | 2042 | |
paul@43 | 2043 | |
paul@43 | 2044 | /************************************************************************* |
paul@43 | 2045 | * LCD |
paul@43 | 2046 | *************************************************************************/ |
paul@43 | 2047 | #define LCD_CFG (LCD_BASE + 0x00) |
paul@43 | 2048 | #define LCD_VSYNC (LCD_BASE + 0x04) |
paul@43 | 2049 | #define LCD_HSYNC (LCD_BASE + 0x08) |
paul@43 | 2050 | #define LCD_VAT (LCD_BASE + 0x0c) |
paul@43 | 2051 | #define LCD_DAH (LCD_BASE + 0x10) |
paul@43 | 2052 | #define LCD_DAV (LCD_BASE + 0x14) |
paul@43 | 2053 | #define LCD_PS (LCD_BASE + 0x18) |
paul@43 | 2054 | #define LCD_CLS (LCD_BASE + 0x1c) |
paul@43 | 2055 | #define LCD_SPL (LCD_BASE + 0x20) |
paul@43 | 2056 | #define LCD_REV (LCD_BASE + 0x24) |
paul@43 | 2057 | #define LCD_CTRL (LCD_BASE + 0x30) |
paul@43 | 2058 | #define LCD_STATE (LCD_BASE + 0x34) |
paul@43 | 2059 | #define LCD_IID (LCD_BASE + 0x38) |
paul@43 | 2060 | #define LCD_DA0 (LCD_BASE + 0x40) |
paul@43 | 2061 | #define LCD_SA0 (LCD_BASE + 0x44) |
paul@43 | 2062 | #define LCD_FID0 (LCD_BASE + 0x48) |
paul@43 | 2063 | #define LCD_CMD0 (LCD_BASE + 0x4c) |
paul@43 | 2064 | #define LCD_DA1 (LCD_BASE + 0x50) |
paul@43 | 2065 | #define LCD_SA1 (LCD_BASE + 0x54) |
paul@43 | 2066 | #define LCD_FID1 (LCD_BASE + 0x58) |
paul@43 | 2067 | #define LCD_CMD1 (LCD_BASE + 0x5c) |
paul@43 | 2068 | |
paul@43 | 2069 | #define REG_LCD_CFG REG32(LCD_CFG) |
paul@43 | 2070 | #define REG_LCD_VSYNC REG32(LCD_VSYNC) |
paul@43 | 2071 | #define REG_LCD_HSYNC REG32(LCD_HSYNC) |
paul@43 | 2072 | #define REG_LCD_VAT REG32(LCD_VAT) |
paul@43 | 2073 | #define REG_LCD_DAH REG32(LCD_DAH) |
paul@43 | 2074 | #define REG_LCD_DAV REG32(LCD_DAV) |
paul@43 | 2075 | #define REG_LCD_PS REG32(LCD_PS) |
paul@43 | 2076 | #define REG_LCD_CLS REG32(LCD_CLS) |
paul@43 | 2077 | #define REG_LCD_SPL REG32(LCD_SPL) |
paul@43 | 2078 | #define REG_LCD_REV REG32(LCD_REV) |
paul@43 | 2079 | #define REG_LCD_CTRL REG32(LCD_CTRL) |
paul@43 | 2080 | #define REG_LCD_STATE REG32(LCD_STATE) |
paul@43 | 2081 | #define REG_LCD_IID REG32(LCD_IID) |
paul@43 | 2082 | #define REG_LCD_DA0 REG32(LCD_DA0) |
paul@43 | 2083 | #define REG_LCD_SA0 REG32(LCD_SA0) |
paul@43 | 2084 | #define REG_LCD_FID0 REG32(LCD_FID0) |
paul@43 | 2085 | #define REG_LCD_CMD0 REG32(LCD_CMD0) |
paul@43 | 2086 | #define REG_LCD_DA1 REG32(LCD_DA1) |
paul@43 | 2087 | #define REG_LCD_SA1 REG32(LCD_SA1) |
paul@43 | 2088 | #define REG_LCD_FID1 REG32(LCD_FID1) |
paul@43 | 2089 | #define REG_LCD_CMD1 REG32(LCD_CMD1) |
paul@43 | 2090 | |
paul@43 | 2091 | #define LCD_CFG_PDW_BIT 4 |
paul@43 | 2092 | #define LCD_CFG_PDW_MASK (0x03 << LCD_DEV_PDW_BIT) |
paul@43 | 2093 | #define LCD_CFG_PDW_1 (0 << LCD_DEV_PDW_BIT) |
paul@43 | 2094 | #define LCD_CFG_PDW_2 (1 << LCD_DEV_PDW_BIT) |
paul@43 | 2095 | #define LCD_CFG_PDW_4 (2 << LCD_DEV_PDW_BIT) |
paul@43 | 2096 | #define LCD_CFG_PDW_8 (3 << LCD_DEV_PDW_BIT) |
paul@43 | 2097 | #define LCD_CFG_MODE_BIT 0 |
paul@43 | 2098 | #define LCD_CFG_MODE_MASK (0x0f << LCD_DEV_MODE_BIT) |
paul@43 | 2099 | #define LCD_CFG_MODE_GENERIC_TFT (0 << LCD_DEV_MODE_BIT) |
paul@43 | 2100 | #define LCD_CFG_MODE_SHARP_HR (1 << LCD_DEV_MODE_BIT) |
paul@43 | 2101 | #define LCD_CFG_MODE_CASIO_TFT (2 << LCD_DEV_MODE_BIT) |
paul@43 | 2102 | #define LCD_CFG_MODE_SAMSUNG_ALPHA (3 << LCD_DEV_MODE_BIT) |
paul@43 | 2103 | #define LCD_CFG_MODE_NONINTER_CCIR656 (4 << LCD_DEV_MODE_BIT) |
paul@43 | 2104 | #define LCD_CFG_MODE_INTER_CCIR656 (5 << LCD_DEV_MODE_BIT) |
paul@43 | 2105 | #define LCD_CFG_MODE_SINGLE_CSTN (8 << LCD_DEV_MODE_BIT) |
paul@43 | 2106 | #define LCD_CFG_MODE_SINGLE_MSTN (9 << LCD_DEV_MODE_BIT) |
paul@43 | 2107 | #define LCD_CFG_MODE_DUAL_CSTN (10 << LCD_DEV_MODE_BIT) |
paul@43 | 2108 | #define LCD_CFG_MODE_DUAL_MSTN (11 << LCD_DEV_MODE_BIT) |
paul@43 | 2109 | |
paul@43 | 2110 | #define LCD_VSYNC_VPS_BIT 16 |
paul@43 | 2111 | #define LCD_VSYNC_VPS_MASK (0xffff << LCD_VSYNC_VPS_BIT) |
paul@43 | 2112 | #define LCD_VSYNC_VPE_BIT 0 |
paul@43 | 2113 | #define LCD_VSYNC_VPE_MASK (0xffff << LCD_VSYNC_VPS_BIT) |
paul@43 | 2114 | |
paul@43 | 2115 | #define LCD_HSYNC_HPS_BIT 16 |
paul@43 | 2116 | #define LCD_HSYNC_HPS_MASK (0xffff << LCD_HSYNC_HPS_BIT) |
paul@43 | 2117 | #define LCD_HSYNC_HPE_BIT 0 |
paul@43 | 2118 | #define LCD_HSYNC_HPE_MASK (0xffff << LCD_HSYNC_HPE_BIT) |
paul@43 | 2119 | |
paul@43 | 2120 | #define LCD_VAT_HT_BIT 16 |
paul@43 | 2121 | #define LCD_VAT_HT_MASK (0xffff << LCD_VAT_HT_BIT) |
paul@43 | 2122 | #define LCD_VAT_VT_BIT 0 |
paul@43 | 2123 | #define LCD_VAT_VT_MASK (0xffff << LCD_VAT_VT_BIT) |
paul@43 | 2124 | |
paul@43 | 2125 | #define LCD_DAH_HDS_BIT 16 |
paul@43 | 2126 | #define LCD_DAH_HDS_MASK (0xffff << LCD_DAH_HDS_BIT) |
paul@43 | 2127 | #define LCD_DAH_HDE_BIT 0 |
paul@43 | 2128 | #define LCD_DAH_HDE_MASK (0xffff << LCD_DAH_HDE_BIT) |
paul@43 | 2129 | |
paul@43 | 2130 | #define LCD_DAV_VDS_BIT 16 |
paul@43 | 2131 | #define LCD_DAV_VDS_MASK (0xffff << LCD_DAV_VDS_BIT) |
paul@43 | 2132 | #define LCD_DAV_VDE_BIT 0 |
paul@43 | 2133 | #define LCD_DAV_VDE_MASK (0xffff << LCD_DAV_VDE_BIT) |
paul@43 | 2134 | |
paul@43 | 2135 | #define LCD_CTRL_BST_BIT 28 |
paul@43 | 2136 | #define LCD_CTRL_BST_MASK (0x03 << LCD_CTRL_BST_BIT) |
paul@43 | 2137 | #define LCD_CTRL_BST_4 (0 << LCD_CTRL_BST_BIT) |
paul@43 | 2138 | #define LCD_CTRL_BST_8 (1 << LCD_CTRL_BST_BIT) |
paul@43 | 2139 | #define LCD_CTRL_BST_16 (2 << LCD_CTRL_BST_BIT) |
paul@43 | 2140 | #define LCD_CTRL_RGB555 (1 << 27) |
paul@43 | 2141 | #define LCD_CTRL_OFUP (1 << 26) |
paul@43 | 2142 | #define LCD_CTRL_FRC_BIT 24 |
paul@43 | 2143 | #define LCD_CTRL_FRC_MASK (0x03 << LCD_CTRL_FRC_BIT) |
paul@43 | 2144 | #define LCD_CTRL_FRC_16 (0 << LCD_CTRL_FRC_BIT) |
paul@43 | 2145 | #define LCD_CTRL_FRC_4 (1 << LCD_CTRL_FRC_BIT) |
paul@43 | 2146 | #define LCD_CTRL_FRC_2 (2 << LCD_CTRL_FRC_BIT) |
paul@43 | 2147 | #define LCD_CTRL_PDD_BIT 16 |
paul@43 | 2148 | #define LCD_CTRL_PDD_MASK (0xff << LCD_CTRL_PDD_BIT) |
paul@43 | 2149 | #define LCD_CTRL_EOFM (1 << 13) |
paul@43 | 2150 | #define LCD_CTRL_SOFM (1 << 12) |
paul@43 | 2151 | #define LCD_CTRL_OFUM (1 << 11) |
paul@43 | 2152 | #define LCD_CTRL_IFUM0 (1 << 10) |
paul@43 | 2153 | #define LCD_CTRL_IFUM1 (1 << 9) |
paul@43 | 2154 | #define LCD_CTRL_LDDM (1 << 8) |
paul@43 | 2155 | #define LCD_CTRL_QDM (1 << 7) |
paul@43 | 2156 | #define LCD_CTRL_BEDN (1 << 6) |
paul@43 | 2157 | #define LCD_CTRL_PEDN (1 << 5) |
paul@43 | 2158 | #define LCD_CTRL_DIS (1 << 4) |
paul@43 | 2159 | #define LCD_CTRL_ENA (1 << 3) |
paul@43 | 2160 | #define LCD_CTRL_BPP_BIT 0 |
paul@43 | 2161 | #define LCD_CTRL_BPP_MASK (0x07 << LCD_CTRL_BPP_BIT) |
paul@43 | 2162 | #define LCD_CTRL_BPP_1 (0 << LCD_CTRL_BPP_BIT) |
paul@43 | 2163 | #define LCD_CTRL_BPP_2 (1 << LCD_CTRL_BPP_BIT) |
paul@43 | 2164 | #define LCD_CTRL_BPP_4 (2 << LCD_CTRL_BPP_BIT) |
paul@43 | 2165 | #define LCD_CTRL_BPP_8 (3 << LCD_CTRL_BPP_BIT) |
paul@43 | 2166 | #define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT) |
paul@43 | 2167 | |
paul@43 | 2168 | #define LCD_STATE_QD (1 << 7) |
paul@43 | 2169 | #define LCD_STATE_EOF (1 << 5) |
paul@43 | 2170 | #define LCD_STATE_SOF (1 << 4) |
paul@43 | 2171 | #define LCD_STATE_OFU (1 << 3) |
paul@43 | 2172 | #define LCD_STATE_IFU0 (1 << 2) |
paul@43 | 2173 | #define LCD_STATE_IFU1 (1 << 1) |
paul@43 | 2174 | #define LCD_STATE_LDD (1 << 0) |
paul@43 | 2175 | |
paul@43 | 2176 | #define LCD_CMD_SOFINT (1 << 31) |
paul@43 | 2177 | #define LCD_CMD_EOFINT (1 << 30) |
paul@43 | 2178 | #define LCD_CMD_PAL (1 << 28) |
paul@43 | 2179 | #define LCD_CMD_LEN_BIT 0 |
paul@43 | 2180 | #define LCD_CMD_LEN_MASK (0xffffff << LCD_CMD_LEN_BIT) |
paul@43 | 2181 | |
paul@43 | 2182 | |
paul@43 | 2183 | |
paul@43 | 2184 | |
paul@43 | 2185 | /************************************************************************* |
paul@43 | 2186 | * DES |
paul@43 | 2187 | *************************************************************************/ |
paul@43 | 2188 | #define DES_CR1 (DES_BASE + 0x000) |
paul@43 | 2189 | #define DES_CR2 (DES_BASE + 0x004) |
paul@43 | 2190 | #define DES_SR (DES_BASE + 0x008) |
paul@43 | 2191 | #define DES_K1L (DES_BASE + 0x010) |
paul@43 | 2192 | #define DES_K1R (DES_BASE + 0x014) |
paul@43 | 2193 | #define DES_K2L (DES_BASE + 0x018) |
paul@43 | 2194 | #define DES_K2R (DES_BASE + 0x01C) |
paul@43 | 2195 | #define DES_K3L (DES_BASE + 0x020) |
paul@43 | 2196 | #define DES_K3R (DES_BASE + 0x024) |
paul@43 | 2197 | #define DES_IVL (DES_BASE + 0x028) |
paul@43 | 2198 | #define DES_IVR (DES_BASE + 0x02C) |
paul@43 | 2199 | #define DES_DIN (DES_BASE + 0x030) |
paul@43 | 2200 | #define DES_DOUT (DES_BASE + 0x034) |
paul@43 | 2201 | |
paul@43 | 2202 | #define REG_DES_CR1 REG32(DES_CR1) |
paul@43 | 2203 | #define REG_DES_CR2 REG32(DES_CR2) |
paul@43 | 2204 | #define REG_DES_SR REG32(DES_SR) |
paul@43 | 2205 | #define REG_DES_K1L REG32(DES_K1L) |
paul@43 | 2206 | #define REG_DES_K1R REG32(DES_K1R) |
paul@43 | 2207 | #define REG_DES_K2L REG32(DES_K2L) |
paul@43 | 2208 | #define REG_DES_K2R REG32(DES_K2R) |
paul@43 | 2209 | #define REG_DES_K3L REG32(DES_K3L) |
paul@43 | 2210 | #define REG_DES_K3R REG32(DES_K3R) |
paul@43 | 2211 | #define REG_DES_IVL REG32(DES_IVL) |
paul@43 | 2212 | #define REG_DES_IVR REG32(DES_IVR) |
paul@43 | 2213 | #define REG_DES_DIN REG32(DES_DIN) |
paul@43 | 2214 | #define REG_DES_DOUT REG32(DES_DOUT) |
paul@43 | 2215 | |
paul@43 | 2216 | /* DES Control Register 1 (DES_CR1) */ |
paul@43 | 2217 | |
paul@43 | 2218 | #define DES_CR1_EN (1 << 0) |
paul@43 | 2219 | |
paul@43 | 2220 | /* DES Control Register 2 (DES_CR2) */ |
paul@43 | 2221 | |
paul@43 | 2222 | #define DES_CR2_ENDEC (1 << 3) |
paul@43 | 2223 | #define DES_CR2_MODE (1 << 2) |
paul@43 | 2224 | #define DES_CR2_ALG (1 << 1) |
paul@43 | 2225 | #define DES_CR2_DMAE (1 << 0) |
paul@43 | 2226 | |
paul@43 | 2227 | /* DES State Register (DES_SR) */ |
paul@43 | 2228 | |
paul@43 | 2229 | #define DES_SR_IN_FULL (1 << 5) |
paul@43 | 2230 | #define DES_SR_IN_LHF (1 << 4) |
paul@43 | 2231 | #define DES_SR_IN_EMPTY (1 << 3) |
paul@43 | 2232 | #define DES_SR_OUT_FULL (1 << 2) |
paul@43 | 2233 | #define DES_SR_OUT_GHF (1 << 1) |
paul@43 | 2234 | #define DES_SR_OUT_EMPTY (1 << 0) |
paul@43 | 2235 | |
paul@43 | 2236 | |
paul@43 | 2237 | |
paul@43 | 2238 | |
paul@43 | 2239 | /************************************************************************* |
paul@43 | 2240 | * CPM |
paul@43 | 2241 | *************************************************************************/ |
paul@43 | 2242 | #define CPM_CFCR (CPM_BASE+0x00) |
paul@43 | 2243 | #define CPM_PLCR1 (CPM_BASE+0x10) |
paul@43 | 2244 | #define CPM_OCR (CPM_BASE+0x1c) |
paul@43 | 2245 | #define CPM_CFCR2 (CPM_BASE+0x60) |
paul@43 | 2246 | #define CPM_LPCR (CPM_BASE+0x04) |
paul@43 | 2247 | #define CPM_RSTR (CPM_BASE+0x08) |
paul@43 | 2248 | #define CPM_MSCR (CPM_BASE+0x20) |
paul@43 | 2249 | #define CPM_SCR (CPM_BASE+0x24) |
paul@43 | 2250 | #define CPM_WRER (CPM_BASE+0x28) |
paul@43 | 2251 | #define CPM_WFER (CPM_BASE+0x2c) |
paul@43 | 2252 | #define CPM_WER (CPM_BASE+0x30) |
paul@43 | 2253 | #define CPM_WSR (CPM_BASE+0x34) |
paul@43 | 2254 | #define CPM_GSR0 (CPM_BASE+0x38) |
paul@43 | 2255 | #define CPM_GSR1 (CPM_BASE+0x3c) |
paul@43 | 2256 | #define CPM_GSR2 (CPM_BASE+0x40) |
paul@43 | 2257 | #define CPM_SPR (CPM_BASE+0x44) |
paul@43 | 2258 | #define CPM_GSR3 (CPM_BASE+0x48) |
paul@43 | 2259 | |
paul@43 | 2260 | #define REG_CPM_CFCR REG32(CPM_CFCR) |
paul@43 | 2261 | #define REG_CPM_PLCR1 REG32(CPM_PLCR1) |
paul@43 | 2262 | #define REG_CPM_OCR REG32(CPM_OCR) |
paul@43 | 2263 | #define REG_CPM_CFCR2 REG32(CPM_CFCR2) |
paul@43 | 2264 | #define REG_CPM_LPCR REG32(CPM_LPCR) |
paul@43 | 2265 | #define REG_CPM_RSTR REG32(CPM_RSTR) |
paul@43 | 2266 | #define REG_CPM_MSCR REG32(CPM_MSCR) |
paul@43 | 2267 | #define REG_CPM_SCR REG32(CPM_SCR) |
paul@43 | 2268 | #define REG_CPM_WRER REG32(CPM_WRER) |
paul@43 | 2269 | #define REG_CPM_WFER REG32(CPM_WFER) |
paul@43 | 2270 | #define REG_CPM_WER REG32(CPM_WER) |
paul@43 | 2271 | #define REG_CPM_WSR REG32(CPM_WSR) |
paul@43 | 2272 | #define REG_CPM_GSR0 REG32(CPM_GSR0) |
paul@43 | 2273 | #define REG_CPM_GSR1 REG32(CPM_GSR1) |
paul@43 | 2274 | #define REG_CPM_GSR2 REG32(CPM_GSR2) |
paul@43 | 2275 | #define REG_CPM_SPR REG32(CPM_SPR) |
paul@43 | 2276 | #define REG_CPM_GSR3 REG32(CPM_GSR3) |
paul@43 | 2277 | |
paul@43 | 2278 | #define CPM_CFCR_SSI (1 << 31) |
paul@43 | 2279 | #define CPM_CFCR_LCD (1 << 30) |
paul@43 | 2280 | #define CPM_CFCR_I2S (1 << 29) |
paul@43 | 2281 | #define CPM_CFCR_UCS (1 << 28) |
paul@43 | 2282 | #define CPM_CFCR_UFR_BIT 25 |
paul@43 | 2283 | #define CPM_CFCR_UFR_MASK (0x07 << CPM_CFCR_UFR_BIT) |
paul@43 | 2284 | #define CPM_CFCR_MSC (1 << 24) |
paul@43 | 2285 | #define CPM_CFCR_CKOEN2 (1 << 23) |
paul@43 | 2286 | #define CPM_CFCR_CKOEN1 (1 << 22) |
paul@43 | 2287 | #define CPM_CFCR_UPE (1 << 20) |
paul@43 | 2288 | #define CPM_CFCR_MFR_BIT 16 |
paul@43 | 2289 | #define CPM_CFCR_MFR_MASK (0x0f << CPM_CFCR_MFR_BIT) |
paul@43 | 2290 | #define CFCR_MDIV_1 (0 << CPM_CFCR_MFR_BIT) |
paul@43 | 2291 | #define CFCR_MDIV_2 (1 << CPM_CFCR_MFR_BIT) |
paul@43 | 2292 | #define CFCR_MDIV_3 (2 << CPM_CFCR_MFR_BIT) |
paul@43 | 2293 | #define CFCR_MDIV_4 (3 << CPM_CFCR_MFR_BIT) |
paul@43 | 2294 | #define CFCR_MDIV_6 (4 << CPM_CFCR_MFR_BIT) |
paul@43 | 2295 | #define CFCR_MDIV_8 (5 << CPM_CFCR_MFR_BIT) |
paul@43 | 2296 | #define CFCR_MDIV_12 (6 << CPM_CFCR_MFR_BIT) |
paul@43 | 2297 | #define CFCR_MDIV_16 (7 << CPM_CFCR_MFR_BIT) |
paul@43 | 2298 | #define CFCR_MDIV_24 (8 << CPM_CFCR_MFR_BIT) |
paul@43 | 2299 | #define CFCR_MDIV_32 (9 << CPM_CFCR_MFR_BIT) |
paul@43 | 2300 | #define CPM_CFCR_LFR_BIT 12 |
paul@43 | 2301 | #define CPM_CFCR_LFR_MASK (0x0f << CPM_CFCR_LFR_BIT) |
paul@43 | 2302 | #define CPM_CFCR_PFR_BIT 8 |
paul@43 | 2303 | #define CPM_CFCR_PFR_MASK (0x0f << CPM_CFCR_PFR_BIT) |
paul@43 | 2304 | #define CFCR_PDIV_1 (0 << CPM_CFCR_PFR_BIT) |
paul@43 | 2305 | #define CFCR_PDIV_2 (1 << CPM_CFCR_PFR_BIT) |
paul@43 | 2306 | #define CFCR_PDIV_3 (2 << CPM_CFCR_PFR_BIT) |
paul@43 | 2307 | #define CFCR_PDIV_4 (3 << CPM_CFCR_PFR_BIT) |
paul@43 | 2308 | #define CFCR_PDIV_6 (4 << CPM_CFCR_PFR_BIT) |
paul@43 | 2309 | #define CFCR_PDIV_8 (5 << CPM_CFCR_PFR_BIT) |
paul@43 | 2310 | #define CFCR_PDIV_12 (6 << CPM_CFCR_PFR_BIT) |
paul@43 | 2311 | #define CFCR_PDIV_16 (7 << CPM_CFCR_PFR_BIT) |
paul@43 | 2312 | #define CFCR_PDIV_24 (8 << CPM_CFCR_PFR_BIT) |
paul@43 | 2313 | #define CFCR_PDIV_32 (9 << CPM_CFCR_PFR_BIT) |
paul@43 | 2314 | #define CPM_CFCR_SFR_BIT 4 |
paul@43 | 2315 | #define CPM_CFCR_SFR_MASK (0x0f << CPM_CFCR_SFR_BIT) |
paul@43 | 2316 | #define CFCR_SDIV_1 (0 << CPM_CFCR_SFR_BIT) |
paul@43 | 2317 | #define CFCR_SDIV_2 (1 << CPM_CFCR_SFR_BIT) |
paul@43 | 2318 | #define CFCR_SDIV_3 (2 << CPM_CFCR_SFR_BIT) |
paul@43 | 2319 | #define CFCR_SDIV_4 (3 << CPM_CFCR_SFR_BIT) |
paul@43 | 2320 | #define CFCR_SDIV_6 (4 << CPM_CFCR_SFR_BIT) |
paul@43 | 2321 | #define CFCR_SDIV_8 (5 << CPM_CFCR_SFR_BIT) |
paul@43 | 2322 | #define CFCR_SDIV_12 (6 << CPM_CFCR_SFR_BIT) |
paul@43 | 2323 | #define CFCR_SDIV_16 (7 << CPM_CFCR_SFR_BIT) |
paul@43 | 2324 | #define CFCR_SDIV_24 (8 << CPM_CFCR_SFR_BIT) |
paul@43 | 2325 | #define CFCR_SDIV_32 (9 << CPM_CFCR_SFR_BIT) |
paul@43 | 2326 | #define CPM_CFCR_IFR_BIT 0 |
paul@43 | 2327 | #define CPM_CFCR_IFR_MASK (0x0f << CPM_CFCR_IFR_BIT) |
paul@43 | 2328 | #define CFCR_IDIV_1 (0 << CPM_CFCR_IFR_BIT) |
paul@43 | 2329 | #define CFCR_IDIV_2 (1 << CPM_CFCR_IFR_BIT) |
paul@43 | 2330 | #define CFCR_IDIV_3 (2 << CPM_CFCR_IFR_BIT) |
paul@43 | 2331 | #define CFCR_IDIV_4 (3 << CPM_CFCR_IFR_BIT) |
paul@43 | 2332 | #define CFCR_IDIV_6 (4 << CPM_CFCR_IFR_BIT) |
paul@43 | 2333 | #define CFCR_IDIV_8 (5 << CPM_CFCR_IFR_BIT) |
paul@43 | 2334 | #define CFCR_IDIV_12 (6 << CPM_CFCR_IFR_BIT) |
paul@43 | 2335 | #define CFCR_IDIV_16 (7 << CPM_CFCR_IFR_BIT) |
paul@43 | 2336 | #define CFCR_IDIV_24 (8 << CPM_CFCR_IFR_BIT) |
paul@43 | 2337 | #define CFCR_IDIV_32 (9 << CPM_CFCR_IFR_BIT) |
paul@43 | 2338 | |
paul@43 | 2339 | #define CPM_PLCR1_PLL1FD_BIT 23 |
paul@43 | 2340 | #define CPM_PLCR1_PLL1FD_MASK (0x1ff << CPM_PLCR1_PLL1FD_BIT) |
paul@43 | 2341 | #define CPM_PLCR1_PLL1RD_BIT 18 |
paul@43 | 2342 | #define CPM_PLCR1_PLL1RD_MASK (0x1f << CPM_PLCR1_PLL1RD_BIT) |
paul@43 | 2343 | #define CPM_PLCR1_PLL1OD_BIT 16 |
paul@43 | 2344 | #define CPM_PLCR1_PLL1OD_MASK (0x03 << CPM_PLCR1_PLL1OD_BIT) |
paul@43 | 2345 | #define CPM_PLCR1_PLL1S (1 << 10) |
paul@43 | 2346 | #define CPM_PLCR1_PLL1BP (1 << 9) |
paul@43 | 2347 | #define CPM_PLCR1_PLL1EN (1 << 8) |
paul@43 | 2348 | #define CPM_PLCR1_PLL1ST_BIT 0 |
paul@43 | 2349 | #define CPM_PLCR1_PLL1ST_MASK (0xff << CPM_PLCR1_PLL1ST_BIT) |
paul@43 | 2350 | |
paul@43 | 2351 | #define CPM_OCR_O1ST_BIT 16 |
paul@43 | 2352 | #define CPM_OCR_O1ST_MASK (0xff << CPM_OCR_O1ST_BIT) |
paul@43 | 2353 | #define CPM_OCR_EXT_RTC_CLK (1<<8) |
paul@43 | 2354 | #define CPM_OCR_SUSPEND_PHY1 (1<<7) |
paul@43 | 2355 | #define CPM_OCR_SUSPEND_PHY0 (1<<6) |
paul@43 | 2356 | |
paul@43 | 2357 | #define CPM_CFCR2_PXFR_BIT 0 |
paul@43 | 2358 | #define CPM_CFCR2_PXFR_MASK (0x1ff << CPM_CFCR2_PXFR_BIT) |
paul@43 | 2359 | |
paul@43 | 2360 | #define CPM_LPCR_DUTY_BIT 3 |
paul@43 | 2361 | #define CPM_LPCR_DUTY_MASK (0x1f << CPM_LPCR_DUTY_BIT) |
paul@43 | 2362 | #define CPM_LPCR_DOZE (1 << 2) |
paul@43 | 2363 | #define CPM_LPCR_LPM_BIT 0 |
paul@43 | 2364 | #define CPM_LPCR_LPM_MASK (0x03 << CPM_LPCR_LPM_BIT) |
paul@43 | 2365 | #define CPM_LPCR_LPM_IDLE (0 << CPM_LPCR_LPM_BIT) |
paul@43 | 2366 | #define CPM_LPCR_LPM_SLEEP (1 << CPM_LPCR_LPM_BIT) |
paul@43 | 2367 | #define CPM_LPCR_LPM_HIBERNATE (2 << CPM_LPCR_LPM_BIT) |
paul@43 | 2368 | |
paul@43 | 2369 | #define CPM_RSTR_SR (1 << 2) |
paul@43 | 2370 | #define CPM_RSTR_WR (1 << 1) |
paul@43 | 2371 | #define CPM_RSTR_HR (1 << 0) |
paul@43 | 2372 | |
paul@43 | 2373 | #define CPM_MSCR_MSTP_BIT 0 |
paul@43 | 2374 | #define CPM_MSCR_MSTP_MASK (0x1ffffff << CPM_MSCR_MSTP_BIT) |
paul@43 | 2375 | #define CPM_MSCR_MSTP_UART0 0 |
paul@43 | 2376 | #define CPM_MSCR_MSTP_UART1 1 |
paul@43 | 2377 | #define CPM_MSCR_MSTP_UART2 2 |
paul@43 | 2378 | #define CPM_MSCR_MSTP_OST 3 |
paul@43 | 2379 | #define CPM_MSCR_MSTP_DMAC 5 |
paul@43 | 2380 | #define CPM_MSCR_MSTP_UHC 6 |
paul@43 | 2381 | #define CPM_MSCR_MSTP_LCD 7 |
paul@43 | 2382 | #define CPM_MSCR_MSTP_I2C 8 |
paul@43 | 2383 | #define CPM_MSCR_MSTP_AICPCLK 9 |
paul@43 | 2384 | #define CPM_MSCR_MSTP_PWM0 10 |
paul@43 | 2385 | #define CPM_MSCR_MSTP_PWM1 11 |
paul@43 | 2386 | #define CPM_MSCR_MSTP_SSI 12 |
paul@43 | 2387 | #define CPM_MSCR_MSTP_MSC 13 |
paul@43 | 2388 | #define CPM_MSCR_MSTP_SCC 14 |
paul@43 | 2389 | #define CPM_MSCR_MSTP_AICBCLK 18 |
paul@43 | 2390 | #define CPM_MSCR_MSTP_UART3 20 |
paul@43 | 2391 | #define CPM_MSCR_MSTP_ETH 21 |
paul@43 | 2392 | #define CPM_MSCR_MSTP_KBC 22 |
paul@43 | 2393 | #define CPM_MSCR_MSTP_CIM 23 |
paul@43 | 2394 | #define CPM_MSCR_MSTP_UDC 24 |
paul@43 | 2395 | #define CPM_MSCR_MSTP_UPRT 25 |
paul@43 | 2396 | |
paul@43 | 2397 | #define CPM_SCR_O1SE (1 << 4) |
paul@43 | 2398 | #define CPM_SCR_HGP (1 << 3) |
paul@43 | 2399 | #define CPM_SCR_HZP (1 << 2) |
paul@43 | 2400 | #define CPM_SCR_HZM (1 << 1) |
paul@43 | 2401 | |
paul@43 | 2402 | #define CPM_WRER_RE_BIT 0 |
paul@43 | 2403 | #define CPM_WRER_RE_MASK (0xffff << CPM_WRER_RE_BIT) |
paul@43 | 2404 | |
paul@43 | 2405 | #define CPM_WFER_FE_BIT 0 |
paul@43 | 2406 | #define CPM_WFER_FE_MASK (0xffff << CPM_WFER_FE_BIT) |
paul@43 | 2407 | |
paul@43 | 2408 | #define CPM_WER_WERTC (1 << 31) |
paul@43 | 2409 | #define CPM_WER_WEETH (1 << 30) |
paul@43 | 2410 | #define CPM_WER_WE_BIT 0 |
paul@43 | 2411 | #define CPM_WER_WE_MASK (0xffff << CPM_WER_WE_BIT) |
paul@43 | 2412 | |
paul@43 | 2413 | #define CPM_WSR_WSRTC (1 << 31) |
paul@43 | 2414 | #define CPM_WSR_WSETH (1 << 30) |
paul@43 | 2415 | #define CPM_WSR_WS_BIT 0 |
paul@43 | 2416 | #define CPM_WSR_WS_MASK (0xffff << CPM_WSR_WS_BIT) |
paul@43 | 2417 | |
paul@43 | 2418 | |
paul@43 | 2419 | |
paul@43 | 2420 | |
paul@43 | 2421 | /************************************************************************* |
paul@43 | 2422 | * SSI |
paul@43 | 2423 | *************************************************************************/ |
paul@43 | 2424 | #define SSI_DR (SSI_BASE + 0x000) |
paul@43 | 2425 | #define SSI_CR0 (SSI_BASE + 0x004) |
paul@43 | 2426 | #define SSI_CR1 (SSI_BASE + 0x008) |
paul@43 | 2427 | #define SSI_SR (SSI_BASE + 0x00C) |
paul@43 | 2428 | #define SSI_ITR (SSI_BASE + 0x010) |
paul@43 | 2429 | #define SSI_ICR (SSI_BASE + 0x014) |
paul@43 | 2430 | #define SSI_GR (SSI_BASE + 0x018) |
paul@43 | 2431 | |
paul@43 | 2432 | #define REG_SSI_DR REG32(SSI_DR) |
paul@43 | 2433 | #define REG_SSI_CR0 REG16(SSI_CR0) |
paul@43 | 2434 | #define REG_SSI_CR1 REG32(SSI_CR1) |
paul@43 | 2435 | #define REG_SSI_SR REG32(SSI_SR) |
paul@43 | 2436 | #define REG_SSI_ITR REG16(SSI_ITR) |
paul@43 | 2437 | #define REG_SSI_ICR REG8(SSI_ICR) |
paul@43 | 2438 | #define REG_SSI_GR REG16(SSI_GR) |
paul@43 | 2439 | |
paul@43 | 2440 | /* SSI Data Register (SSI_DR) */ |
paul@43 | 2441 | |
paul@43 | 2442 | #define SSI_DR_GPC_BIT 0 |
paul@43 | 2443 | #define SSI_DR_GPC_MASK (0x1ff << SSI_DR_GPC_BIT) |
paul@43 | 2444 | |
paul@43 | 2445 | /* SSI Control Register 0 (SSI_CR0) */ |
paul@43 | 2446 | |
paul@43 | 2447 | #define SSI_CR0_SSIE (1 << 15) |
paul@43 | 2448 | #define SSI_CR0_TIE (1 << 14) |
paul@43 | 2449 | #define SSI_CR0_RIE (1 << 13) |
paul@43 | 2450 | #define SSI_CR0_TEIE (1 << 12) |
paul@43 | 2451 | #define SSI_CR0_REIE (1 << 11) |
paul@43 | 2452 | #define SSI_CR0_LOOP (1 << 10) |
paul@43 | 2453 | #define SSI_CR0_RFINE (1 << 9) |
paul@43 | 2454 | #define SSI_CR0_RFINC (1 << 8) |
paul@43 | 2455 | #define SSI_CR0_FSEL (1 << 6) |
paul@43 | 2456 | #define SSI_CR0_TFLUSH (1 << 2) |
paul@43 | 2457 | #define SSI_CR0_RFLUSH (1 << 1) |
paul@43 | 2458 | #define SSI_CR0_DISREV (1 << 0) |
paul@43 | 2459 | |
paul@43 | 2460 | /* SSI Control Register 1 (SSI_CR1) */ |
paul@43 | 2461 | |
paul@43 | 2462 | #define SSI_CR1_FRMHL_BIT 30 |
paul@43 | 2463 | #define SSI_CR1_FRMHL_MASK (0x3 << SSI_CR1_FRMHL_BIT) |
paul@43 | 2464 | #define SSI_CR1_FRMHL_CELOW_CE2LOW (0 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is low valid */ |
paul@43 | 2465 | #define SSI_CR1_FRMHL_CEHIGH_CE2LOW (1 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is low valid */ |
paul@43 | 2466 | #define SSI_CR1_FRMHL_CELOW_CE2HIGH (2 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is high valid */ |
paul@43 | 2467 | #define SSI_CR1_FRMHL_CEHIGH_CE2HIGH (3 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is high valid */ |
paul@43 | 2468 | #define SSI_CR1_TFVCK_BIT 28 |
paul@43 | 2469 | #define SSI_CR1_TFVCK_MASK (0x3 << SSI_CR1_TFVCK_BIT) |
paul@43 | 2470 | #define SSI_CR1_TFVCK_0 (0 << SSI_CR1_TFVCK_BIT) |
paul@43 | 2471 | #define SSI_CR1_TFVCK_1 (1 << SSI_CR1_TFVCK_BIT) |
paul@43 | 2472 | #define SSI_CR1_TFVCK_2 (2 << SSI_CR1_TFVCK_BIT) |
paul@43 | 2473 | #define SSI_CR1_TFVCK_3 (3 << SSI_CR1_TFVCK_BIT) |
paul@43 | 2474 | #define SSI_CR1_TCKFI_BIT 26 |
paul@43 | 2475 | #define SSI_CR1_TCKFI_MASK (0x3 << SSI_CR1_TCKFI_BIT) |
paul@43 | 2476 | #define SSI_CR1_TCKFI_0 (0 << SSI_CR1_TCKFI_BIT) |
paul@43 | 2477 | #define SSI_CR1_TCKFI_1 (1 << SSI_CR1_TCKFI_BIT) |
paul@43 | 2478 | #define SSI_CR1_TCKFI_2 (2 << SSI_CR1_TCKFI_BIT) |
paul@43 | 2479 | #define SSI_CR1_TCKFI_3 (3 << SSI_CR1_TCKFI_BIT) |
paul@43 | 2480 | #define SSI_CR1_LFST (1 << 25) |
paul@43 | 2481 | #define SSI_CR1_ITFRM (1 << 24) |
paul@43 | 2482 | #define SSI_CR1_UNFIN (1 << 23) |
paul@43 | 2483 | #define SSI_CR1_MULTS (1 << 22) |
paul@43 | 2484 | #define SSI_CR1_FMAT_BIT 20 |
paul@43 | 2485 | #define SSI_CR1_FMAT_MASK (0x3 << SSI_CR1_FMAT_BIT) |
paul@43 | 2486 | #define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola????s SPI format */ |
paul@43 | 2487 | #define SSI_CR1_FMAT_SSP (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */ |
paul@43 | 2488 | #define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */ |
paul@43 | 2489 | #define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */ |
paul@43 | 2490 | #define SSI_CR1_MCOM_BIT 12 |
paul@43 | 2491 | #define SSI_CR1_MCOM_MASK (0xf << SSI_CR1_MCOM_BIT) |
paul@43 | 2492 | #define SSI_CR1_MCOM_1BIT (0x0 << SSI_CR1_MCOM_BIT) /* 1-bit command selected */ |
paul@43 | 2493 | #define SSI_CR1_MCOM_2BIT (0x1 << SSI_CR1_MCOM_BIT) /* 2-bit command selected */ |
paul@43 | 2494 | #define SSI_CR1_MCOM_3BIT (0x2 << SSI_CR1_MCOM_BIT) /* 3-bit command selected */ |
paul@43 | 2495 | #define SSI_CR1_MCOM_4BIT (0x3 << SSI_CR1_MCOM_BIT) /* 4-bit command selected */ |
paul@43 | 2496 | #define SSI_CR1_MCOM_5BIT (0x4 << SSI_CR1_MCOM_BIT) /* 5-bit command selected */ |
paul@43 | 2497 | #define SSI_CR1_MCOM_6BIT (0x5 << SSI_CR1_MCOM_BIT) /* 6-bit command selected */ |
paul@43 | 2498 | #define SSI_CR1_MCOM_7BIT (0x6 << SSI_CR1_MCOM_BIT) /* 7-bit command selected */ |
paul@43 | 2499 | #define SSI_CR1_MCOM_8BIT (0x7 << SSI_CR1_MCOM_BIT) /* 8-bit command selected */ |
paul@43 | 2500 | #define SSI_CR1_MCOM_9BIT (0x8 << SSI_CR1_MCOM_BIT) /* 9-bit command selected */ |
paul@43 | 2501 | #define SSI_CR1_MCOM_10BIT (0x9 << SSI_CR1_MCOM_BIT) /* 10-bit command selected */ |
paul@43 | 2502 | #define SSI_CR1_MCOM_11BIT (0xA << SSI_CR1_MCOM_BIT) /* 11-bit command selected */ |
paul@43 | 2503 | #define SSI_CR1_MCOM_12BIT (0xB << SSI_CR1_MCOM_BIT) /* 12-bit command selected */ |
paul@43 | 2504 | #define SSI_CR1_MCOM_13BIT (0xC << SSI_CR1_MCOM_BIT) /* 13-bit command selected */ |
paul@43 | 2505 | #define SSI_CR1_MCOM_14BIT (0xD << SSI_CR1_MCOM_BIT) /* 14-bit command selected */ |
paul@43 | 2506 | #define SSI_CR1_MCOM_15BIT (0xE << SSI_CR1_MCOM_BIT) /* 15-bit command selected */ |
paul@43 | 2507 | #define SSI_CR1_MCOM_16BIT (0xF << SSI_CR1_MCOM_BIT) /* 16-bit command selected */ |
paul@43 | 2508 | #define SSI_CR1_TTRG_BIT 10 |
paul@43 | 2509 | #define SSI_CR1_TTRG_MASK (0x3 << SSI_CR1_TTRG_BIT) |
paul@43 | 2510 | #define SSI_CR1_TTRG_1 (0 << SSI_CR1_TTRG_BIT)/* Less than or equal to 1 */ |
paul@43 | 2511 | #define SSI_CR1_TTRG_4 (1 << SSI_CR1_TTRG_BIT) /* Less than or equal to 4 */ |
paul@43 | 2512 | #define SSI_CR1_TTRG_8 (2 << SSI_CR1_TTRG_BIT) /* Less than or equal to 8 */ |
paul@43 | 2513 | #define SSI_CR1_TTRG_14 (3 << SSI_CR1_TTRG_BIT) /* Less than or equal to 14 */ |
paul@43 | 2514 | #define SSI_CR1_RTRG_BIT 8 |
paul@43 | 2515 | #define SSI_CR1_RTRG_MASK (0x3 << SSI_CR1_RTRG_BIT) |
paul@43 | 2516 | #define SSI_CR1_RTRG_1 (0 << SSI_CR1_RTRG_BIT) /* More than or equal to 1 */ |
paul@43 | 2517 | #define SSI_CR1_RTRG_4 (1 << SSI_CR1_RTRG_BIT) /* More than or equal to 4 */ |
paul@43 | 2518 | #define SSI_CR1_RTRG_8 (2 << SSI_CR1_RTRG_BIT) /* More than or equal to 8 */ |
paul@43 | 2519 | #define SSI_CR1_RTRG_14 (3 << SSI_CR1_RTRG_BIT) /* More than or equal to 14 */ |
paul@43 | 2520 | #define SSI_CR1_FLEN_BIT 4 |
paul@43 | 2521 | #define SSI_CR1_FLEN_MASK (0xf << SSI_CR1_FLEN_BIT) |
paul@43 | 2522 | #define SSI_CR1_FLEN_2BIT (0x0 << SSI_CR1_FLEN_BIT) |
paul@43 | 2523 | #define SSI_CR1_FLEN_3BIT (0x1 << SSI_CR1_FLEN_BIT) |
paul@43 | 2524 | #define SSI_CR1_FLEN_4BIT (0x2 << SSI_CR1_FLEN_BIT) |
paul@43 | 2525 | #define SSI_CR1_FLEN_5BIT (0x3 << SSI_CR1_FLEN_BIT) |
paul@43 | 2526 | #define SSI_CR1_FLEN_6BIT (0x4 << SSI_CR1_FLEN_BIT) |
paul@43 | 2527 | #define SSI_CR1_FLEN_7BIT (0x5 << SSI_CR1_FLEN_BIT) |
paul@43 | 2528 | #define SSI_CR1_FLEN_8BIT (0x6 << SSI_CR1_FLEN_BIT) |
paul@43 | 2529 | #define SSI_CR1_FLEN_9BIT (0x7 << SSI_CR1_FLEN_BIT) |
paul@43 | 2530 | #define SSI_CR1_FLEN_10BIT (0x8 << SSI_CR1_FLEN_BIT) |
paul@43 | 2531 | #define SSI_CR1_FLEN_11BIT (0x9 << SSI_CR1_FLEN_BIT) |
paul@43 | 2532 | #define SSI_CR1_FLEN_12BIT (0xA << SSI_CR1_FLEN_BIT) |
paul@43 | 2533 | #define SSI_CR1_FLEN_13BIT (0xB << SSI_CR1_FLEN_BIT) |
paul@43 | 2534 | #define SSI_CR1_FLEN_14BIT (0xC << SSI_CR1_FLEN_BIT) |
paul@43 | 2535 | #define SSI_CR1_FLEN_15BIT (0xD << SSI_CR1_FLEN_BIT) |
paul@43 | 2536 | #define SSI_CR1_FLEN_16BIT (0xE << SSI_CR1_FLEN_BIT) |
paul@43 | 2537 | #define SSI_CR1_FLEN_17BIT (0xF << SSI_CR1_FLEN_BIT) |
paul@43 | 2538 | #define SSI_CR1_PHA (1 << 1) |
paul@43 | 2539 | #define SSI_CR1_POL (1 << 0) |
paul@43 | 2540 | |
paul@43 | 2541 | /* SSI Status Register (SSI_SR) */ |
paul@43 | 2542 | |
paul@43 | 2543 | #define SSI_SR_TFIFONUM_BIT 13 |
paul@43 | 2544 | #define SSI_SR_TFIFONUM_MASK (0x1f << SSI_SR_TFIFONUM_BIT) |
paul@43 | 2545 | #define SSI_SR_RFIFONUM_BIT 8 |
paul@43 | 2546 | #define SSI_SR_RFIFONUM_MASK (0x1f << SSI_SR_RFIFONUM_BIT) |
paul@43 | 2547 | #define SSI_SR_END (1 << 7) |
paul@43 | 2548 | #define SSI_SR_BUSY (1 << 6) |
paul@43 | 2549 | #define SSI_SR_TFF (1 << 5) |
paul@43 | 2550 | #define SSI_SR_RFE (1 << 4) |
paul@43 | 2551 | #define SSI_SR_TFHE (1 << 3) |
paul@43 | 2552 | #define SSI_SR_RFHF (1 << 2) |
paul@43 | 2553 | #define SSI_SR_UNDR (1 << 1) |
paul@43 | 2554 | #define SSI_SR_OVER (1 << 0) |
paul@43 | 2555 | |
paul@43 | 2556 | /* SSI Interval Time Control Register (SSI_ITR) */ |
paul@43 | 2557 | |
paul@43 | 2558 | #define SSI_ITR_CNTCLK (1 << 15) |
paul@43 | 2559 | #define SSI_ITR_IVLTM_BIT 0 |
paul@43 | 2560 | #define SSI_ITR_IVLTM_MASK (0x7fff << SSI_ITR_IVLTM_BIT) |
paul@43 | 2561 | |
paul@43 | 2562 | #ifndef __ASSEMBLY__ |
paul@43 | 2563 | |
paul@43 | 2564 | /*************************************************************************** |
paul@43 | 2565 | * MSC |
paul@43 | 2566 | ***************************************************************************/ |
paul@43 | 2567 | |
paul@43 | 2568 | #define __msc_start_op() \ |
paul@43 | 2569 | ( REG_MSC_STRPCL = MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START ) |
paul@43 | 2570 | |
paul@43 | 2571 | #define __msc_set_resto(to) ( REG_MSC_RESTO = to ) |
paul@43 | 2572 | #define __msc_set_rdto(to) ( REG_MSC_RDTO = to ) |
paul@43 | 2573 | #define __msc_set_cmd(cmd) ( REG_MSC_CMD = cmd ) |
paul@43 | 2574 | #define __msc_set_arg(arg) ( REG_MSC_ARG = arg ) |
paul@43 | 2575 | #define __msc_set_nob(nob) ( REG_MSC_NOB = nob ) |
paul@43 | 2576 | #define __msc_get_nob() ( REG_MSC_NOB ) |
paul@43 | 2577 | #define __msc_set_blklen(len) ( REG_MSC_BLKLEN = len ) |
paul@43 | 2578 | #define __msc_set_cmdat(cmdat) ( REG_MSC_CMDAT = cmdat ) |
paul@43 | 2579 | #define __msc_set_cmdat_ioabort() ( REG_MSC_CMDAT |= MSC_CMDAT_IO_ABORT ) |
paul@43 | 2580 | #define __msc_clear_cmdat_ioabort() ( REG_MSC_CMDAT &= ~MSC_CMDAT_IO_ABORT ) |
paul@43 | 2581 | |
paul@43 | 2582 | #define __msc_set_cmdat_bus_width1() \ |
paul@43 | 2583 | do { \ |
paul@43 | 2584 | REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \ |
paul@43 | 2585 | REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_1BIT; \ |
paul@43 | 2586 | } while(0) |
paul@43 | 2587 | |
paul@43 | 2588 | #define __msc_set_cmdat_bus_width4() \ |
paul@43 | 2589 | do { \ |
paul@43 | 2590 | REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \ |
paul@43 | 2591 | REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_4BIT; \ |
paul@43 | 2592 | } while(0) |
paul@43 | 2593 | |
paul@43 | 2594 | #define __msc_set_cmdat_dma_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DMA_EN ) |
paul@43 | 2595 | #define __msc_set_cmdat_init() ( REG_MSC_CMDAT |= MSC_CMDAT_INIT ) |
paul@43 | 2596 | #define __msc_set_cmdat_busy() ( REG_MSC_CMDAT |= MSC_CMDAT_BUSY ) |
paul@43 | 2597 | #define __msc_set_cmdat_stream() ( REG_MSC_CMDAT |= MSC_CMDAT_STREAM_BLOCK ) |
paul@43 | 2598 | #define __msc_set_cmdat_block() ( REG_MSC_CMDAT &= ~MSC_CMDAT_STREAM_BLOCK ) |
paul@43 | 2599 | #define __msc_set_cmdat_read() ( REG_MSC_CMDAT &= ~MSC_CMDAT_WRITE_READ ) |
paul@43 | 2600 | #define __msc_set_cmdat_write() ( REG_MSC_CMDAT |= MSC_CMDAT_WRITE_READ ) |
paul@43 | 2601 | #define __msc_set_cmdat_data_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DATA_EN ) |
paul@43 | 2602 | |
paul@43 | 2603 | /* r is MSC_CMDAT_RESPONSE_FORMAT_Rx or MSC_CMDAT_RESPONSE_FORMAT_NONE */ |
paul@43 | 2604 | #define __msc_set_cmdat_res_format(r) \ |
paul@43 | 2605 | do { \ |
paul@43 | 2606 | REG_MSC_CMDAT &= ~MSC_CMDAT_RESPONSE_FORMAT_MASK; \ |
paul@43 | 2607 | REG_MSC_CMDAT |= (r); \ |
paul@43 | 2608 | } while(0) |
paul@43 | 2609 | |
paul@43 | 2610 | #define __msc_clear_cmdat() \ |
paul@43 | 2611 | REG_MSC_CMDAT &= ~( MSC_CMDAT_IO_ABORT | MSC_CMDAT_DMA_EN | MSC_CMDAT_INIT| \ |
paul@43 | 2612 | MSC_CMDAT_BUSY | MSC_CMDAT_STREAM_BLOCK | MSC_CMDAT_WRITE_READ | \ |
paul@43 | 2613 | MSC_CMDAT_DATA_EN | MSC_CMDAT_RESPONSE_FORMAT_MASK ) |
paul@43 | 2614 | |
paul@43 | 2615 | #define __msc_get_imask() ( REG_MSC_IMASK ) |
paul@43 | 2616 | #define __msc_mask_all_intrs() ( REG_MSC_IMASK = 0xff ) |
paul@43 | 2617 | #define __msc_unmask_all_intrs() ( REG_MSC_IMASK = 0x00 ) |
paul@43 | 2618 | #define __msc_mask_rd() ( REG_MSC_IMASK |= MSC_IMASK_RXFIFO_RD_REQ ) |
paul@43 | 2619 | #define __msc_unmask_rd() ( REG_MSC_IMASK &= ~MSC_IMASK_RXFIFO_RD_REQ ) |
paul@43 | 2620 | #define __msc_mask_wr() ( REG_MSC_IMASK |= MSC_IMASK_TXFIFO_WR_REQ ) |
paul@43 | 2621 | #define __msc_unmask_wr() ( REG_MSC_IMASK &= ~MSC_IMASK_TXFIFO_WR_REQ ) |
paul@43 | 2622 | #define __msc_mask_endcmdres() ( REG_MSC_IMASK |= MSC_IMASK_END_CMD_RES ) |
paul@43 | 2623 | #define __msc_unmask_endcmdres() ( REG_MSC_IMASK &= ~MSC_IMASK_END_CMD_RES ) |
paul@43 | 2624 | #define __msc_mask_datatrandone() ( REG_MSC_IMASK |= MSC_IMASK_DATA_TRAN_DONE ) |
paul@43 | 2625 | #define __msc_unmask_datatrandone() ( REG_MSC_IMASK &= ~MSC_IMASK_DATA_TRAN_DONE ) |
paul@43 | 2626 | #define __msc_mask_prgdone() ( REG_MSC_IMASK |= MSC_IMASK_PRG_DONE ) |
paul@43 | 2627 | #define __msc_unmask_prgdone() ( REG_MSC_IMASK &= ~MSC_IMASK_PRG_DONE ) |
paul@43 | 2628 | |
paul@43 | 2629 | /* n=1,2,4,8,16,32,64,128 */ |
paul@43 | 2630 | #define __msc_set_clkrt_div(n) \ |
paul@43 | 2631 | do { \ |
paul@43 | 2632 | REG_MSC_CLKRT &= ~MSC_CLKRT_CLK_RATE_MASK; \ |
paul@43 | 2633 | REG_MSC_CLKRT |= MSC_CLKRT_CLK_RATE_DIV_##n; \ |
paul@43 | 2634 | } while(0) |
paul@43 | 2635 | |
paul@43 | 2636 | #define __msc_get_ireg() ( REG_MSC_IREG ) |
paul@43 | 2637 | #define __msc_ireg_rd() ( REG_MSC_IREG & MSC_IREG_RXFIFO_RD_REQ ) |
paul@43 | 2638 | #define __msc_ireg_wr() ( REG_MSC_IREG & MSC_IREG_TXFIFO_WR_REQ ) |
paul@43 | 2639 | #define __msc_ireg_end_cmd_res() ( REG_MSC_IREG & MSC_IREG_END_CMD_RES ) |
paul@43 | 2640 | #define __msc_ireg_data_tran_done() ( REG_MSC_IREG & MSC_IREG_DATA_TRAN_DONE ) |
paul@43 | 2641 | #define __msc_ireg_prg_done() ( REG_MSC_IREG & MSC_IREG_PRG_DONE ) |
paul@43 | 2642 | #define __msc_ireg_clear_end_cmd_res() ( REG_MSC_IREG = MSC_IREG_END_CMD_RES ) |
paul@43 | 2643 | #define __msc_ireg_clear_data_tran_done() ( REG_MSC_IREG = MSC_IREG_DATA_TRAN_DONE ) |
paul@43 | 2644 | #define __msc_ireg_clear_prg_done() ( REG_MSC_IREG = MSC_IREG_PRG_DONE ) |
paul@43 | 2645 | |
paul@43 | 2646 | #define __msc_get_stat() ( REG_MSC_STAT ) |
paul@43 | 2647 | #define __msc_stat_not_end_cmd_res() ( (REG_MSC_STAT & MSC_STAT_END_CMD_RES) == 0) |
paul@43 | 2648 | #define __msc_stat_crc_err() \ |
paul@43 | 2649 | ( REG_MSC_STAT & (MSC_STAT_CRC_RES_ERR | MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR_YES) ) |
paul@43 | 2650 | #define __msc_stat_res_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_RES_ERR ) |
paul@43 | 2651 | #define __msc_stat_rd_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_READ_ERROR ) |
paul@43 | 2652 | #define __msc_stat_wr_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_WRITE_ERROR_YES ) |
paul@43 | 2653 | #define __msc_stat_resto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_RES ) |
paul@43 | 2654 | #define __msc_stat_rdto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_READ ) |
paul@43 | 2655 | |
paul@43 | 2656 | #define __msc_rd_resfifo() ( REG_MSC_RES ) |
paul@43 | 2657 | #define __msc_rd_rxfifo() ( REG_MSC_RXFIFO ) |
paul@43 | 2658 | #define __msc_wr_txfifo(v) ( REG_MSC_TXFIFO = v ) |
paul@43 | 2659 | |
paul@43 | 2660 | #define __msc_reset() \ |
paul@43 | 2661 | do { \ |
paul@43 | 2662 | REG_MSC_STRPCL = MSC_STRPCL_RESET; \ |
paul@43 | 2663 | while (REG_MSC_STAT & MSC_STAT_IS_RESETTING); \ |
paul@43 | 2664 | } while (0) |
paul@43 | 2665 | |
paul@43 | 2666 | #define __msc_start_clk() \ |
paul@43 | 2667 | do { \ |
paul@43 | 2668 | REG_MSC_STRPCL &= ~MSC_STRPCL_CLOCK_CONTROL_MASK; \ |
paul@43 | 2669 | REG_MSC_STRPCL |= MSC_STRPCL_CLOCK_CONTROL_START; \ |
paul@43 | 2670 | } while (0) |
paul@43 | 2671 | |
paul@43 | 2672 | #define __msc_stop_clk() \ |
paul@43 | 2673 | do { \ |
paul@43 | 2674 | REG_MSC_STRPCL &= ~MSC_STRPCL_CLOCK_CONTROL_MASK; \ |
paul@43 | 2675 | REG_MSC_STRPCL |= MSC_STRPCL_CLOCK_CONTROL_STOP; \ |
paul@43 | 2676 | } while (0) |
paul@43 | 2677 | |
paul@43 | 2678 | #define MMC_CLK 19169200 |
paul@43 | 2679 | #define SD_CLK 24576000 |
paul@43 | 2680 | |
paul@43 | 2681 | /* msc_clk should little than pclk and little than clk retrieve from card */ |
paul@43 | 2682 | #define __msc_calc_clk_divisor(type,dev_clk,msc_clk,lv) \ |
paul@43 | 2683 | do { \ |
paul@43 | 2684 | unsigned int rate, pclk, i; \ |
paul@43 | 2685 | pclk = dev_clk; \ |
paul@43 | 2686 | rate = type?SD_CLK:MMC_CLK; \ |
paul@43 | 2687 | if (msc_clk && msc_clk < pclk) \ |
paul@43 | 2688 | pclk = msc_clk; \ |
paul@43 | 2689 | i = 0; \ |
paul@43 | 2690 | while (pclk < rate) \ |
paul@43 | 2691 | { \ |
paul@43 | 2692 | i ++; \ |
paul@43 | 2693 | rate >>= 1; \ |
paul@43 | 2694 | } \ |
paul@43 | 2695 | lv = i; \ |
paul@43 | 2696 | } while(0) |
paul@43 | 2697 | |
paul@43 | 2698 | /* divide rate to little than or equal to 400kHz */ |
paul@43 | 2699 | #define __msc_calc_slow_clk_divisor(type, lv) \ |
paul@43 | 2700 | do { \ |
paul@43 | 2701 | unsigned int rate, i; \ |
paul@43 | 2702 | rate = (type?SD_CLK:MMC_CLK)/1000/400; \ |
paul@43 | 2703 | i = 0; \ |
paul@43 | 2704 | while (rate > 0) \ |
paul@43 | 2705 | { \ |
paul@43 | 2706 | rate >>= 1; \ |
paul@43 | 2707 | i ++; \ |
paul@43 | 2708 | } \ |
paul@43 | 2709 | lv = i; \ |
paul@43 | 2710 | } while(0) |
paul@43 | 2711 | |
paul@43 | 2712 | /*************************************************************************** |
paul@43 | 2713 | * RTC |
paul@43 | 2714 | ***************************************************************************/ |
paul@43 | 2715 | |
paul@43 | 2716 | #define __rtc_start() ( REG_RTC_RCR |= RTC_RCR_START ) |
paul@43 | 2717 | #define __rtc_stop() ( REG_RTC_RCR &= ~RTC_RCR_START ) |
paul@43 | 2718 | |
paul@43 | 2719 | #define __rtc_enable_alarm() ( REG_RTC_RCR |= RTC_RCR_AE ) |
paul@43 | 2720 | #define __rtc_disable_alarm() ( REG_RTC_RCR &= ~RTC_RCR_AE ) |
paul@43 | 2721 | #define __rtc_enable_alarm_irq() ( REG_RTC_RCR |= RTC_RCR_AIE ) |
paul@43 | 2722 | #define __rtc_disable_alarm_irq() ( REG_RTC_RCR &= ~RTC_RCR_AIE ) |
paul@43 | 2723 | |
paul@43 | 2724 | #define __rtc_enable_1hz_irq() ( REG_RTC_RCR |= RTC_RCR_HZIE ) |
paul@43 | 2725 | #define __rtc_disable_1hz_irq() ( REG_RTC_RCR &= ~RTC_RCR_HZIE ) |
paul@43 | 2726 | |
paul@43 | 2727 | #define __rtc_is_alarm_flag() ( REG_RTC_RCR & RTC_RCR_AF ) |
paul@43 | 2728 | #define __rtc_is_1hz_flag() ( REG_RTC_RCR & RTC_RCR_HZ ) |
paul@43 | 2729 | #define __rtc_clear_alarm_flag() ( REG_RTC_RCR &= ~RTC_RCR_AF ) |
paul@43 | 2730 | #define __rtc_clear_1hz_flag() ( REG_RTC_RCR &= ~RTC_RCR_HZ ) |
paul@43 | 2731 | |
paul@43 | 2732 | #define __rtc_set_second(s) ( REG_RTC_RSR = (s) ) |
paul@43 | 2733 | #define __rtc_get_second() REG_RTC_RSR |
paul@43 | 2734 | #define __rtc_set_alarm(s) ( REG_RTC_RSAR = (s) ) |
paul@43 | 2735 | #define __rtc_get_alarm() REG_RTC_RSAR |
paul@43 | 2736 | |
paul@43 | 2737 | #define __rtc_adjust_1hz(f32k) \ |
paul@43 | 2738 | ( REG_RTC_RGR = (REG_RTC_RGR & ~(RTC_REG_DIV_MASK | RTC_RGR_ADJ_MASK)) | f32k | 0 ) |
paul@43 | 2739 | #define __rtc_lock_1hz() ( REG_RTC_RGR |= RTC_RGR_LOCK ) |
paul@43 | 2740 | |
paul@43 | 2741 | |
paul@43 | 2742 | /*************************************************************************** |
paul@43 | 2743 | * FIR |
paul@43 | 2744 | ***************************************************************************/ |
paul@43 | 2745 | |
paul@43 | 2746 | /* enable/disable fir unit */ |
paul@43 | 2747 | #define __fir_enable() ( REG_FIR_CR1 |= FIR_CR1_FIRUE ) |
paul@43 | 2748 | #define __fir_disable() ( REG_FIR_CR1 &= ~FIR_CR1_FIRUE ) |
paul@43 | 2749 | |
paul@43 | 2750 | /* enable/disable address comparison */ |
paul@43 | 2751 | #define __fir_enable_ac() ( REG_FIR_CR1 |= FIR_CR1_ACE ) |
paul@43 | 2752 | #define __fir_disable_ac() ( REG_FIR_CR1 &= ~FIR_CR1_ACE ) |
paul@43 | 2753 | |
paul@43 | 2754 | /* select frame end mode as underrun or normal */ |
paul@43 | 2755 | #define __fir_set_eous() ( REG_FIR_CR1 |= FIR_CR1_EOUS ) |
paul@43 | 2756 | #define __fir_clear_eous() ( REG_FIR_CR1 &= ~FIR_CR1_EOUS ) |
paul@43 | 2757 | |
paul@43 | 2758 | /* enable/disable transmitter idle interrupt */ |
paul@43 | 2759 | #define __fir_enable_tii() ( REG_FIR_CR1 |= FIR_CR1_TIIE ) |
paul@43 | 2760 | #define __fir_disable_tii() ( REG_FIR_CR1 &= ~FIR_CR1_TIIE ) |
paul@43 | 2761 | |
paul@43 | 2762 | /* enable/disable transmit FIFO service request interrupt */ |
paul@43 | 2763 | #define __fir_enable_tfi() ( REG_FIR_CR1 |= FIR_CR1_TFIE ) |
paul@43 | 2764 | #define __fir_disable_tfi() ( REG_FIR_CR1 &= ~FIR_CR1_TFIE ) |
paul@43 | 2765 | |
paul@43 | 2766 | /* enable/disable receive FIFO service request interrupt */ |
paul@43 | 2767 | #define __fir_enable_rfi() ( REG_FIR_CR1 |= FIR_CR1_RFIE ) |
paul@43 | 2768 | #define __fir_disable_rfi() ( REG_FIR_CR1 &= ~FIR_CR1_RFIE ) |
paul@43 | 2769 | |
paul@43 | 2770 | /* enable/disable tx function */ |
paul@43 | 2771 | #define __fir_tx_enable() ( REG_FIR_CR1 |= FIR_CR1_TXE ) |
paul@43 | 2772 | #define __fir_tx_disable() ( REG_FIR_CR1 &= ~FIR_CR1_TXE ) |
paul@43 | 2773 | |
paul@43 | 2774 | /* enable/disable rx function */ |
paul@43 | 2775 | #define __fir_rx_enable() ( REG_FIR_CR1 |= FIR_CR1_RXE ) |
paul@43 | 2776 | #define __fir_rx_disable() ( REG_FIR_CR1 &= ~FIR_CR1_RXE ) |
paul@43 | 2777 | |
paul@43 | 2778 | |
paul@43 | 2779 | /* enable/disable serial infrared interaction pulse (SIP) */ |
paul@43 | 2780 | #define __fir_enable_sip() ( REG_FIR_CR2 |= FIR_CR2_SIPE ) |
paul@43 | 2781 | #define __fir_disable_sip() ( REG_FIR_CR2 &= ~FIR_CR2_SIPE ) |
paul@43 | 2782 | |
paul@43 | 2783 | /* un-inverted CRC value is sent out */ |
paul@43 | 2784 | #define __fir_enable_bcrc() ( REG_FIR_CR2 |= FIR_CR2_BCRC ) |
paul@43 | 2785 | |
paul@43 | 2786 | /* inverted CRC value is sent out */ |
paul@43 | 2787 | #define __fir_disable_bcrc() ( REG_FIR_CR2 &= ~FIR_CR2_BCRC ) |
paul@43 | 2788 | |
paul@43 | 2789 | /* enable/disable Transmit Frame Length Register */ |
paul@43 | 2790 | #define __fir_enable_tflr() ( REG_FIR_CR2 |= FIR_CR2_TFLRS ) |
paul@43 | 2791 | #define __fir_disable_tflr() ( REG_FIR_CR2 &= ~FIR_CR2_TFLRS ) |
paul@43 | 2792 | |
paul@43 | 2793 | /* Preamble is transmitted in idle state */ |
paul@43 | 2794 | #define __fir_set_iss() ( REG_FIR_CR2 |= FIR_CR2_ISS ) |
paul@43 | 2795 | |
paul@43 | 2796 | /* Abort symbol is transmitted in idle state */ |
paul@43 | 2797 | #define __fir_clear_iss() ( REG_FIR_CR2 &= ~FIR_CR2_ISS ) |
paul@43 | 2798 | |
paul@43 | 2799 | /* enable/disable loopback mode */ |
paul@43 | 2800 | #define __fir_enable_loopback() ( REG_FIR_CR2 |= FIR_CR2_LMS ) |
paul@43 | 2801 | #define __fir_disable_loopback() ( REG_FIR_CR2 &= ~FIR_CR2_LMS ) |
paul@43 | 2802 | |
paul@43 | 2803 | /* select transmit pin polarity */ |
paul@43 | 2804 | #define __fir_tpp_negative() ( REG_FIR_CR2 |= FIR_CR2_TPPS ) |
paul@43 | 2805 | #define __fir_tpp_positive() ( REG_FIR_CR2 &= ~FIR_CR2_TPPS ) |
paul@43 | 2806 | |
paul@43 | 2807 | /* select receive pin polarity */ |
paul@43 | 2808 | #define __fir_rpp_negative() ( REG_FIR_CR2 |= FIR_CR2_RPPS ) |
paul@43 | 2809 | #define __fir_rpp_positive() ( REG_FIR_CR2 &= ~FIR_CR2_RPPS ) |
paul@43 | 2810 | |
paul@43 | 2811 | /* n=16,32,64,128 */ |
paul@43 | 2812 | #define __fir_set_txfifo_trigger(n) \ |
paul@43 | 2813 | do { \ |
paul@43 | 2814 | REG_FIR_CR2 &= ~FIR_CR2_TTRG_MASK; \ |
paul@43 | 2815 | REG_FIR_CR2 |= FIR_CR2_TTRG_##n; \ |
paul@43 | 2816 | } while (0) |
paul@43 | 2817 | |
paul@43 | 2818 | /* n=16,32,64,128 */ |
paul@43 | 2819 | #define __fir_set_rxfifo_trigger(n) \ |
paul@43 | 2820 | do { \ |
paul@43 | 2821 | REG_FIR_CR2 &= ~FIR_CR2_RTRG_MASK; \ |
paul@43 | 2822 | REG_FIR_CR2 |= FIR_CR2_RTRG_##n; \ |
paul@43 | 2823 | } while (0) |
paul@43 | 2824 | |
paul@43 | 2825 | |
paul@43 | 2826 | /* FIR status checking */ |
paul@43 | 2827 | |
paul@43 | 2828 | #define __fir_test_rfw() ( REG_FIR_SR & FIR_SR_RFW ) |
paul@43 | 2829 | #define __fir_test_rfa() ( REG_FIR_SR & FIR_SR_RFA ) |
paul@43 | 2830 | #define __fir_test_tfrtl() ( REG_FIR_SR & FIR_SR_TFRTL ) |
paul@43 | 2831 | #define __fir_test_rfrtl() ( REG_FIR_SR & FIR_SR_RFRTL ) |
paul@43 | 2832 | #define __fir_test_urun() ( REG_FIR_SR & FIR_SR_URUN ) |
paul@43 | 2833 | #define __fir_test_rfte() ( REG_FIR_SR & FIR_SR_RFTE ) |
paul@43 | 2834 | #define __fir_test_orun() ( REG_FIR_SR & FIR_SR_ORUN ) |
paul@43 | 2835 | #define __fir_test_crce() ( REG_FIR_SR & FIR_SR_CRCE ) |
paul@43 | 2836 | #define __fir_test_fend() ( REG_FIR_SR & FIR_SR_FEND ) |
paul@43 | 2837 | #define __fir_test_tff() ( REG_FIR_SR & FIR_SR_TFF ) |
paul@43 | 2838 | #define __fir_test_rfe() ( REG_FIR_SR & FIR_SR_RFE ) |
paul@43 | 2839 | #define __fir_test_tidle() ( REG_FIR_SR & FIR_SR_TIDLE ) |
paul@43 | 2840 | #define __fir_test_rb() ( REG_FIR_SR & FIR_SR_RB ) |
paul@43 | 2841 | |
paul@43 | 2842 | #define __fir_clear_status() \ |
paul@43 | 2843 | do { \ |
paul@43 | 2844 | REG_FIR_SR |= FIR_SR_RFW | FIR_SR_RFA | FIR_SR_URUN; \ |
paul@43 | 2845 | } while (0) |
paul@43 | 2846 | |
paul@43 | 2847 | #define __fir_clear_rfw() ( REG_FIR_SR |= FIR_SR_RFW ) |
paul@43 | 2848 | #define __fir_clear_rfa() ( REG_FIR_SR |= FIR_SR_RFA ) |
paul@43 | 2849 | #define __fir_clear_urun() ( REG_FIR_SR |= FIR_SR_URUN ) |
paul@43 | 2850 | |
paul@43 | 2851 | #define __fir_set_tflr(len) \ |
paul@43 | 2852 | do { \ |
paul@43 | 2853 | REG_FIR_TFLR = len; \ |
paul@43 | 2854 | } while (0) |
paul@43 | 2855 | |
paul@43 | 2856 | #define __fir_set_addr(a) ( REG_FIR_AR = (a) ) |
paul@43 | 2857 | |
paul@43 | 2858 | #define __fir_write_data(data) ( REG_FIR_TDR = data ) |
paul@43 | 2859 | #define __fir_read_data(data) ( data = REG_FIR_RDR ) |
paul@43 | 2860 | |
paul@43 | 2861 | /*************************************************************************** |
paul@43 | 2862 | * SCC |
paul@43 | 2863 | ***************************************************************************/ |
paul@43 | 2864 | |
paul@43 | 2865 | #define __scc_enable(base) ( REG_SCC_CR(base) |= SCC_CR_SCCE ) |
paul@43 | 2866 | #define __scc_disable(base) ( REG_SCC_CR(base) &= ~SCC_CR_SCCE ) |
paul@43 | 2867 | |
paul@43 | 2868 | #define __scc_set_tx_mode(base) ( REG_SCC_CR(base) |= SCC_CR_TRS ) |
paul@43 | 2869 | #define __scc_set_rx_mode(base) ( REG_SCC_CR(base) &= ~SCC_CR_TRS ) |
paul@43 | 2870 | |
paul@43 | 2871 | #define __scc_enable_t2r(base) ( REG_SCC_CR(base) |= SCC_CR_T2R ) |
paul@43 | 2872 | #define __scc_disable_t2r(base) ( REG_SCC_CR(base) &= ~SCC_CR_T2R ) |
paul@43 | 2873 | |
paul@43 | 2874 | #define __scc_clk_as_devclk(base) \ |
paul@43 | 2875 | do { \ |
paul@43 | 2876 | REG_SCC_CR(base) &= ~SCC_CR_FDIV_MASK; \ |
paul@43 | 2877 | REG_SCC_CR(base) |= SCC_CR_FDIV_1; \ |
paul@43 | 2878 | } while (0) |
paul@43 | 2879 | |
paul@43 | 2880 | #define __scc_clk_as_half_devclk(base) \ |
paul@43 | 2881 | do { \ |
paul@43 | 2882 | REG_SCC_CR(base) &= ~SCC_CR_FDIV_MASK; \ |
paul@43 | 2883 | REG_SCC_CR(base) |= SCC_CR_FDIV_2; \ |
paul@43 | 2884 | } while (0) |
paul@43 | 2885 | |
paul@43 | 2886 | /* n=1,4,8,14 */ |
paul@43 | 2887 | #define __scc_set_fifo_trigger(base, n) \ |
paul@43 | 2888 | do { \ |
paul@43 | 2889 | REG_SCC_CR(base) &= ~SCC_CR_TRIG_MASK; \ |
paul@43 | 2890 | REG_SCC_CR(base) |= SCC_CR_TRIG_##n; \ |
paul@43 | 2891 | } while (0) |
paul@43 | 2892 | |
paul@43 | 2893 | #define __scc_set_protocol(base, p) \ |
paul@43 | 2894 | do { \ |
paul@43 | 2895 | if (p) \ |
paul@43 | 2896 | REG_SCC_CR(base) |= SCC_CR_TP; \ |
paul@43 | 2897 | else \ |
paul@43 | 2898 | REG_SCC_CR(base) &= ~SCC_CR_TP; \ |
paul@43 | 2899 | } while (0) |
paul@43 | 2900 | |
paul@43 | 2901 | #define __scc_flush_fifo(base) ( REG_SCC_CR(base) |= SCC_CR_FLUSH ) |
paul@43 | 2902 | |
paul@43 | 2903 | #define __scc_set_invert_mode(base) ( REG_SCC_CR(base) |= SCC_CR_CONV ) |
paul@43 | 2904 | #define __scc_set_direct_mode(base) ( REG_SCC_CR(base) &= ~SCC_CR_CONV ) |
paul@43 | 2905 | |
paul@43 | 2906 | #define SCC_ERR_INTRS \ |
paul@43 | 2907 | ( SCC_CR_ECIE | SCC_CR_EPIE | SCC_CR_RETIE | SCC_CR_EOIE ) |
paul@43 | 2908 | #define SCC_ALL_INTRS \ |
paul@43 | 2909 | ( SCC_CR_TXIE | SCC_CR_RXIE | SCC_CR_TENDIE | SCC_CR_RTOIE | \ |
paul@43 | 2910 | SCC_CR_ECIE | SCC_CR_EPIE | SCC_CR_RETIE | SCC_CR_EOIE ) |
paul@43 | 2911 | |
paul@43 | 2912 | #define __scc_enable_err_intrs(base) ( REG_SCC_CR(base) |= SCC_ERR_INTRS ) |
paul@43 | 2913 | #define __scc_disable_err_intrs(base) ( REG_SCC_CR(base) &= ~SCC_ERR_INTRS ) |
paul@43 | 2914 | |
paul@43 | 2915 | #define SCC_ALL_ERRORS \ |
paul@43 | 2916 | ( SCC_SR_ORER | SCC_SR_RTO | SCC_SR_PER | SCC_SR_RETR_3 | SCC_SR_ECNTO) |
paul@43 | 2917 | |
paul@43 | 2918 | #define __scc_clear_errors(base) ( REG_SCC_SR(base) &= ~SCC_ALL_ERRORS ) |
paul@43 | 2919 | |
paul@43 | 2920 | #define __scc_enable_all_intrs(base) ( REG_SCC_CR(base) |= SCC_ALL_INTRS ) |
paul@43 | 2921 | #define __scc_disable_all_intrs(base) ( REG_SCC_CR(base) &= ~SCC_ALL_INTRS ) |
paul@43 | 2922 | |
paul@43 | 2923 | #define __scc_enable_tx_intr(base) ( REG_SCC_CR(base) |= SCC_CR_TXIE | SCC_CR_TENDIE ) |
paul@43 | 2924 | #define __scc_disable_tx_intr(base) ( REG_SCC_CR(base) &= ~(SCC_CR_TXIE | SCC_CR_TENDIE) ) |
paul@43 | 2925 | |
paul@43 | 2926 | #define __scc_enable_rx_intr(base) ( REG_SCC_CR(base) |= SCC_CR_RXIE) |
paul@43 | 2927 | #define __scc_disable_rx_intr(base) ( REG_SCC_CR(base) &= ~SCC_CR_RXIE) |
paul@43 | 2928 | |
paul@43 | 2929 | #define __scc_set_tsend(base) ( REG_SCC_CR(base) |= SCC_CR_TSEND ) |
paul@43 | 2930 | #define __scc_clear_tsend(base) ( REG_SCC_CR(base) &= ~SCC_CR_TSEND ) |
paul@43 | 2931 | |
paul@43 | 2932 | #define __scc_set_clockstop(base) ( REG_SCC_CR(base) |= SCC_CR_CLKSTP ) |
paul@43 | 2933 | #define __scc_clear_clockstop(base) ( REG_SCC_CR(base) &= ~SCC_CR_CLKSTP ) |
paul@43 | 2934 | |
paul@43 | 2935 | #define __scc_clockstop_low(base) \ |
paul@43 | 2936 | do { \ |
paul@43 | 2937 | REG_SCC_CR(base) &= ~SCC_CR_PX_MASK; \ |
paul@43 | 2938 | REG_SCC_CR(base) |= SCC_CR_PX_STOP_LOW; \ |
paul@43 | 2939 | } while (0) |
paul@43 | 2940 | |
paul@43 | 2941 | #define __scc_clockstop_high(base) \ |
paul@43 | 2942 | do { \ |
paul@43 | 2943 | REG_SCC_CR(base) &= ~SCC_CR_PX_MASK; \ |
paul@43 | 2944 | REG_SCC_CR(base) |= SCC_CR_PX_STOP_HIGH; \ |
paul@43 | 2945 | } while (0) |
paul@43 | 2946 | |
paul@43 | 2947 | |
paul@43 | 2948 | /* SCC status checking */ |
paul@43 | 2949 | #define __scc_check_transfer_status(base) ( REG_SCC_SR(base) & SCC_SR_TRANS ) |
paul@43 | 2950 | #define __scc_check_rx_overrun_error(base) ( REG_SCC_SR(base) & SCC_SR_ORER ) |
paul@43 | 2951 | #define __scc_check_rx_timeout(base) ( REG_SCC_SR(base) & SCC_SR_RTO ) |
paul@43 | 2952 | #define __scc_check_parity_error(base) ( REG_SCC_SR(base) & SCC_SR_PER ) |
paul@43 | 2953 | #define __scc_check_txfifo_trigger(base) ( REG_SCC_SR(base) & SCC_SR_TFTG ) |
paul@43 | 2954 | #define __scc_check_rxfifo_trigger(base) ( REG_SCC_SR(base) & SCC_SR_RFTG ) |
paul@43 | 2955 | #define __scc_check_tx_end(base) ( REG_SCC_SR(base) & SCC_SR_TEND ) |
paul@43 | 2956 | #define __scc_check_retx_3(base) ( REG_SCC_SR(base) & SCC_SR_RETR_3 ) |
paul@43 | 2957 | #define __scc_check_ecnt_overflow(base) ( REG_SCC_SR(base) & SCC_SR_ECNTO ) |
paul@43 | 2958 | |
paul@43 | 2959 | |
paul@43 | 2960 | /*************************************************************************** |
paul@43 | 2961 | * WDT |
paul@43 | 2962 | ***************************************************************************/ |
paul@43 | 2963 | |
paul@43 | 2964 | #define __wdt_set_count(count) ( REG_WDT_WTCNT = (count) ) |
paul@43 | 2965 | #define __wdt_start() ( REG_WDT_WTCSR |= WDT_WTCSR_START ) |
paul@43 | 2966 | #define __wdt_stop() ( REG_WDT_WTCSR &= ~WDT_WTCSR_START ) |
paul@43 | 2967 | |
paul@43 | 2968 | |
paul@43 | 2969 | /*************************************************************************** |
paul@43 | 2970 | * OST |
paul@43 | 2971 | ***************************************************************************/ |
paul@43 | 2972 | |
paul@43 | 2973 | #define __ost_enable_all() ( REG_OST_TER |= 0x07 ) |
paul@43 | 2974 | #define __ost_disable_all() ( REG_OST_TER &= ~0x07 ) |
paul@43 | 2975 | #define __ost_enable_channel(n) ( REG_OST_TER |= (1 << (n)) ) |
paul@43 | 2976 | #define __ost_disable_channel(n) ( REG_OST_TER &= ~(1 << (n)) ) |
paul@43 | 2977 | #define __ost_set_reload(n, val) ( REG_OST_TRDR(n) = (val) ) |
paul@43 | 2978 | #define __ost_set_count(n, val) ( REG_OST_TCNT(n) = (val) ) |
paul@43 | 2979 | #define __ost_get_count(n) ( REG_OST_TCNT(n) ) |
paul@43 | 2980 | #define __ost_set_clock(n, cs) ( REG_OST_TCSR(n) |= (cs) ) |
paul@43 | 2981 | #define __ost_set_mode(n, val) ( REG_OST_TCSR(n) = (val) ) |
paul@43 | 2982 | #define __ost_enable_interrupt(n) ( REG_OST_TCSR(n) |= OST_TCSR_UIE ) |
paul@43 | 2983 | #define __ost_disable_interrupt(n) ( REG_OST_TCSR(n) &= ~OST_TCSR_UIE ) |
paul@43 | 2984 | #define __ost_uf_detected(n) ( REG_OST_TCSR(n) & OST_TCSR_UF ) |
paul@43 | 2985 | #define __ost_clear_uf(n) ( REG_OST_TCSR(n) &= ~OST_TCSR_UF ) |
paul@43 | 2986 | #define __ost_is_busy(n) ( REG_OST_TCSR(n) & OST_TCSR_BUSY ) |
paul@43 | 2987 | #define __ost_clear_busy(n) ( REG_OST_TCSR(n) &= ~OST_TCSR_BUSY ) |
paul@43 | 2988 | |
paul@43 | 2989 | |
paul@43 | 2990 | /*************************************************************************** |
paul@43 | 2991 | * UART |
paul@43 | 2992 | ***************************************************************************/ |
paul@43 | 2993 | |
paul@43 | 2994 | #define __uart_enable(n) \ |
paul@43 | 2995 | ( REG8(UART_BASE + UART_OFF*(n) + OFF_FCR) = UARTFCR_UUE | UARTFCR_FE ) |
paul@43 | 2996 | #define __uart_disable(n) \ |
paul@43 | 2997 | ( REG8(UART_BASE + UART_OFF*(n) + OFF_FCR) = ~UARTFCR_UUE ) |
paul@43 | 2998 | |
paul@43 | 2999 | #define __uart_enable_transmit_irq(n) \ |
paul@43 | 3000 | ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) |= UARTIER_TIE ) |
paul@43 | 3001 | #define __uart_disable_transmit_irq(n) \ |
paul@43 | 3002 | ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) &= ~UARTIER_TIE ) |
paul@43 | 3003 | |
paul@43 | 3004 | #define __uart_enable_receive_irq(n) \ |
paul@43 | 3005 | ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) |= UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE ) |
paul@43 | 3006 | #define __uart_disable_receive_irq(n) \ |
paul@43 | 3007 | ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) &= ~(UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE) ) |
paul@43 | 3008 | |
paul@43 | 3009 | #define __uart_enable_loopback(n) \ |
paul@43 | 3010 | ( REG8(UART_BASE + UART_OFF*(n) + OFF_MCR) |= UARTMCR_LOOP ) |
paul@43 | 3011 | #define __uart_disable_loopback(n) \ |
paul@43 | 3012 | ( REG8(UART_BASE + UART_OFF*(n) + OFF_MCR) &= ~UARTMCR_LOOP ) |
paul@43 | 3013 | |
paul@43 | 3014 | #define __uart_set_8n1(n) \ |
paul@43 | 3015 | ( REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) = UARTLCR_WLEN_8 ) |
paul@43 | 3016 | |
paul@43 | 3017 | #define __uart_set_baud(n, devclk, baud) \ |
paul@43 | 3018 | do { \ |
paul@43 | 3019 | REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) |= UARTLCR_DLAB; \ |
paul@43 | 3020 | REG8(UART_BASE + UART_OFF*(n) + OFF_DLLR) = (devclk / 16 / baud) & 0xff; \ |
paul@43 | 3021 | REG8(UART_BASE + UART_OFF*(n) + OFF_DLHR) = ((devclk / 16 / baud) >> 8) & 0xff; \ |
paul@43 | 3022 | REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) &= ~UARTLCR_DLAB; \ |
paul@43 | 3023 | } while (0) |
paul@43 | 3024 | |
paul@43 | 3025 | #define __uart_parity_error(n) \ |
paul@43 | 3026 | ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_PER) != 0 ) |
paul@43 | 3027 | |
paul@43 | 3028 | #define __uart_clear_errors(n) \ |
paul@43 | 3029 | ( REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) &= ~(UARTLSR_ORER | UARTLSR_BRK | UARTLSR_FER | UARTLSR_PER | UARTSR_RFER) ) |
paul@43 | 3030 | |
paul@43 | 3031 | #define __uart_transmit_fifo_empty(n) \ |
paul@43 | 3032 | ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_TDRQ) != 0 ) |
paul@43 | 3033 | |
paul@43 | 3034 | #define __uart_transmit_end(n) \ |
paul@43 | 3035 | ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_TEMT) != 0 ) |
paul@43 | 3036 | |
paul@43 | 3037 | #define __uart_transmit_char(n, ch) \ |
paul@43 | 3038 | REG8(UART_BASE + UART_OFF*(n) + OFF_TDR) = (ch) |
paul@43 | 3039 | |
paul@43 | 3040 | #define __uart_receive_fifo_full(n) \ |
paul@43 | 3041 | ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_DR) != 0 ) |
paul@43 | 3042 | |
paul@43 | 3043 | #define __uart_receive_ready(n) \ |
paul@43 | 3044 | ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_DR) != 0 ) |
paul@43 | 3045 | |
paul@43 | 3046 | #define __uart_receive_char(n) \ |
paul@43 | 3047 | REG8(UART_BASE + UART_OFF*(n) + OFF_RDR) |
paul@43 | 3048 | |
paul@43 | 3049 | #define __uart_disable_irda() \ |
paul@43 | 3050 | ( REG8(IRDA_BASE + OFF_SIRCR) &= ~(SIRCR_TSIRE | SIRCR_RSIRE) ) |
paul@43 | 3051 | #define __uart_enable_irda() \ |
paul@43 | 3052 | /* Tx high pulse as 0, Rx low pulse as 0 */ \ |
paul@43 | 3053 | ( REG8(IRDA_BASE + OFF_SIRCR) = SIRCR_TSIRE | SIRCR_RSIRE | SIRCR_RXPL | SIRCR_TPWS ) |
paul@43 | 3054 | |
paul@43 | 3055 | |
paul@43 | 3056 | /*************************************************************************** |
paul@43 | 3057 | * INTC |
paul@43 | 3058 | ***************************************************************************/ |
paul@43 | 3059 | #define __intc_unmask_irq(n) ( REG_INTC_IMCR = (1 << (n)) ) |
paul@43 | 3060 | #define __intc_mask_irq(n) ( REG_INTC_IMSR = (1 << (n)) ) |
paul@43 | 3061 | #define __intc_ack_irq(n) ( REG_INTC_IPR = (1 << (n)) ) |
paul@43 | 3062 | |
paul@43 | 3063 | /*************************************************************************** |
paul@43 | 3064 | * CIM |
paul@43 | 3065 | ***************************************************************************/ |
paul@43 | 3066 | |
paul@43 | 3067 | #define __cim_enable() ( REG_CIM_CTRL |= CIM_CTRL_ENA ) |
paul@43 | 3068 | #define __cim_disable() ( REG_CIM_CTRL &= ~CIM_CTRL_ENA ) |
paul@43 | 3069 | |
paul@43 | 3070 | #define __cim_input_data_inverse() ( REG_CIM_CFG |= CIM_CFG_INV_DAT ) |
paul@43 | 3071 | #define __cim_input_data_normal() ( REG_CIM_CFG &= ~CIM_CFG_INV_DAT ) |
paul@43 | 3072 | |
paul@43 | 3073 | #define __cim_vsync_active_low() ( REG_CIM_CFG |= CIM_CFG_VSP ) |
paul@43 | 3074 | #define __cim_vsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_VSP ) |
paul@43 | 3075 | |
paul@43 | 3076 | #define __cim_hsync_active_low() ( REG_CIM_CFG |= CIM_CFG_HSP ) |
paul@43 | 3077 | #define __cim_hsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_HSP ) |
paul@43 | 3078 | |
paul@43 | 3079 | #define __cim_sample_data_at_pclk_falling_edge() \ |
paul@43 | 3080 | ( REG_CIM_CFG |= CIM_CFG_PCP ) |
paul@43 | 3081 | #define __cim_sample_data_at_pclk_rising_edge() \ |
paul@43 | 3082 | ( REG_CIM_CFG &= ~CIM_CFG_PCP ) |
paul@43 | 3083 | |
paul@43 | 3084 | #define __cim_enable_dummy_zero() ( REG_CIM_CFG |= CIM_CFG_DUMMY_ZERO ) |
paul@43 | 3085 | #define __cim_disable_dummy_zero() ( REG_CIM_CFG &= ~CIM_CFG_DUMMY_ZERO ) |
paul@43 | 3086 | |
paul@43 | 3087 | #define __cim_select_external_vsync() ( REG_CIM_CFG |= CIM_CFG_EXT_VSYNC ) |
paul@43 | 3088 | #define __cim_select_internal_vsync() ( REG_CIM_CFG &= ~CIM_CFG_EXT_VSYNC ) |
paul@43 | 3089 | |
paul@43 | 3090 | /* n=0-7 */ |
paul@43 | 3091 | #define __cim_set_data_packing_mode(n) \ |
paul@43 | 3092 | do { \ |
paul@43 | 3093 | REG_CIM_CFG &= ~CIM_CFG_PACK_MASK; \ |
paul@43 | 3094 | REG_CIM_CFG |= (CIM_CFG_PACK_##n); \ |
paul@43 | 3095 | } while (0) |
paul@43 | 3096 | |
paul@43 | 3097 | #define __cim_enable_ccir656_progressive_mode() \ |
paul@43 | 3098 | do { \ |
paul@43 | 3099 | REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ |
paul@43 | 3100 | REG_CIM_CFG |= CIM_CFG_DSM_CPM; \ |
paul@43 | 3101 | } while (0) |
paul@43 | 3102 | |
paul@43 | 3103 | #define __cim_enable_ccir656_interlace_mode() \ |
paul@43 | 3104 | do { \ |
paul@43 | 3105 | REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ |
paul@43 | 3106 | REG_CIM_CFG |= CIM_CFG_DSM_CIM; \ |
paul@43 | 3107 | } while (0) |
paul@43 | 3108 | |
paul@43 | 3109 | #define __cim_enable_gated_clock_mode() \ |
paul@43 | 3110 | do { \ |
paul@43 | 3111 | REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ |
paul@43 | 3112 | REG_CIM_CFG |= CIM_CFG_DSM_GCM; \ |
paul@43 | 3113 | } while (0) |
paul@43 | 3114 | |
paul@43 | 3115 | #define __cim_enable_nongated_clock_mode() \ |
paul@43 | 3116 | do { \ |
paul@43 | 3117 | REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ |
paul@43 | 3118 | REG_CIM_CFG |= CIM_CFG_DSM_NGCM; \ |
paul@43 | 3119 | } while (0) |
paul@43 | 3120 | |
paul@43 | 3121 | /* sclk:system bus clock |
paul@43 | 3122 | * mclk: CIM master clock |
paul@43 | 3123 | */ |
paul@43 | 3124 | #define __cim_set_master_clk(sclk, mclk) \ |
paul@43 | 3125 | do { \ |
paul@43 | 3126 | REG_CIM_CTRL &= ~CIM_CTRL_MCLKDIV_MASK; \ |
paul@43 | 3127 | REG_CIM_CTRL |= (((sclk)/(mclk) - 1) << CIM_CTRL_MCLKDIV_BIT); \ |
paul@43 | 3128 | } while (0) |
paul@43 | 3129 | |
paul@43 | 3130 | #define __cim_enable_sof_intr() \ |
paul@43 | 3131 | ( REG_CIM_CTRL |= CIM_CTRL_DMA_SOFM ) |
paul@43 | 3132 | #define __cim_disable_sof_intr() \ |
paul@43 | 3133 | ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_SOFM ) |
paul@43 | 3134 | |
paul@43 | 3135 | #define __cim_enable_eof_intr() \ |
paul@43 | 3136 | ( REG_CIM_CTRL |= CIM_CTRL_DMA_EOFM ) |
paul@43 | 3137 | #define __cim_disable_eof_intr() \ |
paul@43 | 3138 | ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EOFM ) |
paul@43 | 3139 | |
paul@43 | 3140 | #define __cim_enable_stop_intr() \ |
paul@43 | 3141 | ( REG_CIM_CTRL |= CIM_CTRL_DMA_STOPM ) |
paul@43 | 3142 | #define __cim_disable_stop_intr() \ |
paul@43 | 3143 | ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_STOPM ) |
paul@43 | 3144 | |
paul@43 | 3145 | #define __cim_enable_trig_intr() \ |
paul@43 | 3146 | ( REG_CIM_CTRL |= CIM_CTRL_RXF_TRIGM ) |
paul@43 | 3147 | #define __cim_disable_trig_intr() \ |
paul@43 | 3148 | ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIGM ) |
paul@43 | 3149 | |
paul@43 | 3150 | #define __cim_enable_rxfifo_overflow_intr() \ |
paul@43 | 3151 | ( REG_CIM_CTRL |= CIM_CTRL_RXF_OFM ) |
paul@43 | 3152 | #define __cim_disable_rxfifo_overflow_intr() \ |
paul@43 | 3153 | ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_OFM ) |
paul@43 | 3154 | |
paul@43 | 3155 | /* n=1-16 */ |
paul@43 | 3156 | #define __cim_set_frame_rate(n) \ |
paul@43 | 3157 | do { \ |
paul@43 | 3158 | REG_CIM_CTRL &= ~CIM_CTRL_FRC_MASK; \ |
paul@43 | 3159 | REG_CIM_CTRL |= CIM_CTRL_FRC_##n; \ |
paul@43 | 3160 | } while (0) |
paul@43 | 3161 | |
paul@43 | 3162 | #define __cim_enable_dma() ( REG_CIM_CTRL |= CIM_CTRL_DMA_EN ) |
paul@43 | 3163 | #define __cim_disable_dma() ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EN ) |
paul@43 | 3164 | |
paul@43 | 3165 | #define __cim_reset_rxfifo() ( REG_CIM_CTRL |= CIM_CTRL_RXF_RST ) |
paul@43 | 3166 | #define __cim_unreset_rxfifo() ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_RST ) |
paul@43 | 3167 | |
paul@43 | 3168 | /* n=4,8,12,16,20,24,28,32 */ |
paul@43 | 3169 | #define __cim_set_rxfifo_trigger(n) \ |
paul@43 | 3170 | do { \ |
paul@43 | 3171 | REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIG_MASK; \ |
paul@43 | 3172 | REG_CIM_CTRL |= CIM_CTRL_RXF_TRIG_##n; \ |
paul@43 | 3173 | } while (0) |
paul@43 | 3174 | |
paul@43 | 3175 | #define __cim_clear_state() ( REG_CIM_STATE = 0 ) |
paul@43 | 3176 | |
paul@43 | 3177 | #define __cim_disable_done() ( REG_CIM_STATE & CIM_STATE_VDD ) |
paul@43 | 3178 | #define __cim_rxfifo_empty() ( REG_CIM_STATE & CIM_STATE_RXF_EMPTY ) |
paul@43 | 3179 | #define __cim_rxfifo_reach_trigger() ( REG_CIM_STATE & CIM_STATE_RXF_TRIG ) |
paul@43 | 3180 | #define __cim_rxfifo_overflow() ( REG_CIM_STATE & CIM_STATE_RXF_OF ) |
paul@43 | 3181 | #define __cim_clear_rxfifo_overflow() ( REG_CIM_STATE &= ~CIM_STATE_RXF_OF ) |
paul@43 | 3182 | #define __cim_dma_stop() ( REG_CIM_STATE & CIM_STATE_DMA_STOP ) |
paul@43 | 3183 | #define __cim_dma_eof() ( REG_CIM_STATE & CIM_STATE_DMA_EOF ) |
paul@43 | 3184 | #define __cim_dma_sof() ( REG_CIM_STATE & CIM_STATE_DMA_SOF ) |
paul@43 | 3185 | |
paul@43 | 3186 | #define __cim_get_iid() ( REG_CIM_IID ) |
paul@43 | 3187 | #define __cim_get_image_data() ( REG_CIM_RXFIFO ) |
paul@43 | 3188 | #define __cim_get_dam_cmd() ( REG_CIM_CMD ) |
paul@43 | 3189 | |
paul@43 | 3190 | #define __cim_set_da(a) ( REG_CIM_DA = (a) ) |
paul@43 | 3191 | |
paul@43 | 3192 | /*************************************************************************** |
paul@43 | 3193 | * PWM |
paul@43 | 3194 | ***************************************************************************/ |
paul@43 | 3195 | |
paul@43 | 3196 | /* n is the pwm channel (0,1,..) */ |
paul@43 | 3197 | #define __pwm_enable_module(n) ( REG_PWM_CTR(n) |= PWM_CTR_EN ) |
paul@43 | 3198 | #define __pwm_disable_module(n) ( REG_PWM_CTR(n) &= ~PWM_CTR_EN ) |
paul@43 | 3199 | #define __pwm_graceful_shutdown_mode(n) ( REG_PWM_CTR(n) &= ~PWM_CTR_SD ) |
paul@43 | 3200 | #define __pwm_abrupt_shutdown_mode(n) ( REG_PWM_CTR(n) |= PWM_CTR_SD ) |
paul@43 | 3201 | #define __pwm_set_full_duty(n) ( REG_PWM_DUT(n) |= PWM_DUT_FDUTY ) |
paul@43 | 3202 | |
paul@43 | 3203 | #define __pwm_set_prescale(n, p) \ |
paul@43 | 3204 | ( REG_PWM_CTR(n) = ((REG_PWM_CTR(n) & ~PWM_CTR_PRESCALE_MASK) | (p) ) ) |
paul@43 | 3205 | #define __pwm_set_period(n, p) \ |
paul@43 | 3206 | ( REG_PWM_PER(n) = ( (REG_PWM_PER(n) & ~PWM_PER_PERIOD_MASK) | (p) ) ) |
paul@43 | 3207 | #define __pwm_set_duty(n, d) \ |
paul@43 | 3208 | ( REG_PWM_DUT(n) = ( (REG_PWM_DUT(n) & ~PWM_DUT_FDUTY) | (d) ) ) |
paul@43 | 3209 | |
paul@43 | 3210 | /*************************************************************************** |
paul@43 | 3211 | * EMC |
paul@43 | 3212 | ***************************************************************************/ |
paul@43 | 3213 | |
paul@43 | 3214 | #define __emc_enable_split() ( REG_EMC_BCR = EMC_BCR_BRE ) |
paul@43 | 3215 | #define __emc_disable_split() ( REG_EMC_BCR = 0 ) |
paul@43 | 3216 | |
paul@43 | 3217 | #define __emc_smem_bus_width(n) /* 8, 16 or 32*/ \ |
paul@43 | 3218 | ( REG_EMC_SMCR = (REG_EMC_SMCR & EMC_SMCR_BW_MASK) | \ |
paul@43 | 3219 | EMC_SMCR_BW_##n##BIT ) |
paul@43 | 3220 | #define __emc_smem_byte_control() \ |
paul@43 | 3221 | ( REG_EMC_SMCR = (REG_EMC_SMCR | EMC_SMCR_BCM ) |
paul@43 | 3222 | #define __emc_normal_smem() \ |
paul@43 | 3223 | ( REG_EMC_SMCR = (REG_EMC_SMCR & ~EMC_SMCR_SMT ) |
paul@43 | 3224 | #define __emc_burst_smem() \ |
paul@43 | 3225 | ( REG_EMC_SMCR = (REG_EMC_SMCR | EMC_SMCR_SMT ) |
paul@43 | 3226 | #define __emc_smem_burstlen(n) /* 4, 8, 16 or 32 */ \ |
paul@43 | 3227 | ( REG_EMC_SMCR = (REG_EMC_SMCR & EMC_SMCR_BL_MASK) | (EMC_SMCR_BL_##n ) |
paul@43 | 3228 | |
paul@43 | 3229 | /*************************************************************************** |
paul@43 | 3230 | * GPIO |
paul@43 | 3231 | ***************************************************************************/ |
paul@43 | 3232 | |
paul@43 | 3233 | /* p is the port number (0,1,2,3) |
paul@43 | 3234 | * o is the pin offset (0-31) inside the port |
paul@43 | 3235 | * n is the absolute number of a pin (0-124), regardless of the port |
paul@43 | 3236 | * m is the interrupt manner (low/high/falling/rising) |
paul@43 | 3237 | */ |
paul@43 | 3238 | |
paul@43 | 3239 | #define __gpio_port_data(p) ( REG_GPIO_GPDR(p) ) |
paul@43 | 3240 | |
paul@43 | 3241 | #define __gpio_port_as_output(p, o) \ |
paul@43 | 3242 | do { \ |
paul@43 | 3243 | unsigned int tmp; \ |
paul@43 | 3244 | REG_GPIO_GPIER(p) &= ~(1 << (o)); \ |
paul@43 | 3245 | REG_GPIO_GPDIR(p) |= (1 << (o)); \ |
paul@43 | 3246 | if (o < 16) { \ |
paul@43 | 3247 | tmp = REG_GPIO_GPALR(p); \ |
paul@43 | 3248 | tmp &= ~(3 << ((o) << 1)); \ |
paul@43 | 3249 | REG_GPIO_GPALR(p) = tmp; \ |
paul@43 | 3250 | } else { \ |
paul@43 | 3251 | tmp = REG_GPIO_GPAUR(p); \ |
paul@43 | 3252 | tmp &= ~(3 << (((o) - 16)<< 1)); \ |
paul@43 | 3253 | REG_GPIO_GPAUR(p) = tmp; \ |
paul@43 | 3254 | } \ |
paul@43 | 3255 | } while (0) |
paul@43 | 3256 | |
paul@43 | 3257 | #define __gpio_port_as_input(p, o) \ |
paul@43 | 3258 | do { \ |
paul@43 | 3259 | unsigned int tmp; \ |
paul@43 | 3260 | REG_GPIO_GPIER(p) &= ~(1 << (o)); \ |
paul@43 | 3261 | REG_GPIO_GPDIR(p) &= ~(1 << (o)); \ |
paul@43 | 3262 | if (o < 16) { \ |
paul@43 | 3263 | tmp = REG_GPIO_GPALR(p); \ |
paul@43 | 3264 | tmp &= ~(3 << ((o) << 1)); \ |
paul@43 | 3265 | REG_GPIO_GPALR(p) = tmp; \ |
paul@43 | 3266 | } else { \ |
paul@43 | 3267 | tmp = REG_GPIO_GPAUR(p); \ |
paul@43 | 3268 | tmp &= ~(3 << (((o) - 16)<< 1)); \ |
paul@43 | 3269 | REG_GPIO_GPAUR(p) = tmp; \ |
paul@43 | 3270 | } \ |
paul@43 | 3271 | } while (0) |
paul@43 | 3272 | |
paul@43 | 3273 | #define __gpio_as_output(n) \ |
paul@43 | 3274 | do { \ |
paul@43 | 3275 | unsigned int p, o; \ |
paul@43 | 3276 | p = (n) / 32; \ |
paul@43 | 3277 | o = (n) % 32; \ |
paul@43 | 3278 | __gpio_port_as_output(p, o); \ |
paul@43 | 3279 | } while (0) |
paul@43 | 3280 | |
paul@43 | 3281 | #define __gpio_as_input(n) \ |
paul@43 | 3282 | do { \ |
paul@43 | 3283 | unsigned int p, o; \ |
paul@43 | 3284 | p = (n) / 32; \ |
paul@43 | 3285 | o = (n) % 32; \ |
paul@43 | 3286 | __gpio_port_as_input(p, o); \ |
paul@43 | 3287 | } while (0) |
paul@43 | 3288 | |
paul@43 | 3289 | #define __gpio_set_pin(n) \ |
paul@43 | 3290 | do { \ |
paul@43 | 3291 | unsigned int p, o; \ |
paul@43 | 3292 | p = (n) / 32; \ |
paul@43 | 3293 | o = (n) % 32; \ |
paul@43 | 3294 | __gpio_port_data(p) |= (1 << o); \ |
paul@43 | 3295 | } while (0) |
paul@43 | 3296 | |
paul@43 | 3297 | #define __gpio_clear_pin(n) \ |
paul@43 | 3298 | do { \ |
paul@43 | 3299 | unsigned int p, o; \ |
paul@43 | 3300 | p = (n) / 32; \ |
paul@43 | 3301 | o = (n) % 32; \ |
paul@43 | 3302 | __gpio_port_data(p) &= ~(1 << o); \ |
paul@43 | 3303 | } while (0) |
paul@43 | 3304 | |
paul@43 | 3305 | static __inline__ unsigned int __gpio_get_pin(unsigned int n) |
paul@43 | 3306 | { |
paul@43 | 3307 | unsigned int p, o; |
paul@43 | 3308 | p = (n) / 32; |
paul@43 | 3309 | o = (n) % 32; |
paul@43 | 3310 | if (__gpio_port_data(p) & (1 << o)) |
paul@43 | 3311 | return 1; |
paul@43 | 3312 | else |
paul@43 | 3313 | return 0; |
paul@43 | 3314 | } |
paul@43 | 3315 | |
paul@43 | 3316 | |
paul@43 | 3317 | #define __gpio_set_irq_detect_manner(p, o, m) \ |
paul@43 | 3318 | do { \ |
paul@43 | 3319 | unsigned int tmp; \ |
paul@43 | 3320 | if (o < 16) { \ |
paul@43 | 3321 | tmp = REG_GPIO_GPIDLR(p); \ |
paul@43 | 3322 | tmp &= ~(3 << ((o) << 1)); \ |
paul@43 | 3323 | tmp |= ((m) << ((o) << 1)); \ |
paul@43 | 3324 | REG_GPIO_GPIDLR(p) = tmp; \ |
paul@43 | 3325 | } else { \ |
paul@43 | 3326 | o -= 16; \ |
paul@43 | 3327 | tmp = REG_GPIO_GPIDUR(p); \ |
paul@43 | 3328 | tmp &= ~(3 << ((o) << 1)); \ |
paul@43 | 3329 | tmp |= ((m) << ((o) << 1)); \ |
paul@43 | 3330 | REG_GPIO_GPIDUR(p) = tmp; \ |
paul@43 | 3331 | } \ |
paul@43 | 3332 | } while (0) |
paul@43 | 3333 | |
paul@43 | 3334 | #define __gpio_port_as_irq(p, o, m) \ |
paul@43 | 3335 | do { \ |
paul@43 | 3336 | __gpio_set_irq_detect_manner(p, o, m); \ |
paul@43 | 3337 | __gpio_port_as_input(p, o); \ |
paul@43 | 3338 | REG_GPIO_GPIER(p) |= (1 << o); \ |
paul@43 | 3339 | } while (0) |
paul@43 | 3340 | |
paul@43 | 3341 | #define __gpio_as_irq(n, m) \ |
paul@43 | 3342 | do { \ |
paul@43 | 3343 | unsigned int p, o; \ |
paul@43 | 3344 | p = (n) / 32; \ |
paul@43 | 3345 | o = (n) % 32; \ |
paul@43 | 3346 | __gpio_port_as_irq(p, o, m); \ |
paul@43 | 3347 | } while (0) |
paul@43 | 3348 | |
paul@43 | 3349 | |
paul@43 | 3350 | #define __gpio_as_irq_high_level(n) __gpio_as_irq(n, GPIO_IRQ_HILEVEL) |
paul@43 | 3351 | #define __gpio_as_irq_low_level(n) __gpio_as_irq(n, GPIO_IRQ_LOLEVEL) |
paul@43 | 3352 | #define __gpio_as_irq_fall_edge(n) __gpio_as_irq(n, GPIO_IRQ_FALLEDG) |
paul@43 | 3353 | #define __gpio_as_irq_rise_edge(n) __gpio_as_irq(n, GPIO_IRQ_RAISEDG) |
paul@43 | 3354 | |
paul@43 | 3355 | |
paul@43 | 3356 | #define __gpio_mask_irq(n) \ |
paul@43 | 3357 | do { \ |
paul@43 | 3358 | unsigned int p, o; \ |
paul@43 | 3359 | p = (n) / 32; \ |
paul@43 | 3360 | o = (n) % 32; \ |
paul@43 | 3361 | REG_GPIO_GPIER(p) &= ~(1 << o); \ |
paul@43 | 3362 | } while (0) |
paul@43 | 3363 | |
paul@43 | 3364 | #define __gpio_unmask_irq(n) \ |
paul@43 | 3365 | do { \ |
paul@43 | 3366 | unsigned int p, o; \ |
paul@43 | 3367 | p = (n) / 32; \ |
paul@43 | 3368 | o = (n) % 32; \ |
paul@43 | 3369 | REG_GPIO_GPIER(n) |= (1 << o); \ |
paul@43 | 3370 | } while (0) |
paul@43 | 3371 | |
paul@43 | 3372 | #define __gpio_ack_irq(n) \ |
paul@43 | 3373 | do { \ |
paul@43 | 3374 | unsigned int p, o; \ |
paul@43 | 3375 | p = (n) / 32; \ |
paul@43 | 3376 | o = (n) % 32; \ |
paul@43 | 3377 | REG_GPIO_GPFR(p) |= (1 << o); \ |
paul@43 | 3378 | } while (0) |
paul@43 | 3379 | |
paul@43 | 3380 | |
paul@43 | 3381 | static __inline__ unsigned int __gpio_get_irq(void) |
paul@43 | 3382 | { |
paul@43 | 3383 | unsigned int tmp, i; |
paul@43 | 3384 | |
paul@43 | 3385 | tmp = REG_GPIO_GPFR(3); |
paul@43 | 3386 | for (i=0; i<32; i++) |
paul@43 | 3387 | if (tmp & (1 << i)) |
paul@43 | 3388 | return 0x60 + i; |
paul@43 | 3389 | tmp = REG_GPIO_GPFR(2); |
paul@43 | 3390 | for (i=0; i<32; i++) |
paul@43 | 3391 | if (tmp & (1 << i)) |
paul@43 | 3392 | return 0x40 + i; |
paul@43 | 3393 | tmp = REG_GPIO_GPFR(1); |
paul@43 | 3394 | for (i=0; i<32; i++) |
paul@43 | 3395 | if (tmp & (1 << i)) |
paul@43 | 3396 | return 0x20 + i; |
paul@43 | 3397 | tmp = REG_GPIO_GPFR(0); |
paul@43 | 3398 | for (i=0; i<32; i++) |
paul@43 | 3399 | if (tmp & (1 << i)) |
paul@43 | 3400 | return i; |
paul@43 | 3401 | return 0; |
paul@43 | 3402 | } |
paul@43 | 3403 | |
paul@43 | 3404 | #define __gpio_group_irq(n) \ |
paul@43 | 3405 | ({ \ |
paul@43 | 3406 | register int tmp, i; \ |
paul@43 | 3407 | tmp = REG_GPIO_GPFR((n)); \ |
paul@43 | 3408 | for (i=31;i>=0;i--) \ |
paul@43 | 3409 | if (tmp & (1 << i)) \ |
paul@43 | 3410 | break; \ |
paul@43 | 3411 | i; \ |
paul@43 | 3412 | }) |
paul@43 | 3413 | |
paul@43 | 3414 | #define __gpio_enable_pull(n) \ |
paul@43 | 3415 | do { \ |
paul@43 | 3416 | unsigned int p, o; \ |
paul@43 | 3417 | p = (n) / 32; \ |
paul@43 | 3418 | o = (n) % 32; \ |
paul@43 | 3419 | REG_GPIO_GPPUR(p) |= (1 << o); \ |
paul@43 | 3420 | } while (0) |
paul@43 | 3421 | |
paul@43 | 3422 | #define __gpio_disable_pull(n) \ |
paul@43 | 3423 | do { \ |
paul@43 | 3424 | unsigned int p, o; \ |
paul@43 | 3425 | p = (n) / 32; \ |
paul@43 | 3426 | o = (n) % 32; \ |
paul@43 | 3427 | REG_GPIO_GPPUR(p) &= ~(1 << o); \ |
paul@43 | 3428 | } while (0) |
paul@43 | 3429 | |
paul@43 | 3430 | /* Init the alternate function pins */ |
paul@43 | 3431 | |
paul@43 | 3432 | |
paul@43 | 3433 | #define __gpio_as_ssi() \ |
paul@43 | 3434 | do { \ |
paul@43 | 3435 | REG_GPIO_GPALR(2) &= 0xFC00FFFF; \ |
paul@43 | 3436 | REG_GPIO_GPALR(2) |= 0x01550000; \ |
paul@43 | 3437 | } while (0) |
paul@43 | 3438 | |
paul@43 | 3439 | #define __gpio_as_uart3() \ |
paul@43 | 3440 | do { \ |
paul@43 | 3441 | REG_GPIO_GPAUR(0) &= 0xFFFF0000; \ |
paul@43 | 3442 | REG_GPIO_GPAUR(0) |= 0x00005555; \ |
paul@43 | 3443 | } while (0) |
paul@43 | 3444 | |
paul@43 | 3445 | #define __gpio_as_uart2() \ |
paul@43 | 3446 | do { \ |
paul@43 | 3447 | REG_GPIO_GPALR(3) &= 0x3FFFFFFF; \ |
paul@43 | 3448 | REG_GPIO_GPALR(3) |= 0x40000000; \ |
paul@43 | 3449 | REG_GPIO_GPAUR(3) &= 0xF3FFFFFF; \ |
paul@43 | 3450 | REG_GPIO_GPAUR(3) |= 0x04000000; \ |
paul@43 | 3451 | } while (0) |
paul@43 | 3452 | |
paul@43 | 3453 | #define __gpio_as_uart1() \ |
paul@43 | 3454 | do { \ |
paul@43 | 3455 | REG_GPIO_GPAUR(0) &= 0xFFF0FFFF; \ |
paul@43 | 3456 | REG_GPIO_GPAUR(0) |= 0x00050000; \ |
paul@43 | 3457 | } while (0) |
paul@43 | 3458 | |
paul@43 | 3459 | #define __gpio_as_uart0() \ |
paul@43 | 3460 | do { \ |
paul@43 | 3461 | REG_GPIO_GPAUR(3) &= 0x0FFFFFFF; \ |
paul@43 | 3462 | REG_GPIO_GPAUR(3) |= 0x50000000; \ |
paul@43 | 3463 | } while (0) |
paul@43 | 3464 | |
paul@43 | 3465 | |
paul@43 | 3466 | #define __gpio_as_scc0() \ |
paul@43 | 3467 | do { \ |
paul@43 | 3468 | REG_GPIO_GPALR(2) &= 0xFFFFFFCC; \ |
paul@43 | 3469 | REG_GPIO_GPALR(2) |= 0x00000011; \ |
paul@43 | 3470 | } while (0) |
paul@43 | 3471 | |
paul@43 | 3472 | #define __gpio_as_scc1() \ |
paul@43 | 3473 | do { \ |
paul@43 | 3474 | REG_GPIO_GPALR(2) &= 0xFFFFFF33; \ |
paul@43 | 3475 | REG_GPIO_GPALR(2) |= 0x00000044; \ |
paul@43 | 3476 | } while (0) |
paul@43 | 3477 | |
paul@43 | 3478 | #define __gpio_as_scc() \ |
paul@43 | 3479 | do { \ |
paul@43 | 3480 | __gpio_as_scc0(); \ |
paul@43 | 3481 | __gpio_as_scc1(); \ |
paul@43 | 3482 | } while (0) |
paul@43 | 3483 | |
paul@43 | 3484 | #define __gpio_as_dma() \ |
paul@43 | 3485 | do { \ |
paul@43 | 3486 | REG_GPIO_GPALR(0) &= 0x00FFFFFF; \ |
paul@43 | 3487 | REG_GPIO_GPALR(0) |= 0x55000000; \ |
paul@43 | 3488 | REG_GPIO_GPAUR(0) &= 0xFF0FFFFF; \ |
paul@43 | 3489 | REG_GPIO_GPAUR(0) |= 0x00500000; \ |
paul@43 | 3490 | } while (0) |
paul@43 | 3491 | |
paul@43 | 3492 | #define __gpio_as_msc() \ |
paul@43 | 3493 | do { \ |
paul@43 | 3494 | REG_GPIO_GPALR(1) &= 0xFFFF000F; \ |
paul@43 | 3495 | REG_GPIO_GPALR(1) |= 0x00005550; \ |
paul@43 | 3496 | } while (0) |
paul@43 | 3497 | |
paul@43 | 3498 | #define __gpio_as_pcmcia() \ |
paul@43 | 3499 | do { \ |
paul@43 | 3500 | REG_GPIO_GPAUR(2) &= 0xF000FFFF; \ |
paul@43 | 3501 | REG_GPIO_GPAUR(2) |= 0x05550000; \ |
paul@43 | 3502 | } while (0) |
paul@43 | 3503 | |
paul@43 | 3504 | #define __gpio_as_emc() \ |
paul@43 | 3505 | do { \ |
paul@43 | 3506 | REG_GPIO_GPALR(2) &= 0x3FFFFFFF; \ |
paul@43 | 3507 | REG_GPIO_GPALR(2) |= 0x40000000; \ |
paul@43 | 3508 | REG_GPIO_GPAUR(2) &= 0xFFFF0000; \ |
paul@43 | 3509 | REG_GPIO_GPAUR(2) |= 0x00005555; \ |
paul@43 | 3510 | } while (0) |
paul@43 | 3511 | |
paul@43 | 3512 | #define __gpio_as_lcd_slave() \ |
paul@43 | 3513 | do { \ |
paul@43 | 3514 | REG_GPIO_GPALR(1) &= 0x0000FFFF; \ |
paul@43 | 3515 | REG_GPIO_GPALR(1) |= 0x55550000; \ |
paul@43 | 3516 | REG_GPIO_GPAUR(1) &= 0x00000000; \ |
paul@43 | 3517 | REG_GPIO_GPAUR(1) |= 0x55555555; \ |
paul@43 | 3518 | } while (0) |
paul@43 | 3519 | |
paul@43 | 3520 | #define __gpio_as_lcd_master() \ |
paul@43 | 3521 | do { \ |
paul@43 | 3522 | REG_GPIO_GPALR(1) &= 0x0000FFFF; \ |
paul@43 | 3523 | REG_GPIO_GPALR(1) |= 0x55550000; \ |
paul@43 | 3524 | REG_GPIO_GPAUR(1) &= 0x00000000; \ |
paul@43 | 3525 | REG_GPIO_GPAUR(1) |= 0x556A5555; \ |
paul@43 | 3526 | } while (0) |
paul@43 | 3527 | |
paul@43 | 3528 | #define __gpio_as_usb() \ |
paul@43 | 3529 | do { \ |
paul@43 | 3530 | REG_GPIO_GPAUR(0) &= 0x00FFFFFF; \ |
paul@43 | 3531 | REG_GPIO_GPAUR(0) |= 0x55000000; \ |
paul@43 | 3532 | } while (0) |
paul@43 | 3533 | |
paul@43 | 3534 | #define __gpio_as_ac97() \ |
paul@43 | 3535 | do { \ |
paul@43 | 3536 | REG_GPIO_GPALR(2) &= 0xC3FF03FF; \ |
paul@43 | 3537 | REG_GPIO_GPALR(2) |= 0x24005400; \ |
paul@43 | 3538 | } while (0) |
paul@43 | 3539 | |
paul@43 | 3540 | #define __gpio_as_i2s_slave() \ |
paul@43 | 3541 | do { \ |
paul@43 | 3542 | REG_GPIO_GPALR(2) &= 0xC3FF0CFF; \ |
paul@43 | 3543 | REG_GPIO_GPALR(2) |= 0x14005100; \ |
paul@43 | 3544 | } while (0) |
paul@43 | 3545 | |
paul@43 | 3546 | #define __gpio_as_i2s_master() \ |
paul@43 | 3547 | do { \ |
paul@43 | 3548 | REG_GPIO_GPALR(2) &= 0xC3FF0CFF; \ |
paul@43 | 3549 | REG_GPIO_GPALR(2) |= 0x28005100; \ |
paul@43 | 3550 | } while (0) |
paul@43 | 3551 | |
paul@43 | 3552 | #define __gpio_as_eth() \ |
paul@43 | 3553 | do { \ |
paul@43 | 3554 | REG_GPIO_GPAUR(3) &= 0xFC000000; \ |
paul@43 | 3555 | REG_GPIO_GPAUR(3) |= 0x01555555; \ |
paul@43 | 3556 | } while (0) |
paul@43 | 3557 | |
paul@43 | 3558 | #define __gpio_as_pwm() \ |
paul@43 | 3559 | do { \ |
paul@43 | 3560 | REG_GPIO_GPAUR(2) &= 0x0FFFFFFF; \ |
paul@43 | 3561 | REG_GPIO_GPAUR(2) |= 0x50000000; \ |
paul@43 | 3562 | } while (0) |
paul@43 | 3563 | |
paul@43 | 3564 | #define __gpio_as_ps2() \ |
paul@43 | 3565 | do { \ |
paul@43 | 3566 | REG_GPIO_GPALR(1) &= 0xFFFFFFF0; \ |
paul@43 | 3567 | REG_GPIO_GPALR(1) |= 0x00000005; \ |
paul@43 | 3568 | } while (0) |
paul@43 | 3569 | |
paul@43 | 3570 | #define __gpio_as_uprt() \ |
paul@43 | 3571 | do { \ |
paul@43 | 3572 | REG_GPIO_GPALR(1) &= 0x0000000F; \ |
paul@43 | 3573 | REG_GPIO_GPALR(1) |= 0x55555550; \ |
paul@43 | 3574 | REG_GPIO_GPALR(3) &= 0xC0000000; \ |
paul@43 | 3575 | REG_GPIO_GPALR(3) |= 0x15555555; \ |
paul@43 | 3576 | } while (0) |
paul@43 | 3577 | |
paul@43 | 3578 | #define __gpio_as_cim() \ |
paul@43 | 3579 | do { \ |
paul@43 | 3580 | REG_GPIO_GPALR(0) &= 0xFF000000; \ |
paul@43 | 3581 | REG_GPIO_GPALR(0) |= 0x00555555; \ |
paul@43 | 3582 | } while (0) |
paul@43 | 3583 | |
paul@43 | 3584 | /*************************************************************************** |
paul@43 | 3585 | * HARB |
paul@43 | 3586 | ***************************************************************************/ |
paul@43 | 3587 | |
paul@43 | 3588 | #define __harb_usb0_udc() \ |
paul@43 | 3589 | do { \ |
paul@43 | 3590 | REG_HARB_HAPOR &= ~HARB_HAPOR_UCHSEL; \ |
paul@43 | 3591 | } while (0) |
paul@43 | 3592 | |
paul@43 | 3593 | #define __harb_usb0_uhc() \ |
paul@43 | 3594 | do { \ |
paul@43 | 3595 | REG_HARB_HAPOR |= HARB_HAPOR_UCHSEL; \ |
paul@43 | 3596 | } while (0) |
paul@43 | 3597 | |
paul@43 | 3598 | #define __harb_set_priority(n) \ |
paul@43 | 3599 | do { \ |
paul@43 | 3600 | REG_HARB_HAPOR = ((REG_HARB_HAPOR & ~HARB_HAPOR_PRIO_MASK) | n); \ |
paul@43 | 3601 | } while (0) |
paul@43 | 3602 | |
paul@43 | 3603 | /*************************************************************************** |
paul@43 | 3604 | * I2C |
paul@43 | 3605 | ***************************************************************************/ |
paul@43 | 3606 | |
paul@43 | 3607 | #define __i2c_enable() ( REG_I2C_CR |= I2C_CR_I2CE ) |
paul@43 | 3608 | #define __i2c_disable() ( REG_I2C_CR &= ~I2C_CR_I2CE ) |
paul@43 | 3609 | |
paul@43 | 3610 | #define __i2c_send_start() ( REG_I2C_CR |= I2C_CR_STA ) |
paul@43 | 3611 | #define __i2c_send_stop() ( REG_I2C_CR |= I2C_CR_STO ) |
paul@43 | 3612 | #define __i2c_send_ack() ( REG_I2C_CR &= ~I2C_CR_AC ) |
paul@43 | 3613 | #define __i2c_send_nack() ( REG_I2C_CR |= I2C_CR_AC ) |
paul@43 | 3614 | |
paul@43 | 3615 | #define __i2c_set_drf() ( REG_I2C_SR |= I2C_SR_DRF ) |
paul@43 | 3616 | #define __i2c_clear_drf() ( REG_I2C_SR &= ~I2C_SR_DRF ) |
paul@43 | 3617 | #define __i2c_check_drf() ( REG_I2C_SR & I2C_SR_DRF ) |
paul@43 | 3618 | |
paul@43 | 3619 | #define __i2c_received_ack() ( !(REG_I2C_SR & I2C_SR_ACKF) ) |
paul@43 | 3620 | #define __i2c_is_busy() ( REG_I2C_SR & I2C_SR_BUSY ) |
paul@43 | 3621 | #define __i2c_transmit_ended() ( REG_I2C_SR & I2C_SR_TEND ) |
paul@43 | 3622 | |
paul@43 | 3623 | #define __i2c_set_clk(dev_clk, i2c_clk) \ |
paul@43 | 3624 | ( REG_I2C_GR = (dev_clk) / (16*(i2c_clk)) - 1 ) |
paul@43 | 3625 | |
paul@43 | 3626 | #define __i2c_read() ( REG_I2C_DR ) |
paul@43 | 3627 | #define __i2c_write(val) ( REG_I2C_DR = (val) ) |
paul@43 | 3628 | |
paul@43 | 3629 | /*************************************************************************** |
paul@43 | 3630 | * UDC |
paul@43 | 3631 | ***************************************************************************/ |
paul@43 | 3632 | |
paul@43 | 3633 | #define __udc_set_16bit_phy() ( REG_UDC_DevCFGR |= UDC_DevCFGR_PI ) |
paul@43 | 3634 | #define __udc_set_8bit_phy() ( REG_UDC_DevCFGR &= ~UDC_DevCFGR_PI ) |
paul@43 | 3635 | |
paul@43 | 3636 | #define __udc_enable_sync_frame() ( REG_UDC_DevCFGR |= UDC_DevCFGR_SS ) |
paul@43 | 3637 | #define __udc_disable_sync_frame() ( REG_UDC_DevCFGR &= ~UDC_DevCFGR_SS ) |
paul@43 | 3638 | |
paul@43 | 3639 | #define __udc_self_powered() ( REG_UDC_DevCFGR |= UDC_DevCFGR_SP ) |
paul@43 | 3640 | #define __udc_bus_powered() ( REG_UDC_DevCFGR &= ~UDC_DevCFGR_SP ) |
paul@43 | 3641 | |
paul@43 | 3642 | #define __udc_enable_remote_wakeup() ( REG_UDC_DevCFGR |= UDC_DevCFGR_RW ) |
paul@43 | 3643 | #define __udc_disable_remote_wakeup() ( REG_UDC_DevCFGR &= ~UDC_DevCFGR_RW ) |
paul@43 | 3644 | |
paul@43 | 3645 | #define __udc_set_speed_high() \ |
paul@43 | 3646 | do { \ |
paul@43 | 3647 | REG_UDC_DevCFGR &= ~UDC_DevCFGR_SPD_MASK; \ |
paul@43 | 3648 | REG_UDC_DevCFGR |= UDC_DevCFGR_SPD_HS; \ |
paul@43 | 3649 | } while (0) |
paul@43 | 3650 | |
paul@43 | 3651 | #define __udc_set_speed_full() \ |
paul@43 | 3652 | do { \ |
paul@43 | 3653 | REG_UDC_DevCFGR &= ~UDC_DevCFGR_SPD_MASK; \ |
paul@43 | 3654 | REG_UDC_DevCFGR |= UDC_DevCFGR_SPD_FS; \ |
paul@43 | 3655 | } while (0) |
paul@43 | 3656 | |
paul@43 | 3657 | #define __udc_set_speed_low() \ |
paul@43 | 3658 | do { \ |
paul@43 | 3659 | REG_UDC_DevCFGR &= ~UDC_DevCFGR_SPD_MASK; \ |
paul@43 | 3660 | REG_UDC_DevCFGR |= UDC_DevCFGR_SPD_LS; \ |
paul@43 | 3661 | } while (0) |
paul@43 | 3662 | |
paul@43 | 3663 | |
paul@43 | 3664 | #define __udc_set_dma_mode() ( REG_UDC_DevCR |= UDC_DevCR_DM ) |
paul@43 | 3665 | #define __udc_set_slave_mode() ( REG_UDC_DevCR &= ~UDC_DevCR_DM ) |
paul@43 | 3666 | #define __udc_set_big_endian() ( REG_UDC_DevCR |= UDC_DevCR_BE ) |
paul@43 | 3667 | #define __udc_set_little_endian() ( REG_UDC_DevCR &= ~UDC_DevCR_BE ) |
paul@43 | 3668 | #define __udc_generate_resume() ( REG_UDC_DevCR |= UDC_DevCR_RES ) |
paul@43 | 3669 | #define __udc_clear_resume() ( REG_UDC_DevCR &= ~UDC_DevCR_RES ) |
paul@43 | 3670 | |
paul@43 | 3671 | |
paul@43 | 3672 | #define __udc_get_enumarated_speed() ( REG_UDC_DevSR & UDC_DevSR_ENUMSPD_MASK ) |
paul@43 | 3673 | #define __udc_suspend_detected() ( REG_UDC_DevSR & UDC_DevSR_SUSP ) |
paul@43 | 3674 | #define __udc_get_alternate_setting() ( (REG_UDC_DevSR & UDC_DevSR_ALT_MASK) >> UDC_DevSR_ALT_BIT ) |
paul@43 | 3675 | #define __udc_get_interface_number() ( (REG_UDC_DevSR & UDC_DevSR_INTF_MASK) >> UDC_DevSR_INTF_BIT ) |
paul@43 | 3676 | #define __udc_get_config_number() ( (REG_UDC_DevSR & UDC_DevSR_CFG_MASK) >> UDC_DevSR_CFG_BIT ) |
paul@43 | 3677 | |
paul@43 | 3678 | |
paul@43 | 3679 | #define __udc_sof_detected(r) ( (r) & UDC_DevIntR_SOF ) |
paul@43 | 3680 | #define __udc_usb_suspend_detected(r) ( (r) & UDC_DevIntR_US ) |
paul@43 | 3681 | #define __udc_usb_reset_detected(r) ( (r) & UDC_DevIntR_UR ) |
paul@43 | 3682 | #define __udc_set_interface_detected(r) ( (r) & UDC_DevIntR_SI ) |
paul@43 | 3683 | #define __udc_set_config_detected(r) ( (r) & UDC_DevIntR_SC ) |
paul@43 | 3684 | |
paul@43 | 3685 | #define __udc_clear_sof() ( REG_UDC_DevIntR |= UDC_DevIntR_SOF ) |
paul@43 | 3686 | #define __udc_clear_usb_suspend() ( REG_UDC_DevIntR |= UDC_DevIntR_US ) |
paul@43 | 3687 | #define __udc_clear_usb_reset() ( REG_UDC_DevIntR |= UDC_DevIntR_UR ) |
paul@43 | 3688 | #define __udc_clear_set_interface() ( REG_UDC_DevIntR |= UDC_DevIntR_SI ) |
paul@43 | 3689 | #define __udc_clear_set_config() ( REG_UDC_DevIntR |= UDC_DevIntR_SC ) |
paul@43 | 3690 | |
paul@43 | 3691 | #define __udc_mask_sof() ( REG_UDC_DevIntMR |= UDC_DevIntR_SOF ) |
paul@43 | 3692 | #define __udc_mask_usb_suspend() ( REG_UDC_DevIntMR |= UDC_DevIntR_US ) |
paul@43 | 3693 | #define __udc_mask_usb_reset() ( REG_UDC_DevIntMR |= UDC_DevIntR_UR ) |
paul@43 | 3694 | #define __udc_mask_set_interface() ( REG_UDC_DevIntMR |= UDC_DevIntR_SI ) |
paul@43 | 3695 | #define __udc_mask_set_config() ( REG_UDC_DevIntMR |= UDC_DevIntR_SC ) |
paul@43 | 3696 | #define __udc_mask_all_dev_intrs() \ |
paul@43 | 3697 | ( REG_UDC_DevIntMR = UDC_DevIntR_SOF | UDC_DevIntR_US | \ |
paul@43 | 3698 | UDC_DevIntR_UR | UDC_DevIntR_SI | UDC_DevIntR_SC ) |
paul@43 | 3699 | |
paul@43 | 3700 | #define __udc_unmask_sof() ( REG_UDC_DevIntMR &= ~UDC_DevIntR_SOF ) |
paul@43 | 3701 | #define __udc_unmask_usb_suspend() ( REG_UDC_DevIntMR &= ~UDC_DevIntR_US ) |
paul@43 | 3702 | #define __udc_unmask_usb_reset() ( REG_UDC_DevIntMR &= ~UDC_DevIntR_UR ) |
paul@43 | 3703 | #define __udc_unmask_set_interface() ( REG_UDC_DevIntMR &= ~UDC_DevIntR_SI ) |
paul@43 | 3704 | #define __udc_unmask_set_config() ( REG_UDC_DevIntMR &= ~UDC_DevIntR_SC ) |
paul@43 | 3705 | #if 0 |
paul@43 | 3706 | #define __udc_unmask_all_dev_intrs() \ |
paul@43 | 3707 | ( REG_UDC_DevIntMR = ~(UDC_DevIntR_SOF | UDC_DevIntR_US | \ |
paul@43 | 3708 | UDC_DevIntR_UR | UDC_DevIntR_SI | UDC_DevIntR_SC) ) |
paul@43 | 3709 | #else |
paul@43 | 3710 | #define __udc_unmask_all_dev_intrs() \ |
paul@43 | 3711 | ( REG_UDC_DevIntMR = 0x00000000 ) |
paul@43 | 3712 | #endif |
paul@43 | 3713 | |
paul@43 | 3714 | |
paul@43 | 3715 | #define __udc_ep0out_irq_detected(epintr) \ |
paul@43 | 3716 | ( (((epintr) & UDC_EPIntR_OUTEP_MASK) >> (UDC_EPIntR_OUTEP_BIT + 0)) & 0x1 ) |
paul@43 | 3717 | #define __udc_ep5out_irq_detected(epintr) \ |
paul@43 | 3718 | ( (((epintr) & UDC_EPIntR_OUTEP_MASK) >> (UDC_EPIntR_OUTEP_BIT + 5)) & 0x1 ) |
paul@43 | 3719 | #define __udc_ep6out_irq_detected(epintr) \ |
paul@43 | 3720 | ( (((epintr) & UDC_EPIntR_OUTEP_MASK) >> (UDC_EPIntR_OUTEP_BIT + 6)) & 0x1 ) |
paul@43 | 3721 | #define __udc_ep7out_irq_detected(epintr) \ |
paul@43 | 3722 | ( (((epintr) & UDC_EPIntR_OUTEP_MASK) >> (UDC_EPIntR_OUTEP_BIT + 7)) & 0x1 ) |
paul@43 | 3723 | |
paul@43 | 3724 | #define __udc_ep0in_irq_detected(epintr) \ |
paul@43 | 3725 | ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 0)) & 0x1 ) |
paul@43 | 3726 | #define __udc_ep1in_irq_detected(epintr) \ |
paul@43 | 3727 | ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 1)) & 0x1 ) |
paul@43 | 3728 | #define __udc_ep2in_irq_detected(epintr) \ |
paul@43 | 3729 | ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 2)) & 0x1 ) |
paul@43 | 3730 | #define __udc_ep3in_irq_detected(epintr) \ |
paul@43 | 3731 | ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 3)) & 0x1 ) |
paul@43 | 3732 | #define __udc_ep4in_irq_detected(epintr) \ |
paul@43 | 3733 | ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 4)) & 0x1 ) |
paul@43 | 3734 | |
paul@43 | 3735 | |
paul@43 | 3736 | #define __udc_mask_ep0out_irq() \ |
paul@43 | 3737 | ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_OUTEP_BIT + 0)) ) |
paul@43 | 3738 | #define __udc_mask_ep5out_irq() \ |
paul@43 | 3739 | ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_OUTEP_BIT + 5)) ) |
paul@43 | 3740 | #define __udc_mask_ep6out_irq() \ |
paul@43 | 3741 | ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_OUTEP_BIT + 6)) ) |
paul@43 | 3742 | #define __udc_mask_ep7out_irq() \ |
paul@43 | 3743 | ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_OUTEP_BIT + 7)) ) |
paul@43 | 3744 | |
paul@43 | 3745 | #define __udc_unmask_ep0out_irq() \ |
paul@43 | 3746 | ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_OUTEP_BIT + 0)) ) |
paul@43 | 3747 | #define __udc_unmask_ep5out_irq() \ |
paul@43 | 3748 | ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_OUTEP_BIT + 5)) ) |
paul@43 | 3749 | #define __udc_unmask_ep6out_irq() \ |
paul@43 | 3750 | ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_OUTEP_BIT + 6)) ) |
paul@43 | 3751 | #define __udc_unmask_ep7out_irq() \ |
paul@43 | 3752 | ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_OUTEP_BIT + 7)) ) |
paul@43 | 3753 | |
paul@43 | 3754 | #define __udc_mask_ep0in_irq() \ |
paul@43 | 3755 | ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 0)) ) |
paul@43 | 3756 | #define __udc_mask_ep1in_irq() \ |
paul@43 | 3757 | ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 1)) ) |
paul@43 | 3758 | #define __udc_mask_ep2in_irq() \ |
paul@43 | 3759 | ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 2)) ) |
paul@43 | 3760 | #define __udc_mask_ep3in_irq() \ |
paul@43 | 3761 | ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 3)) ) |
paul@43 | 3762 | #define __udc_mask_ep4in_irq() \ |
paul@43 | 3763 | ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 4)) ) |
paul@43 | 3764 | |
paul@43 | 3765 | #define __udc_unmask_ep0in_irq() \ |
paul@43 | 3766 | ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 0)) ) |
paul@43 | 3767 | #define __udc_unmask_ep1in_irq() \ |
paul@43 | 3768 | ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 1)) ) |
paul@43 | 3769 | #define __udc_unmask_ep2in_irq() \ |
paul@43 | 3770 | ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 2)) ) |
paul@43 | 3771 | #define __udc_unmask_ep3in_irq() \ |
paul@43 | 3772 | ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 3)) ) |
paul@43 | 3773 | #define __udc_unmask_ep4in_irq() \ |
paul@43 | 3774 | ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 4)) ) |
paul@43 | 3775 | |
paul@43 | 3776 | #define __udc_mask_all_ep_intrs() \ |
paul@43 | 3777 | ( REG_UDC_EPIntMR = 0xffffffff ) |
paul@43 | 3778 | #define __udc_unmask_all_ep_intrs() \ |
paul@43 | 3779 | ( REG_UDC_EPIntMR = 0x00000000 ) |
paul@43 | 3780 | |
paul@43 | 3781 | |
paul@43 | 3782 | /* ep0 only CTRL, ep1 only INTR, ep2/3/5/6 only BULK, ep4/7 only ISO */ |
paul@43 | 3783 | #define __udc_config_endpoint_type() \ |
paul@43 | 3784 | do { \ |
paul@43 | 3785 | REG_UDC_EP0InCR = (REG_UDC_EP0InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_CTRL; \ |
paul@43 | 3786 | REG_UDC_EP0OutCR = (REG_UDC_EP0OutCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_CTRL; \ |
paul@43 | 3787 | REG_UDC_EP1InCR = (REG_UDC_EP1InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_INTR; \ |
paul@43 | 3788 | REG_UDC_EP2InCR = (REG_UDC_EP2InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_BULK; \ |
paul@43 | 3789 | REG_UDC_EP3InCR = (REG_UDC_EP3InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_BULK; \ |
paul@43 | 3790 | REG_UDC_EP4InCR = (REG_UDC_EP4InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_ISO; \ |
paul@43 | 3791 | REG_UDC_EP5OutCR = (REG_UDC_EP5OutCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_BULK; \ |
paul@43 | 3792 | REG_UDC_EP6OutCR = (REG_UDC_EP6OutCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_BULK; \ |
paul@43 | 3793 | REG_UDC_EP7OutCR = (REG_UDC_EP7OutCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_ISO; \ |
paul@43 | 3794 | } while (0) |
paul@43 | 3795 | |
paul@43 | 3796 | #define __udc_enable_ep0out_snoop_mode() ( REG_UDC_EP0OutCR |= UDC_EPCR_SN ) |
paul@43 | 3797 | #define __udc_enable_ep5out_snoop_mode() ( REG_UDC_EP5OutCR |= UDC_EPCR_SN ) |
paul@43 | 3798 | #define __udc_enable_ep6out_snoop_mode() ( REG_UDC_EP6OutCR |= UDC_EPCR_SN ) |
paul@43 | 3799 | #define __udc_enable_ep7out_snoop_mode() ( REG_UDC_EP7OutCR |= UDC_EPCR_SN ) |
paul@43 | 3800 | |
paul@43 | 3801 | #define __udc_disable_ep0out_snoop_mode() ( REG_UDC_EP0OutCR &= ~UDC_EPCR_SN ) |
paul@43 | 3802 | #define __udc_disable_ep5out_snoop_mode() ( REG_UDC_EP5OutCR &= ~UDC_EPCR_SN ) |
paul@43 | 3803 | #define __udc_disable_ep6out_snoop_mode() ( REG_UDC_EP6OutCR &= ~UDC_EPCR_SN ) |
paul@43 | 3804 | #define __udc_disable_ep7out_snoop_mode() ( REG_UDC_EP7OutCR &= ~UDC_EPCR_SN ) |
paul@43 | 3805 | |
paul@43 | 3806 | #define __udc_flush_ep0in_fifo() ( REG_UDC_EP0InCR |= UDC_EPCR_F ) |
paul@43 | 3807 | #define __udc_flush_ep1in_fifo() ( REG_UDC_EP1InCR |= UDC_EPCR_F ) |
paul@43 | 3808 | #define __udc_flush_ep2in_fifo() ( REG_UDC_EP2InCR |= UDC_EPCR_F ) |
paul@43 | 3809 | #define __udc_flush_ep3in_fifo() ( REG_UDC_EP3InCR |= UDC_EPCR_F ) |
paul@43 | 3810 | #define __udc_flush_ep4in_fifo() ( REG_UDC_EP4InCR |= UDC_EPCR_F ) |
paul@43 | 3811 | |
paul@43 | 3812 | #define __udc_unflush_ep0in_fifo() ( REG_UDC_EP0InCR &= ~UDC_EPCR_F ) |
paul@43 | 3813 | #define __udc_unflush_ep1in_fifo() ( REG_UDC_EP1InCR &= ~UDC_EPCR_F ) |
paul@43 | 3814 | #define __udc_unflush_ep2in_fifo() ( REG_UDC_EP2InCR &= ~UDC_EPCR_F ) |
paul@43 | 3815 | #define __udc_unflush_ep3in_fifo() ( REG_UDC_EP3InCR &= ~UDC_EPCR_F ) |
paul@43 | 3816 | #define __udc_unflush_ep4in_fifo() ( REG_UDC_EP4InCR &= ~UDC_EPCR_F ) |
paul@43 | 3817 | |
paul@43 | 3818 | #define __udc_enable_ep0in_stall() ( REG_UDC_EP0InCR |= UDC_EPCR_S ) |
paul@43 | 3819 | #define __udc_enable_ep0out_stall() ( REG_UDC_EP0OutCR |= UDC_EPCR_S ) |
paul@43 | 3820 | #define __udc_enable_ep1in_stall() ( REG_UDC_EP1InCR |= UDC_EPCR_S ) |
paul@43 | 3821 | #define __udc_enable_ep2in_stall() ( REG_UDC_EP2InCR |= UDC_EPCR_S ) |
paul@43 | 3822 | #define __udc_enable_ep3in_stall() ( REG_UDC_EP3InCR |= UDC_EPCR_S ) |
paul@43 | 3823 | #define __udc_enable_ep4in_stall() ( REG_UDC_EP4InCR |= UDC_EPCR_S ) |
paul@43 | 3824 | #define __udc_enable_ep5out_stall() ( REG_UDC_EP5OutCR |= UDC_EPCR_S ) |
paul@43 | 3825 | #define __udc_enable_ep6out_stall() ( REG_UDC_EP6OutCR |= UDC_EPCR_S ) |
paul@43 | 3826 | #define __udc_enable_ep7out_stall() ( REG_UDC_EP7OutCR |= UDC_EPCR_S ) |
paul@43 | 3827 | |
paul@43 | 3828 | #define __udc_disable_ep0in_stall() ( REG_UDC_EP0InCR &= ~UDC_EPCR_S ) |
paul@43 | 3829 | #define __udc_disable_ep0out_stall() ( REG_UDC_EP0OutCR &= ~UDC_EPCR_S ) |
paul@43 | 3830 | #define __udc_disable_ep1in_stall() ( REG_UDC_EP1InCR &= ~UDC_EPCR_S ) |
paul@43 | 3831 | #define __udc_disable_ep2in_stall() ( REG_UDC_EP2InCR &= ~UDC_EPCR_S ) |
paul@43 | 3832 | #define __udc_disable_ep3in_stall() ( REG_UDC_EP3InCR &= ~UDC_EPCR_S ) |
paul@43 | 3833 | #define __udc_disable_ep4in_stall() ( REG_UDC_EP4InCR &= ~UDC_EPCR_S ) |
paul@43 | 3834 | #define __udc_disable_ep5out_stall() ( REG_UDC_EP5OutCR &= ~UDC_EPCR_S ) |
paul@43 | 3835 | #define __udc_disable_ep6out_stall() ( REG_UDC_EP6OutCR &= ~UDC_EPCR_S ) |
paul@43 | 3836 | #define __udc_disable_ep7out_stall() ( REG_UDC_EP7OutCR &= ~UDC_EPCR_S ) |
paul@43 | 3837 | |
paul@43 | 3838 | |
paul@43 | 3839 | #define __udc_ep0out_packet_size() \ |
paul@43 | 3840 | ( (REG_UDC_EP0OutSR & UDC_EPSR_RXPKTSIZE_MASK) >> UDC_EPSR_RXPKTSIZE_BIT ) |
paul@43 | 3841 | #define __udc_ep5out_packet_size() \ |
paul@43 | 3842 | ( (REG_UDC_EP5OutSR & UDC_EPSR_RXPKTSIZE_MASK) >> UDC_EPSR_RXPKTSIZE_BIT ) |
paul@43 | 3843 | #define __udc_ep6out_packet_size() \ |
paul@43 | 3844 | ( (REG_UDC_EP6OutSR & UDC_EPSR_RXPKTSIZE_MASK) >> UDC_EPSR_RXPKTSIZE_BIT ) |
paul@43 | 3845 | #define __udc_ep7out_packet_size() \ |
paul@43 | 3846 | ( (REG_UDC_EP7OutSR & UDC_EPSR_RXPKTSIZE_MASK) >> UDC_EPSR_RXPKTSIZE_BIT ) |
paul@43 | 3847 | |
paul@43 | 3848 | #define __udc_ep0in_received_intoken() ( (REG_UDC_EP0InSR & UDC_EPSR_IN) ) |
paul@43 | 3849 | #define __udc_ep1in_received_intoken() ( (REG_UDC_EP1InSR & UDC_EPSR_IN) ) |
paul@43 | 3850 | #define __udc_ep2in_received_intoken() ( (REG_UDC_EP2InSR & UDC_EPSR_IN) ) |
paul@43 | 3851 | #define __udc_ep3in_received_intoken() ( (REG_UDC_EP3InSR & UDC_EPSR_IN) ) |
paul@43 | 3852 | #define __udc_ep4in_received_intoken() ( (REG_UDC_EP4InSR & UDC_EPSR_IN) ) |
paul@43 | 3853 | |
paul@43 | 3854 | #define __udc_ep0out_received_none() \ |
paul@43 | 3855 | ( (REG_UDC_EP0OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_NONE ) |
paul@43 | 3856 | #define __udc_ep0out_received_data() \ |
paul@43 | 3857 | ( (REG_UDC_EP0OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVDATA ) |
paul@43 | 3858 | #define __udc_ep0out_received_setup() \ |
paul@43 | 3859 | ( (REG_UDC_EP0OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVSETUP ) |
paul@43 | 3860 | |
paul@43 | 3861 | #define __udc_ep5out_received_none() \ |
paul@43 | 3862 | ( (REG_UDC_EP5OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_NONE ) |
paul@43 | 3863 | #define __udc_ep5out_received_data() \ |
paul@43 | 3864 | ( (REG_UDC_EP5OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVDATA ) |
paul@43 | 3865 | #define __udc_ep5out_received_setup() \ |
paul@43 | 3866 | ( (REG_UDC_EP5OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVSETUP ) |
paul@43 | 3867 | |
paul@43 | 3868 | #define __udc_ep6out_received_none() \ |
paul@43 | 3869 | ( (REG_UDC_EP6OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_NONE ) |
paul@43 | 3870 | #define __udc_ep6out_received_data() \ |
paul@43 | 3871 | ( (REG_UDC_EP6OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVDATA ) |
paul@43 | 3872 | #define __udc_ep6out_received_setup() \ |
paul@43 | 3873 | ( (REG_UDC_EP6OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVSETUP ) |
paul@43 | 3874 | |
paul@43 | 3875 | #define __udc_ep7out_received_none() \ |
paul@43 | 3876 | ( (REG_UDC_EP7OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_NONE ) |
paul@43 | 3877 | #define __udc_ep7out_received_data() \ |
paul@43 | 3878 | ( (REG_UDC_EP7OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVDATA ) |
paul@43 | 3879 | #define __udc_ep7out_received_setup() \ |
paul@43 | 3880 | ( (REG_UDC_EP7OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVSETUP ) |
paul@43 | 3881 | |
paul@43 | 3882 | /* ep7out ISO only */ |
paul@43 | 3883 | #define __udc_ep7out_get_pid() \ |
paul@43 | 3884 | ( (REG_UDC_EP7OutSR & UDC_EPSR_PID_MASK) >> UDC_EPSR_PID_BIT ) |
paul@43 | 3885 | |
paul@43 | 3886 | |
paul@43 | 3887 | #define __udc_ep0in_set_buffer_size(n) ( REG_UDC_EP0InBSR = (n) ) |
paul@43 | 3888 | #define __udc_ep1in_set_buffer_size(n) ( REG_UDC_EP1InBSR = (n) ) |
paul@43 | 3889 | #define __udc_ep2in_set_buffer_size(n) ( REG_UDC_EP2InBSR = (n) ) |
paul@43 | 3890 | #define __udc_ep3in_set_buffer_size(n) ( REG_UDC_EP3InBSR = (n) ) |
paul@43 | 3891 | #define __udc_ep4in_set_buffer_size(n) ( REG_UDC_EP4InBSR = (n) ) |
paul@43 | 3892 | |
paul@43 | 3893 | #define __udc_ep0out_get_frame_number(n) ( UDC_EP0OutPFNR ) |
paul@43 | 3894 | #define __udc_ep5out_get_frame_number(n) ( UDC_EP5OutPFNR ) |
paul@43 | 3895 | #define __udc_ep6out_get_frame_number(n) ( UDC_EP6OutPFNR ) |
paul@43 | 3896 | #define __udc_ep7out_get_frame_number(n) ( UDC_EP7OutPFNR ) |
paul@43 | 3897 | |
paul@43 | 3898 | |
paul@43 | 3899 | #define __udc_ep0in_set_max_packet_size(n) ( REG_UDC_EP0InMPSR = (n) ) |
paul@43 | 3900 | #define __udc_ep0out_set_max_packet_size(n) ( REG_UDC_EP0OutMPSR = (n) ) |
paul@43 | 3901 | #define __udc_ep1in_set_max_packet_size(n) ( REG_UDC_EP1InMPSR = (n) ) |
paul@43 | 3902 | #define __udc_ep2in_set_max_packet_size(n) ( REG_UDC_EP2InMPSR = (n) ) |
paul@43 | 3903 | #define __udc_ep3in_set_max_packet_size(n) ( REG_UDC_EP3InMPSR = (n) ) |
paul@43 | 3904 | #define __udc_ep4in_set_max_packet_size(n) ( REG_UDC_EP4InMPSR = (n) ) |
paul@43 | 3905 | #define __udc_ep5out_set_max_packet_size(n) ( REG_UDC_EP5OutMPSR = (n) ) |
paul@43 | 3906 | #define __udc_ep6out_set_max_packet_size(n) ( REG_UDC_EP6OutMPSR = (n) ) |
paul@43 | 3907 | #define __udc_ep7out_set_max_packet_size(n) ( REG_UDC_EP7OutMPSR = (n) ) |
paul@43 | 3908 | |
paul@43 | 3909 | /* set to 0xFFFF for UDC */ |
paul@43 | 3910 | #define __udc_set_setup_command_address(n) ( REG_UDC_STCMAR = (n) ) |
paul@43 | 3911 | |
paul@43 | 3912 | /* Init and configure EPxInfR(x=0,1,2,3,4,5,6,7) |
paul@43 | 3913 | * c: Configuration number to which this endpoint belongs |
paul@43 | 3914 | * i: Interface number to which this endpoint belongs |
paul@43 | 3915 | * a: Alternate setting to which this endpoint belongs |
paul@43 | 3916 | * p: max Packet size of this endpoint |
paul@43 | 3917 | */ |
paul@43 | 3918 | |
paul@43 | 3919 | #define __udc_ep0info_init(c,i,a,p) \ |
paul@43 | 3920 | do { \ |
paul@43 | 3921 | REG_UDC_EP0InfR &= ~UDC_EPInfR_MPS_MASK; \ |
paul@43 | 3922 | REG_UDC_EP0InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ |
paul@43 | 3923 | REG_UDC_EP0InfR &= ~UDC_EPInfR_ALTS_MASK; \ |
paul@43 | 3924 | REG_UDC_EP0InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ |
paul@43 | 3925 | REG_UDC_EP0InfR &= ~UDC_EPInfR_IFN_MASK; \ |
paul@43 | 3926 | REG_UDC_EP0InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ |
paul@43 | 3927 | REG_UDC_EP0InfR &= ~UDC_EPInfR_CGN_MASK; \ |
paul@43 | 3928 | REG_UDC_EP0InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ |
paul@43 | 3929 | REG_UDC_EP0InfR &= ~UDC_EPInfR_EPT_MASK; \ |
paul@43 | 3930 | REG_UDC_EP0InfR |= UDC_EPInfR_EPT_CTRL; \ |
paul@43 | 3931 | REG_UDC_EP0InfR &= ~UDC_EPInfR_EPD; \ |
paul@43 | 3932 | REG_UDC_EP0InfR |= UDC_EPInfR_EPD_OUT; \ |
paul@43 | 3933 | REG_UDC_EP0InfR &= ~UDC_EPInfR_EPN_MASK; \ |
paul@43 | 3934 | REG_UDC_EP0InfR |= (0 << UDC_EPInfR_EPN_BIT); \ |
paul@43 | 3935 | } while (0) |
paul@43 | 3936 | |
paul@43 | 3937 | #define __udc_ep1info_init(c,i,a,p) \ |
paul@43 | 3938 | do { \ |
paul@43 | 3939 | REG_UDC_EP1InfR &= ~UDC_EPInfR_MPS_MASK; \ |
paul@43 | 3940 | REG_UDC_EP1InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ |
paul@43 | 3941 | REG_UDC_EP1InfR &= ~UDC_EPInfR_ALTS_MASK; \ |
paul@43 | 3942 | REG_UDC_EP1InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ |
paul@43 | 3943 | REG_UDC_EP1InfR &= ~UDC_EPInfR_IFN_MASK; \ |
paul@43 | 3944 | REG_UDC_EP1InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ |
paul@43 | 3945 | REG_UDC_EP1InfR &= ~UDC_EPInfR_CGN_MASK; \ |
paul@43 | 3946 | REG_UDC_EP1InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ |
paul@43 | 3947 | REG_UDC_EP1InfR &= ~UDC_EPInfR_EPT_MASK; \ |
paul@43 | 3948 | REG_UDC_EP1InfR |= UDC_EPInfR_EPT_INTR; \ |
paul@43 | 3949 | REG_UDC_EP1InfR &= ~UDC_EPInfR_EPD; \ |
paul@43 | 3950 | REG_UDC_EP1InfR |= UDC_EPInfR_EPD_IN; \ |
paul@43 | 3951 | REG_UDC_EP1InfR &= ~UDC_EPInfR_EPN_MASK; \ |
paul@43 | 3952 | REG_UDC_EP1InfR |= (1 << UDC_EPInfR_EPN_BIT); \ |
paul@43 | 3953 | } while (0) |
paul@43 | 3954 | |
paul@43 | 3955 | #define __udc_ep2info_init(c,i,a,p) \ |
paul@43 | 3956 | do { \ |
paul@43 | 3957 | REG_UDC_EP2InfR &= ~UDC_EPInfR_MPS_MASK; \ |
paul@43 | 3958 | REG_UDC_EP2InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ |
paul@43 | 3959 | REG_UDC_EP2InfR &= ~UDC_EPInfR_ALTS_MASK; \ |
paul@43 | 3960 | REG_UDC_EP2InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ |
paul@43 | 3961 | REG_UDC_EP2InfR &= ~UDC_EPInfR_IFN_MASK; \ |
paul@43 | 3962 | REG_UDC_EP2InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ |
paul@43 | 3963 | REG_UDC_EP2InfR &= ~UDC_EPInfR_CGN_MASK; \ |
paul@43 | 3964 | REG_UDC_EP2InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ |
paul@43 | 3965 | REG_UDC_EP2InfR &= ~UDC_EPInfR_EPT_MASK; \ |
paul@43 | 3966 | REG_UDC_EP2InfR |= UDC_EPInfR_EPT_BULK; \ |
paul@43 | 3967 | REG_UDC_EP2InfR &= ~UDC_EPInfR_EPD; \ |
paul@43 | 3968 | REG_UDC_EP2InfR |= UDC_EPInfR_EPD_IN; \ |
paul@43 | 3969 | REG_UDC_EP2InfR &= ~UDC_EPInfR_EPN_MASK; \ |
paul@43 | 3970 | REG_UDC_EP2InfR |= (2 << UDC_EPInfR_EPN_BIT); \ |
paul@43 | 3971 | } while (0) |
paul@43 | 3972 | |
paul@43 | 3973 | #define __udc_ep3info_init(c,i,a,p) \ |
paul@43 | 3974 | do { \ |
paul@43 | 3975 | REG_UDC_EP3InfR &= ~UDC_EPInfR_MPS_MASK; \ |
paul@43 | 3976 | REG_UDC_EP3InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ |
paul@43 | 3977 | REG_UDC_EP3InfR &= ~UDC_EPInfR_ALTS_MASK; \ |
paul@43 | 3978 | REG_UDC_EP3InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ |
paul@43 | 3979 | REG_UDC_EP3InfR &= ~UDC_EPInfR_IFN_MASK; \ |
paul@43 | 3980 | REG_UDC_EP3InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ |
paul@43 | 3981 | REG_UDC_EP3InfR &= ~UDC_EPInfR_CGN_MASK; \ |
paul@43 | 3982 | REG_UDC_EP3InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ |
paul@43 | 3983 | REG_UDC_EP3InfR &= ~UDC_EPInfR_EPT_MASK; \ |
paul@43 | 3984 | REG_UDC_EP3InfR |= UDC_EPInfR_EPT_BULK; \ |
paul@43 | 3985 | REG_UDC_EP3InfR &= ~UDC_EPInfR_EPD; \ |
paul@43 | 3986 | REG_UDC_EP3InfR |= UDC_EPInfR_EPD_IN; \ |
paul@43 | 3987 | REG_UDC_EP3InfR &= ~UDC_EPInfR_EPN_MASK; \ |
paul@43 | 3988 | REG_UDC_EP3InfR |= (3 << UDC_EPInfR_EPN_BIT); \ |
paul@43 | 3989 | } while (0) |
paul@43 | 3990 | |
paul@43 | 3991 | #define __udc_ep4info_init(c,i,a,p) \ |
paul@43 | 3992 | do { \ |
paul@43 | 3993 | REG_UDC_EP4InfR &= ~UDC_EPInfR_MPS_MASK; \ |
paul@43 | 3994 | REG_UDC_EP4InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ |
paul@43 | 3995 | REG_UDC_EP4InfR &= ~UDC_EPInfR_ALTS_MASK; \ |
paul@43 | 3996 | REG_UDC_EP4InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ |
paul@43 | 3997 | REG_UDC_EP4InfR &= ~UDC_EPInfR_IFN_MASK; \ |
paul@43 | 3998 | REG_UDC_EP4InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ |
paul@43 | 3999 | REG_UDC_EP4InfR &= ~UDC_EPInfR_CGN_MASK; \ |
paul@43 | 4000 | REG_UDC_EP4InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ |
paul@43 | 4001 | REG_UDC_EP4InfR &= ~UDC_EPInfR_EPT_MASK; \ |
paul@43 | 4002 | REG_UDC_EP4InfR |= UDC_EPInfR_EPT_ISO; \ |
paul@43 | 4003 | REG_UDC_EP4InfR &= ~UDC_EPInfR_EPD; \ |
paul@43 | 4004 | REG_UDC_EP4InfR |= UDC_EPInfR_EPD_IN; \ |
paul@43 | 4005 | REG_UDC_EP4InfR &= ~UDC_EPInfR_EPN_MASK; \ |
paul@43 | 4006 | REG_UDC_EP4InfR |= (4 << UDC_EPInfR_EPN_BIT); \ |
paul@43 | 4007 | } while (0) |
paul@43 | 4008 | |
paul@43 | 4009 | #define __udc_ep5info_init(c,i,a,p) \ |
paul@43 | 4010 | do { \ |
paul@43 | 4011 | REG_UDC_EP5InfR &= ~UDC_EPInfR_MPS_MASK; \ |
paul@43 | 4012 | REG_UDC_EP5InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ |
paul@43 | 4013 | REG_UDC_EP5InfR &= ~UDC_EPInfR_ALTS_MASK; \ |
paul@43 | 4014 | REG_UDC_EP5InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ |
paul@43 | 4015 | REG_UDC_EP5InfR &= ~UDC_EPInfR_IFN_MASK; \ |
paul@43 | 4016 | REG_UDC_EP5InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ |
paul@43 | 4017 | REG_UDC_EP5InfR &= ~UDC_EPInfR_CGN_MASK; \ |
paul@43 | 4018 | REG_UDC_EP5InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ |
paul@43 | 4019 | REG_UDC_EP5InfR &= ~UDC_EPInfR_EPT_MASK; \ |
paul@43 | 4020 | REG_UDC_EP5InfR |= UDC_EPInfR_EPT_BULK; \ |
paul@43 | 4021 | REG_UDC_EP5InfR &= ~UDC_EPInfR_EPD; \ |
paul@43 | 4022 | REG_UDC_EP5InfR |= UDC_EPInfR_EPD_OUT; \ |
paul@43 | 4023 | REG_UDC_EP5InfR &= ~UDC_EPInfR_EPN_MASK; \ |
paul@43 | 4024 | REG_UDC_EP5InfR |= (5 << UDC_EPInfR_EPN_BIT); \ |
paul@43 | 4025 | } while (0) |
paul@43 | 4026 | |
paul@43 | 4027 | #define __udc_ep6info_init(c,i,a,p) \ |
paul@43 | 4028 | do { \ |
paul@43 | 4029 | REG_UDC_EP6InfR &= ~UDC_EPInfR_MPS_MASK; \ |
paul@43 | 4030 | REG_UDC_EP6InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ |
paul@43 | 4031 | REG_UDC_EP6InfR &= ~UDC_EPInfR_ALTS_MASK; \ |
paul@43 | 4032 | REG_UDC_EP6InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ |
paul@43 | 4033 | REG_UDC_EP6InfR &= ~UDC_EPInfR_IFN_MASK; \ |
paul@43 | 4034 | REG_UDC_EP6InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ |
paul@43 | 4035 | REG_UDC_EP6InfR &= ~UDC_EPInfR_CGN_MASK; \ |
paul@43 | 4036 | REG_UDC_EP6InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ |
paul@43 | 4037 | REG_UDC_EP6InfR &= ~UDC_EPInfR_EPT_MASK; \ |
paul@43 | 4038 | REG_UDC_EP6InfR |= UDC_EPInfR_EPT_BULK; \ |
paul@43 | 4039 | REG_UDC_EP6InfR &= ~UDC_EPInfR_EPD; \ |
paul@43 | 4040 | REG_UDC_EP6InfR |= UDC_EPInfR_EPD_OUT; \ |
paul@43 | 4041 | REG_UDC_EP6InfR &= ~UDC_EPInfR_EPN_MASK; \ |
paul@43 | 4042 | REG_UDC_EP6InfR |= (6 << UDC_EPInfR_EPN_BIT); \ |
paul@43 | 4043 | } while (0) |
paul@43 | 4044 | |
paul@43 | 4045 | #define __udc_ep7info_init(c,i,a,p) \ |
paul@43 | 4046 | do { \ |
paul@43 | 4047 | REG_UDC_EP7InfR &= ~UDC_EPInfR_MPS_MASK; \ |
paul@43 | 4048 | REG_UDC_EP7InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ |
paul@43 | 4049 | REG_UDC_EP7InfR &= ~UDC_EPInfR_ALTS_MASK; \ |
paul@43 | 4050 | REG_UDC_EP7InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ |
paul@43 | 4051 | REG_UDC_EP7InfR &= ~UDC_EPInfR_IFN_MASK; \ |
paul@43 | 4052 | REG_UDC_EP7InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ |
paul@43 | 4053 | REG_UDC_EP7InfR &= ~UDC_EPInfR_CGN_MASK; \ |
paul@43 | 4054 | REG_UDC_EP7InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ |
paul@43 | 4055 | REG_UDC_EP7InfR &= ~UDC_EPInfR_EPT_MASK; \ |
paul@43 | 4056 | REG_UDC_EP7InfR |= UDC_EPInfR_EPT_ISO; \ |
paul@43 | 4057 | REG_UDC_EP7InfR &= ~UDC_EPInfR_EPD; \ |
paul@43 | 4058 | REG_UDC_EP7InfR |= UDC_EPInfR_EPD_OUT; \ |
paul@43 | 4059 | REG_UDC_EP7InfR &= ~UDC_EPInfR_EPN_MASK; \ |
paul@43 | 4060 | REG_UDC_EP7InfR |= (7 << UDC_EPInfR_EPN_BIT); \ |
paul@43 | 4061 | } while (0) |
paul@43 | 4062 | |
paul@43 | 4063 | |
paul@43 | 4064 | /*************************************************************************** |
paul@43 | 4065 | * DMAC |
paul@43 | 4066 | ***************************************************************************/ |
paul@43 | 4067 | |
paul@43 | 4068 | /* n is the DMA channel (0 - 7) */ |
paul@43 | 4069 | |
paul@43 | 4070 | #define __dmac_enable_all_channels() \ |
paul@43 | 4071 | ( REG_DMAC_DMACR |= DMAC_DMACR_DME | DMAC_DMACR_PR_ROUNDROBIN ) |
paul@43 | 4072 | #define __dmac_disable_all_channels() \ |
paul@43 | 4073 | ( REG_DMAC_DMACR &= ~DMAC_DMACR_DME ) |
paul@43 | 4074 | |
paul@43 | 4075 | /* p=0,1,2,3 */ |
paul@43 | 4076 | #define __dmac_set_priority(p) \ |
paul@43 | 4077 | do { \ |
paul@43 | 4078 | REG_DMAC_DMACR &= ~DMAC_DMACR_PR_MASK; \ |
paul@43 | 4079 | REG_DMAC_DMACR |= ((p) << DMAC_DMACR_PR_BIT); \ |
paul@43 | 4080 | } while (0) |
paul@43 | 4081 | |
paul@43 | 4082 | #define __dmac_test_halt_error() ( REG_DMAC_DMACR & DMAC_DMACR_HTR ) |
paul@43 | 4083 | #define __dmac_test_addr_error() ( REG_DMAC_DMACR & DMAC_DMACR_AER ) |
paul@43 | 4084 | |
paul@43 | 4085 | #define __dmac_enable_channel(n) \ |
paul@43 | 4086 | ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_CHDE ) |
paul@43 | 4087 | #define __dmac_disable_channel(n) \ |
paul@43 | 4088 | ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_CHDE ) |
paul@43 | 4089 | #define __dmac_channel_enabled(n) \ |
paul@43 | 4090 | ( REG_DMAC_DCCSR(n) & DMAC_DCCSR_CHDE ) |
paul@43 | 4091 | |
paul@43 | 4092 | #define __dmac_channel_enable_irq(n) \ |
paul@43 | 4093 | ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_TCIE ) |
paul@43 | 4094 | #define __dmac_channel_disable_irq(n) \ |
paul@43 | 4095 | ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TCIE ) |
paul@43 | 4096 | |
paul@43 | 4097 | #define __dmac_channel_transmit_halt_detected(n) \ |
paul@43 | 4098 | ( REG_DMAC_DCCSR(n) & DMAC_DCCSR_HLT ) |
paul@43 | 4099 | #define __dmac_channel_transmit_end_detected(n) \ |
paul@43 | 4100 | ( REG_DMAC_DCCSR(n) & DMAC_DCCSR_TC ) |
paul@43 | 4101 | #define __dmac_channel_address_error_detected(n) \ |
paul@43 | 4102 | ( REG_DMAC_DCCSR(n) & DMAC_DCCSR_AR ) |
paul@43 | 4103 | |
paul@43 | 4104 | #define __dmac_channel_clear_transmit_halt(n) \ |
paul@43 | 4105 | ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT ) |
paul@43 | 4106 | #define __dmac_channel_clear_transmit_end(n) \ |
paul@43 | 4107 | ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TC ) |
paul@43 | 4108 | #define __dmac_channel_clear_address_error(n) \ |
paul@43 | 4109 | ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_AR ) |
paul@43 | 4110 | |
paul@43 | 4111 | #define __dmac_channel_set_single_mode(n) \ |
paul@43 | 4112 | ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TM ) |
paul@43 | 4113 | #define __dmac_channel_set_block_mode(n) \ |
paul@43 | 4114 | ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_TM ) |
paul@43 | 4115 | |
paul@43 | 4116 | #define __dmac_channel_set_transfer_unit_32bit(n) \ |
paul@43 | 4117 | do { \ |
paul@43 | 4118 | REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DS_MASK; \ |
paul@43 | 4119 | REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DS_32b; \ |
paul@43 | 4120 | } while (0) |
paul@43 | 4121 | |
paul@43 | 4122 | #define __dmac_channel_set_transfer_unit_16bit(n) \ |
paul@43 | 4123 | do { \ |
paul@43 | 4124 | REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DS_MASK; \ |
paul@43 | 4125 | REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DS_16b; \ |
paul@43 | 4126 | } while (0) |
paul@43 | 4127 | |
paul@43 | 4128 | #define __dmac_channel_set_transfer_unit_8bit(n) \ |
paul@43 | 4129 | do { \ |
paul@43 | 4130 | REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DS_MASK; \ |
paul@43 | 4131 | REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DS_8b; \ |
paul@43 | 4132 | } while (0) |
paul@43 | 4133 | |
paul@43 | 4134 | #define __dmac_channel_set_transfer_unit_16byte(n) \ |
paul@43 | 4135 | do { \ |
paul@43 | 4136 | REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DS_MASK; \ |
paul@43 | 4137 | REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DS_16B; \ |
paul@43 | 4138 | } while (0) |
paul@43 | 4139 | |
paul@43 | 4140 | #define __dmac_channel_set_transfer_unit_32byte(n) \ |
paul@43 | 4141 | do { \ |
paul@43 | 4142 | REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DS_MASK; \ |
paul@43 | 4143 | REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DS_32B; \ |
paul@43 | 4144 | } while (0) |
paul@43 | 4145 | |
paul@43 | 4146 | /* w=8,16,32 */ |
paul@43 | 4147 | #define __dmac_channel_set_dest_port_width(n,w) \ |
paul@43 | 4148 | do { \ |
paul@43 | 4149 | REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DWDH_MASK; \ |
paul@43 | 4150 | REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DWDH_##w; \ |
paul@43 | 4151 | } while (0) |
paul@43 | 4152 | |
paul@43 | 4153 | /* w=8,16,32 */ |
paul@43 | 4154 | #define __dmac_channel_set_src_port_width(n,w) \ |
paul@43 | 4155 | do { \ |
paul@43 | 4156 | REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_SWDH_MASK; \ |
paul@43 | 4157 | REG_DMAC_DCCSR(n) |= DMAC_DCCSR_SWDH_##w; \ |
paul@43 | 4158 | } while (0) |
paul@43 | 4159 | |
paul@43 | 4160 | /* v=0-15 */ |
paul@43 | 4161 | #define __dmac_channel_set_rdil(n,v) \ |
paul@43 | 4162 | do { \ |
paul@43 | 4163 | REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_RDIL_MASK; \ |
paul@43 | 4164 | REG_DMAC_DCCSR(n) |= ((v) << DMAC_DCCSR_RDIL_BIT); \ |
paul@43 | 4165 | } while (0) |
paul@43 | 4166 | |
paul@43 | 4167 | #define __dmac_channel_dest_addr_fixed(n) \ |
paul@43 | 4168 | ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DAM ) |
paul@43 | 4169 | #define __dmac_channel_dest_addr_increment(n) \ |
paul@43 | 4170 | ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DAM ) |
paul@43 | 4171 | |
paul@43 | 4172 | #define __dmac_channel_src_addr_fixed(n) \ |
paul@43 | 4173 | ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_SAM ) |
paul@43 | 4174 | #define __dmac_channel_src_addr_increment(n) \ |
paul@43 | 4175 | ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_SAM ) |
paul@43 | 4176 | |
paul@43 | 4177 | #define __dmac_channel_set_eop_high(n) \ |
paul@43 | 4178 | ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_EOPM ) |
paul@43 | 4179 | #define __dmac_channel_set_eop_low(n) \ |
paul@43 | 4180 | ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_EOPM ) |
paul@43 | 4181 | |
paul@43 | 4182 | #define __dmac_channel_set_erdm(n,m) \ |
paul@43 | 4183 | do { \ |
paul@43 | 4184 | REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_SWDH_MASK; \ |
paul@43 | 4185 | REG_DMAC_DCCSR(n) |= ((m) << DMAC_DCCSR_ERDM_BIT); \ |
paul@43 | 4186 | } while (0) |
paul@43 | 4187 | |
paul@43 | 4188 | #define __dmac_channel_set_eackm(n) \ |
paul@43 | 4189 | ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_EACKM ) |
paul@43 | 4190 | #define __dmac_channel_clear_eackm(n) \ |
paul@43 | 4191 | ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_EACKM ) |
paul@43 | 4192 | |
paul@43 | 4193 | #define __dmac_channel_set_eacks(n) \ |
paul@43 | 4194 | ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_EACKS ) |
paul@43 | 4195 | #define __dmac_channel_clear_eacks(n) \ |
paul@43 | 4196 | ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_EACKS ) |
paul@43 | 4197 | |
paul@43 | 4198 | |
paul@43 | 4199 | #define __dmac_channel_irq_detected(n) \ |
paul@43 | 4200 | ( REG_DMAC_DCCSR(n) & (DMAC_DCCSR_TC | DMAC_DCCSR_AR) ) |
paul@43 | 4201 | |
paul@43 | 4202 | static __inline__ int __dmac_get_irq(void) |
paul@43 | 4203 | { |
paul@43 | 4204 | int i; |
paul@43 | 4205 | for (i=0;i<NUM_DMA;i++) |
paul@43 | 4206 | if (__dmac_channel_irq_detected(i)) |
paul@43 | 4207 | return i; |
paul@43 | 4208 | return -1; |
paul@43 | 4209 | } |
paul@43 | 4210 | |
paul@43 | 4211 | /*************************************************************************** |
paul@43 | 4212 | * AIC (AC'97 & I2S Controller) |
paul@43 | 4213 | ***************************************************************************/ |
paul@43 | 4214 | |
paul@43 | 4215 | #define __aic_enable() ( REG_AIC_FR |= AIC_FR_ENB ) |
paul@43 | 4216 | #define __aic_disable() ( REG_AIC_FR &= ~AIC_FR_ENB ) |
paul@43 | 4217 | #define __aic_reset() ( REG_AIC_FR |= AIC_FR_RST ) |
paul@43 | 4218 | #define __aic_select_ac97() ( REG_AIC_FR &= ~AIC_FR_AUSEL ) |
paul@43 | 4219 | #define __aic_select_i2s() ( REG_AIC_FR |= AIC_FR_AUSEL ) |
paul@43 | 4220 | |
paul@43 | 4221 | #define __i2s_as_master() ( REG_AIC_FR |= AIC_FR_BCKD | AIC_FR_SYNCD ) |
paul@43 | 4222 | #define __i2s_as_slave() ( REG_AIC_FR &= ~(AIC_FR_BCKD | AIC_FR_SYNCD) ) |
paul@43 | 4223 | |
paul@43 | 4224 | #define __aic_set_transmit_trigger(n) \ |
paul@43 | 4225 | do { \ |
paul@43 | 4226 | REG_AIC_FR &= ~AIC_FR_TFTH_MASK; \ |
paul@43 | 4227 | REG_AIC_FR |= ((n) << AIC_FR_TFTH_BIT); \ |
paul@43 | 4228 | } while(0) |
paul@43 | 4229 | |
paul@43 | 4230 | #define __aic_set_receive_trigger(n) \ |
paul@43 | 4231 | do { \ |
paul@43 | 4232 | REG_AIC_FR &= ~AIC_FR_RFTH_MASK; \ |
paul@43 | 4233 | REG_AIC_FR |= ((n) << AIC_FR_RFTH_BIT); \ |
paul@43 | 4234 | } while(0) |
paul@43 | 4235 | |
paul@43 | 4236 | #define __aic_enable_record() ( REG_AIC_CR |= AIC_CR_EREC ) |
paul@43 | 4237 | #define __aic_disable_record() ( REG_AIC_CR &= ~AIC_CR_EREC ) |
paul@43 | 4238 | #define __aic_enable_replay() ( REG_AIC_CR |= AIC_CR_ERPL ) |
paul@43 | 4239 | #define __aic_disable_replay() ( REG_AIC_CR &= ~AIC_CR_ERPL ) |
paul@43 | 4240 | #define __aic_enable_loopback() ( REG_AIC_CR |= AIC_CR_ENLBF ) |
paul@43 | 4241 | #define __aic_disable_loopback() ( REG_AIC_CR &= ~AIC_CR_ENLBF ) |
paul@43 | 4242 | |
paul@43 | 4243 | #define __aic_flush_fifo() ( REG_AIC_CR |= AIC_CR_FLUSH ) |
paul@43 | 4244 | #define __aic_unflush_fifo() ( REG_AIC_CR &= ~AIC_CR_FLUSH ) |
paul@43 | 4245 | |
paul@43 | 4246 | #define __aic_enable_transmit_intr() \ |
paul@43 | 4247 | ( REG_AIC_CR |= (AIC_CR_ETFS | AIC_CR_ETUR) ) |
paul@43 | 4248 | #define __aic_disable_transmit_intr() \ |
paul@43 | 4249 | ( REG_AIC_CR &= ~(AIC_CR_ETFS | AIC_CR_ETUR) ) |
paul@43 | 4250 | #define __aic_enable_receive_intr() \ |
paul@43 | 4251 | ( REG_AIC_CR |= (AIC_CR_ERFS | AIC_CR_EROR) ) |
paul@43 | 4252 | #define __aic_disable_receive_intr() \ |
paul@43 | 4253 | ( REG_AIC_CR &= ~(AIC_CR_ERFS | AIC_CR_EROR) ) |
paul@43 | 4254 | |
paul@43 | 4255 | #define __aic_enable_transmit_dma() ( REG_AIC_CR |= AIC_CR_TDMS ) |
paul@43 | 4256 | #define __aic_disable_transmit_dma() ( REG_AIC_CR &= ~AIC_CR_TDMS ) |
paul@43 | 4257 | #define __aic_enable_receive_dma() ( REG_AIC_CR |= AIC_CR_RDMS ) |
paul@43 | 4258 | #define __aic_disable_receive_dma() ( REG_AIC_CR &= ~AIC_CR_RDMS ) |
paul@43 | 4259 | |
paul@43 | 4260 | #define AC97_PCM_XS_L_FRONT AIC_ACCR1_XS_SLOT3 |
paul@43 | 4261 | #define AC97_PCM_XS_R_FRONT AIC_ACCR1_XS_SLOT4 |
paul@43 | 4262 | #define AC97_PCM_XS_CENTER AIC_ACCR1_XS_SLOT6 |
paul@43 | 4263 | #define AC97_PCM_XS_L_SURR AIC_ACCR1_XS_SLOT7 |
paul@43 | 4264 | #define AC97_PCM_XS_R_SURR AIC_ACCR1_XS_SLOT8 |
paul@43 | 4265 | #define AC97_PCM_XS_LFE AIC_ACCR1_XS_SLOT9 |
paul@43 | 4266 | |
paul@43 | 4267 | #define AC97_PCM_RS_L_FRONT AIC_ACCR1_RS_SLOT3 |
paul@43 | 4268 | #define AC97_PCM_RS_R_FRONT AIC_ACCR1_RS_SLOT4 |
paul@43 | 4269 | #define AC97_PCM_RS_CENTER AIC_ACCR1_RS_SLOT6 |
paul@43 | 4270 | #define AC97_PCM_RS_L_SURR AIC_ACCR1_RS_SLOT7 |
paul@43 | 4271 | #define AC97_PCM_RS_R_SURR AIC_ACCR1_RS_SLOT8 |
paul@43 | 4272 | #define AC97_PCM_RS_LFE AIC_ACCR1_RS_SLOT9 |
paul@43 | 4273 | |
paul@43 | 4274 | #define __ac97_set_xs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK ) |
paul@43 | 4275 | #define __ac97_set_xs_mono() \ |
paul@43 | 4276 | do { \ |
paul@43 | 4277 | REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \ |
paul@43 | 4278 | REG_AIC_ACCR1 |= AC97_PCM_XS_R_FRONT; \ |
paul@43 | 4279 | } while(0) |
paul@43 | 4280 | #define __ac97_set_xs_stereo() \ |
paul@43 | 4281 | do { \ |
paul@43 | 4282 | REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \ |
paul@43 | 4283 | REG_AIC_ACCR1 |= AC97_PCM_XS_L_FRONT | AC97_PCM_XS_R_FRONT; \ |
paul@43 | 4284 | } while(0) |
paul@43 | 4285 | |
paul@43 | 4286 | /* In fact, only stereo is support now. */ |
paul@43 | 4287 | #define __ac97_set_rs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK ) |
paul@43 | 4288 | #define __ac97_set_rs_mono() \ |
paul@43 | 4289 | do { \ |
paul@43 | 4290 | REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \ |
paul@43 | 4291 | REG_AIC_ACCR1 |= AC97_PCM_RS_R_FRONT; \ |
paul@43 | 4292 | } while(0) |
paul@43 | 4293 | #define __ac97_set_rs_stereo() \ |
paul@43 | 4294 | do { \ |
paul@43 | 4295 | REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \ |
paul@43 | 4296 | REG_AIC_ACCR1 |= AC97_PCM_RS_L_FRONT | AC97_PCM_RS_R_FRONT; \ |
paul@43 | 4297 | } while(0) |
paul@43 | 4298 | |
paul@43 | 4299 | #define __ac97_warm_reset_codec() \ |
paul@43 | 4300 | do { \ |
paul@43 | 4301 | REG_AIC_ACCR2 |= AIC_ACCR2_SA; \ |
paul@43 | 4302 | REG_AIC_ACCR2 |= AIC_ACCR2_SS; \ |
paul@43 | 4303 | udelay(1); \ |
paul@43 | 4304 | REG_AIC_ACCR2 &= ~AIC_ACCR2_SS; \ |
paul@43 | 4305 | REG_AIC_ACCR2 &= ~AIC_ACCR2_SA; \ |
paul@43 | 4306 | } while (0) |
paul@43 | 4307 | |
paul@43 | 4308 | //#define Jz_AC97_RESET_BUG 1 |
paul@43 | 4309 | #ifndef Jz_AC97_RESET_BUG |
paul@43 | 4310 | #define __ac97_cold_reset_codec() \ |
paul@43 | 4311 | do { \ |
paul@43 | 4312 | REG_AIC_ACCR2 |= AIC_ACCR2_SA; \ |
paul@43 | 4313 | REG_AIC_ACCR2 &= ~AIC_ACCR2_SS; \ |
paul@43 | 4314 | REG_AIC_ACCR2 |= AIC_ACCR2_SR; \ |
paul@43 | 4315 | udelay(1); \ |
paul@43 | 4316 | REG_AIC_ACCR2 &= ~AIC_ACCR2_SR; \ |
paul@43 | 4317 | REG_AIC_ACCR2 &= ~AIC_ACCR2_SA; \ |
paul@43 | 4318 | } while (0) |
paul@43 | 4319 | #else |
paul@43 | 4320 | #define __ac97_cold_reset_codec() \ |
paul@43 | 4321 | do { \ |
paul@43 | 4322 | __gpio_as_output(111); /* SDATA_OUT */ \ |
paul@43 | 4323 | __gpio_as_output(110); /* SDATA_IN */ \ |
paul@43 | 4324 | __gpio_as_output(112); /* SYNC */ \ |
paul@43 | 4325 | __gpio_as_output(114); /* RESET# */ \ |
paul@43 | 4326 | __gpio_clear_pin(111); \ |
paul@43 | 4327 | __gpio_clear_pin(110); \ |
paul@43 | 4328 | __gpio_clear_pin(112); \ |
paul@43 | 4329 | __gpio_clear_pin(114); \ |
paul@43 | 4330 | udelay(2); \ |
paul@43 | 4331 | __gpio_set_pin(114); \ |
paul@43 | 4332 | udelay(1); \ |
paul@43 | 4333 | __gpio_as_ac97(); \ |
paul@43 | 4334 | } while (0) |
paul@43 | 4335 | #endif |
paul@43 | 4336 | |
paul@43 | 4337 | /* n=8,16,18,20 */ |
paul@43 | 4338 | #define __ac97_set_iass(n) \ |
paul@43 | 4339 | ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_IASS_MASK) | AIC_ACCR2_IASS_##n##BIT ) |
paul@43 | 4340 | #define __ac97_set_oass(n) \ |
paul@43 | 4341 | ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_OASS_MASK) | AIC_ACCR2_OASS_##n##BIT ) |
paul@43 | 4342 | |
paul@43 | 4343 | #define __i2s_select_i2s() ( REG_AIC_I2SCR &= ~AIC_I2SCR_AMSL ) |
paul@43 | 4344 | #define __i2s_select_left_justified() ( REG_AIC_I2SCR |= AIC_I2SCR_AMSL ) |
paul@43 | 4345 | |
paul@43 | 4346 | /* n=8,16,18,20,24 */ |
paul@43 | 4347 | #define __i2s_set_sample_size(n) \ |
paul@43 | 4348 | ( REG_AIC_I2SCR |= (REG_AIC_I2SCR & ~AIC_I2SCR_WL_MASK) | AIC_I2SCR_WL_##n##BIT ) |
paul@43 | 4349 | |
paul@43 | 4350 | #define __i2s_stop_clock() ( REG_AIC_I2SCR |= AIC_I2SCR_STPBK ) |
paul@43 | 4351 | #define __i2s_start_clock() ( REG_AIC_I2SCR &= ~AIC_I2SCR_STPBK ) |
paul@43 | 4352 | |
paul@43 | 4353 | #define __aic_transmit_request() ( REG_AIC_SR & AIC_SR_TFS ) |
paul@43 | 4354 | #define __aic_receive_request() ( REG_AIC_SR & AIC_SR_RFS ) |
paul@43 | 4355 | #define __aic_transmit_underrun() ( REG_AIC_SR & AIC_SR_TUR ) |
paul@43 | 4356 | #define __aic_receive_overrun() ( REG_AIC_SR & AIC_SR_ROR ) |
paul@43 | 4357 | |
paul@43 | 4358 | #define __aic_clear_errors() ( REG_AIC_SR &= ~(AIC_SR_TUR | AIC_SR_ROR) ) |
paul@43 | 4359 | |
paul@43 | 4360 | #define __aic_get_transmit_resident() \ |
paul@43 | 4361 | ( (REG_AIC_SR & AIC_SR_TFL_MASK) >> AIC_SR_TFL_BIT ) |
paul@43 | 4362 | #define __aic_get_receive_count() \ |
paul@43 | 4363 | ( (REG_AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_BIT ) |
paul@43 | 4364 | |
paul@43 | 4365 | #define __ac97_command_transmitted() ( REG_AIC_ACSR & AIC_ACSR_CADT ) |
paul@43 | 4366 | #define __ac97_status_received() ( REG_AIC_ACSR & AIC_ACSR_SADR ) |
paul@43 | 4367 | #define __ac97_status_receive_timeout() ( REG_AIC_ACSR & AIC_ACSR_RSTO ) |
paul@43 | 4368 | #define __ac97_codec_is_low_power_mode() ( REG_AIC_ACSR & AIC_ACSR_CLPM ) |
paul@43 | 4369 | #define __ac97_codec_is_ready() ( REG_AIC_ACSR & AIC_ACSR_CRDY ) |
paul@43 | 4370 | |
paul@43 | 4371 | #define __i2s_is_busy() ( REG_AIC_I2SSR & AIC_I2SSR_BSY ) |
paul@43 | 4372 | |
paul@43 | 4373 | #define CODEC_READ_CMD (1 << 19) |
paul@43 | 4374 | #define CODEC_WRITE_CMD (0 << 19) |
paul@43 | 4375 | #define CODEC_REG_INDEX_BIT 12 |
paul@43 | 4376 | #define CODEC_REG_INDEX_MASK (0x7f << CODEC_REG_INDEX_BIT) /* 18:12 */ |
paul@43 | 4377 | #define CODEC_REG_DATA_BIT 4 |
paul@43 | 4378 | #define CODEC_REG_DATA_MASK (0x0ffff << 4) /* 19:4 */ |
paul@43 | 4379 | |
paul@43 | 4380 | #define __ac97_out_rcmd_addr(reg) \ |
paul@43 | 4381 | do { \ |
paul@43 | 4382 | REG_AIC_ACCAR = CODEC_READ_CMD | ((reg) << CODEC_REG_INDEX_BIT); \ |
paul@43 | 4383 | } while (0) |
paul@43 | 4384 | |
paul@43 | 4385 | #define __ac97_out_wcmd_addr(reg) \ |
paul@43 | 4386 | do { \ |
paul@43 | 4387 | REG_AIC_ACCAR = CODEC_WRITE_CMD | ((reg) << CODEC_REG_INDEX_BIT); \ |
paul@43 | 4388 | } while (0) |
paul@43 | 4389 | |
paul@43 | 4390 | #define __ac97_out_data(value) \ |
paul@43 | 4391 | do { \ |
paul@43 | 4392 | REG_AIC_ACCDR = ((value) << CODEC_REG_DATA_BIT); \ |
paul@43 | 4393 | } while (0) |
paul@43 | 4394 | |
paul@43 | 4395 | #define __ac97_in_data() \ |
paul@43 | 4396 | ( (REG_AIC_ACSDR & CODEC_REG_DATA_MASK) >> CODEC_REG_DATA_BIT ) |
paul@43 | 4397 | |
paul@43 | 4398 | #define __ac97_in_status_addr() \ |
paul@43 | 4399 | ( (REG_AIC_ACSAR & CODEC_REG_INDEX_MASK) >> CODEC_REG_INDEX_BIT ) |
paul@43 | 4400 | |
paul@43 | 4401 | #define __i2s_set_sample_rate(i2sclk, sync) \ |
paul@43 | 4402 | ( REG_AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) ) |
paul@43 | 4403 | |
paul@43 | 4404 | #define __aic_write_tfifo(v) ( REG_AIC_DR = (v) ) |
paul@43 | 4405 | #define __aic_read_rfifo() ( REG_AIC_DR ) |
paul@43 | 4406 | |
paul@43 | 4407 | // |
paul@43 | 4408 | // Define next ops for AC97 compatible |
paul@43 | 4409 | // |
paul@43 | 4410 | |
paul@43 | 4411 | #define AC97_ACSR AIC_ACSR |
paul@43 | 4412 | |
paul@43 | 4413 | #define __ac97_enable() __aic_enable(); __aic_select_ac97() |
paul@43 | 4414 | #define __ac97_disable() __aic_disable() |
paul@43 | 4415 | #define __ac97_reset() __aic_reset() |
paul@43 | 4416 | |
paul@43 | 4417 | #define __ac97_set_transmit_trigger(n) __aic_set_transmit_trigger(n) |
paul@43 | 4418 | #define __ac97_set_receive_trigger(n) __aic_set_receive_trigger(n) |
paul@43 | 4419 | |
paul@43 | 4420 | #define __ac97_enable_record() __aic_enable_record() |
paul@43 | 4421 | #define __ac97_disable_record() __aic_disable_record() |
paul@43 | 4422 | #define __ac97_enable_replay() __aic_enable_replay() |
paul@43 | 4423 | #define __ac97_disable_replay() __aic_disable_replay() |
paul@43 | 4424 | #define __ac97_enable_loopback() __aic_enable_loopback() |
paul@43 | 4425 | #define __ac97_disable_loopback() __aic_disable_loopback() |
paul@43 | 4426 | |
paul@43 | 4427 | #define __ac97_enable_transmit_dma() __aic_enable_transmit_dma() |
paul@43 | 4428 | #define __ac97_disable_transmit_dma() __aic_disable_transmit_dma() |
paul@43 | 4429 | #define __ac97_enable_receive_dma() __aic_enable_receive_dma() |
paul@43 | 4430 | #define __ac97_disable_receive_dma() __aic_disable_receive_dma() |
paul@43 | 4431 | |
paul@43 | 4432 | #define __ac97_transmit_request() __aic_transmit_request() |
paul@43 | 4433 | #define __ac97_receive_request() __aic_receive_request() |
paul@43 | 4434 | #define __ac97_transmit_underrun() __aic_transmit_underrun() |
paul@43 | 4435 | #define __ac97_receive_overrun() __aic_receive_overrun() |
paul@43 | 4436 | |
paul@43 | 4437 | #define __ac97_clear_errors() __aic_clear_errors() |
paul@43 | 4438 | |
paul@43 | 4439 | #define __ac97_get_transmit_resident() __aic_get_transmit_resident() |
paul@43 | 4440 | #define __ac97_get_receive_count() __aic_get_receive_count() |
paul@43 | 4441 | |
paul@43 | 4442 | #define __ac97_enable_transmit_intr() __aic_enable_transmit_intr() |
paul@43 | 4443 | #define __ac97_disable_transmit_intr() __aic_disable_transmit_intr() |
paul@43 | 4444 | #define __ac97_enable_receive_intr() __aic_enable_receive_intr() |
paul@43 | 4445 | #define __ac97_disable_receive_intr() __aic_disable_receive_intr() |
paul@43 | 4446 | |
paul@43 | 4447 | #define __ac97_write_tfifo(v) __aic_write_tfifo(v) |
paul@43 | 4448 | #define __ac97_read_rfifo() __aic_read_rfifo() |
paul@43 | 4449 | |
paul@43 | 4450 | // |
paul@43 | 4451 | // Define next ops for I2S compatible |
paul@43 | 4452 | // |
paul@43 | 4453 | |
paul@43 | 4454 | #define I2S_ACSR AIC_I2SSR |
paul@43 | 4455 | |
paul@43 | 4456 | #define __i2s_enable() __aic_enable(); __aic_select_i2s() |
paul@43 | 4457 | #define __i2s_disable() __aic_disable() |
paul@43 | 4458 | #define __i2s_reset() __aic_reset() |
paul@43 | 4459 | |
paul@43 | 4460 | #define __i2s_set_transmit_trigger(n) __aic_set_transmit_trigger(n) |
paul@43 | 4461 | #define __i2s_set_receive_trigger(n) __aic_set_receive_trigger(n) |
paul@43 | 4462 | |
paul@43 | 4463 | #define __i2s_enable_record() __aic_enable_record() |
paul@43 | 4464 | #define __i2s_disable_record() __aic_disable_record() |
paul@43 | 4465 | #define __i2s_enable_replay() __aic_enable_replay() |
paul@43 | 4466 | #define __i2s_disable_replay() __aic_disable_replay() |
paul@43 | 4467 | #define __i2s_enable_loopback() __aic_enable_loopback() |
paul@43 | 4468 | #define __i2s_disable_loopback() __aic_disable_loopback() |
paul@43 | 4469 | |
paul@43 | 4470 | #define __i2s_enable_transmit_dma() __aic_enable_transmit_dma() |
paul@43 | 4471 | #define __i2s_disable_transmit_dma() __aic_disable_transmit_dma() |
paul@43 | 4472 | #define __i2s_enable_receive_dma() __aic_enable_receive_dma() |
paul@43 | 4473 | #define __i2s_disable_receive_dma() __aic_disable_receive_dma() |
paul@43 | 4474 | |
paul@43 | 4475 | #define __i2s_transmit_request() __aic_transmit_request() |
paul@43 | 4476 | #define __i2s_receive_request() __aic_receive_request() |
paul@43 | 4477 | #define __i2s_transmit_underrun() __aic_transmit_underrun() |
paul@43 | 4478 | #define __i2s_receive_overrun() __aic_receive_overrun() |
paul@43 | 4479 | |
paul@43 | 4480 | #define __i2s_clear_errors() __aic_clear_errors() |
paul@43 | 4481 | |
paul@43 | 4482 | #define __i2s_get_transmit_resident() __aic_get_transmit_resident() |
paul@43 | 4483 | #define __i2s_get_receive_count() __aic_get_receive_count() |
paul@43 | 4484 | |
paul@43 | 4485 | #define __i2s_enable_transmit_intr() __aic_enable_transmit_intr() |
paul@43 | 4486 | #define __i2s_disable_transmit_intr() __aic_disable_transmit_intr() |
paul@43 | 4487 | #define __i2s_enable_receive_intr() __aic_enable_receive_intr() |
paul@43 | 4488 | #define __i2s_disable_receive_intr() __aic_disable_receive_intr() |
paul@43 | 4489 | |
paul@43 | 4490 | #define __i2s_write_tfifo(v) __aic_write_tfifo(v) |
paul@43 | 4491 | #define __i2s_read_rfifo() __aic_read_rfifo() |
paul@43 | 4492 | |
paul@43 | 4493 | #define __i2s_reset_codec() \ |
paul@43 | 4494 | do { \ |
paul@43 | 4495 | __gpio_as_output(111); /* SDATA_OUT */ \ |
paul@43 | 4496 | __gpio_as_input(110); /* SDATA_IN */ \ |
paul@43 | 4497 | __gpio_as_output(112); /* SYNC */ \ |
paul@43 | 4498 | __gpio_as_output(114); /* RESET# */ \ |
paul@43 | 4499 | __gpio_clear_pin(111); \ |
paul@43 | 4500 | __gpio_clear_pin(110); \ |
paul@43 | 4501 | __gpio_clear_pin(112); \ |
paul@43 | 4502 | __gpio_clear_pin(114); \ |
paul@43 | 4503 | __gpio_as_i2s_master(); \ |
paul@43 | 4504 | } while (0) |
paul@43 | 4505 | |
paul@43 | 4506 | |
paul@43 | 4507 | /*************************************************************************** |
paul@43 | 4508 | * LCD |
paul@43 | 4509 | ***************************************************************************/ |
paul@43 | 4510 | |
paul@43 | 4511 | #define __lcd_set_dis() ( REG_LCD_CTRL |= LCD_CTRL_DIS ) |
paul@43 | 4512 | #define __lcd_clr_dis() ( REG_LCD_CTRL &= ~LCD_CTRL_DIS ) |
paul@43 | 4513 | |
paul@43 | 4514 | #define __lcd_set_ena() ( REG_LCD_CTRL |= LCD_CTRL_ENA ) |
paul@43 | 4515 | #define __lcd_clr_ena() ( REG_LCD_CTRL &= ~LCD_CTRL_ENA ) |
paul@43 | 4516 | |
paul@43 | 4517 | /* n=1,2,4,8,16 */ |
paul@43 | 4518 | #define __lcd_set_bpp(n) \ |
paul@43 | 4519 | ( REG_LCD_CTRL = (REG_LCD_CTRL & ~LCD_CTRL_BPP_MASK) | LCD_CTRL_BPP_##n ) |
paul@43 | 4520 | |
paul@43 | 4521 | /* n=4,8,16 */ |
paul@43 | 4522 | #define __lcd_set_burst_length(n) \ |
paul@43 | 4523 | do { \ |
paul@43 | 4524 | REG_LCD_CTRL &= ~LCD_CTRL_BST_MASK; \ |
paul@43 | 4525 | REG_LCD_CTRL |= LCD_CTRL_BST_n##; \ |
paul@43 | 4526 | } while (0) |
paul@43 | 4527 | |
paul@43 | 4528 | #define __lcd_select_rgb565() ( REG_LCD_CTRL &= ~LCD_CTRL_RGB555 ) |
paul@43 | 4529 | #define __lcd_select_rgb555() ( REG_LCD_CTRL |= LCD_CTRL_RGB555 ) |
paul@43 | 4530 | |
paul@43 | 4531 | #define __lcd_set_ofup() ( REG_LCD_CTRL |= LCD_CTRL_OFUP ) |
paul@43 | 4532 | #define __lcd_clr_ofup() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUP ) |
paul@43 | 4533 | |
paul@43 | 4534 | /* n=2,4,16 */ |
paul@43 | 4535 | #define __lcd_set_stn_frc(n) \ |
paul@43 | 4536 | do { \ |
paul@43 | 4537 | REG_LCD_CTRL &= ~LCD_CTRL_FRC_MASK; \ |
paul@43 | 4538 | REG_LCD_CTRL |= LCD_CTRL_FRC_n##; \ |
paul@43 | 4539 | } while (0) |
paul@43 | 4540 | |
paul@43 | 4541 | |
paul@43 | 4542 | #define __lcd_pixel_endian_little() ( REG_LCD_CTRL |= LCD_CTRL_PEDN ) |
paul@43 | 4543 | #define __lcd_pixel_endian_big() ( REG_LCD_CTRL &= ~LCD_CTRL_PEDN ) |
paul@43 | 4544 | |
paul@43 | 4545 | #define __lcd_reverse_byte_endian() ( REG_LCD_CTRL |= LCD_CTRL_BEDN ) |
paul@43 | 4546 | #define __lcd_normal_byte_endian() ( REG_LCD_CTRL &= ~LCD_CTRL_BEDN ) |
paul@43 | 4547 | |
paul@43 | 4548 | #define __lcd_enable_eof_intr() ( REG_LCD_CTRL |= LCD_CTRL_EOFM ) |
paul@43 | 4549 | #define __lcd_disable_eof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_EOFM ) |
paul@43 | 4550 | |
paul@43 | 4551 | #define __lcd_enable_sof_intr() ( REG_LCD_CTRL |= LCD_CTRL_SOFM ) |
paul@43 | 4552 | #define __lcd_disable_sof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_SOFM ) |
paul@43 | 4553 | |
paul@43 | 4554 | #define __lcd_enable_ofu_intr() ( REG_LCD_CTRL |= LCD_CTRL_OFUM ) |
paul@43 | 4555 | #define __lcd_disable_ofu_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUM ) |
paul@43 | 4556 | |
paul@43 | 4557 | #define __lcd_enable_ifu0_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM0 ) |
paul@43 | 4558 | #define __lcd_disable_ifu0_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM0 ) |
paul@43 | 4559 | |
paul@43 | 4560 | #define __lcd_enable_ifu1_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM1 ) |
paul@43 | 4561 | #define __lcd_disable_ifu1_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM1 ) |
paul@43 | 4562 | |
paul@43 | 4563 | #define __lcd_enable_ldd_intr() ( REG_LCD_CTRL |= LCD_CTRL_LDDM ) |
paul@43 | 4564 | #define __lcd_disable_ldd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_LDDM ) |
paul@43 | 4565 | |
paul@43 | 4566 | #define __lcd_enable_qd_intr() ( REG_LCD_CTRL |= LCD_CTRL_QDM ) |
paul@43 | 4567 | #define __lcd_disable_qd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_QDM ) |
paul@43 | 4568 | |
paul@43 | 4569 | |
paul@43 | 4570 | /* LCD status register indication */ |
paul@43 | 4571 | |
paul@43 | 4572 | #define __lcd_quick_disable_done() ( REG_LCD_STATE & LCD_STATE_QD ) |
paul@43 | 4573 | #define __lcd_disable_done() ( REG_LCD_STATE & LCD_STATE_LDD ) |
paul@43 | 4574 | #define __lcd_infifo0_underrun() ( REG_LCD_STATE & LCD_STATE_IFU0 ) |
paul@43 | 4575 | #define __lcd_infifo1_underrun() ( REG_LCD_STATE & LCD_STATE_IFU1 ) |
paul@43 | 4576 | #define __lcd_outfifo_underrun() ( REG_LCD_STATE & LCD_STATE_OFU ) |
paul@43 | 4577 | #define __lcd_start_of_frame() ( REG_LCD_STATE & LCD_STATE_SOF ) |
paul@43 | 4578 | #define __lcd_end_of_frame() ( REG_LCD_STATE & LCD_STATE_EOF ) |
paul@43 | 4579 | |
paul@43 | 4580 | #define __lcd_clr_outfifounderrun() ( REG_LCD_STATE &= ~LCD_STATE_OFU ) |
paul@43 | 4581 | #define __lcd_clr_sof() ( REG_LCD_STATE &= ~LCD_STATE_SOF ) |
paul@43 | 4582 | #define __lcd_clr_eof() ( REG_LCD_STATE &= ~LCD_STATE_EOF ) |
paul@43 | 4583 | |
paul@43 | 4584 | #define __lcd_panel_white() ( REG_LCD_DEV |= LCD_DEV_WHITE ) |
paul@43 | 4585 | #define __lcd_panel_black() ( REG_LCD_DEV &= ~LCD_DEV_WHITE ) |
paul@43 | 4586 | |
paul@43 | 4587 | /* n=1,2,4,8 for single mono-STN |
paul@43 | 4588 | * n=4,8 for dual mono-STN |
paul@43 | 4589 | */ |
paul@43 | 4590 | #define __lcd_set_panel_datawidth(n) \ |
paul@43 | 4591 | do { \ |
paul@43 | 4592 | REG_LCD_DEV &= ~LCD_DEV_PDW_MASK; \ |
paul@43 | 4593 | REG_LCD_DEV |= LCD_DEV_PDW_n##; \ |
paul@43 | 4594 | } while (0) |
paul@43 | 4595 | |
paul@43 | 4596 | /* m=LCD_DEV_MODE_GENERUIC_TFT_xxx */ |
paul@43 | 4597 | #define __lcd_set_panel_mode(m) \ |
paul@43 | 4598 | do { \ |
paul@43 | 4599 | REG_LCD_DEV &= ~LCD_DEV_MODE_MASK; \ |
paul@43 | 4600 | REG_LCD_DEV |= (m); \ |
paul@43 | 4601 | } while(0) |
paul@43 | 4602 | |
paul@43 | 4603 | /* n = 0-255 */ |
paul@43 | 4604 | #define __lcd_disable_ac_bias() ( REG_LCD_IO = 0xff ) |
paul@43 | 4605 | #define __lcd_set_ac_bias(n) \ |
paul@43 | 4606 | do { \ |
paul@43 | 4607 | REG_LCD_IO &= ~LCD_IO_ACB_MASK; \ |
paul@43 | 4608 | REG_LCD_IO |= ((n) << LCD_IO_ACB_BIT); \ |
paul@43 | 4609 | } while(0) |
paul@43 | 4610 | |
paul@43 | 4611 | #define __lcd_io_set_dir() ( REG_LCD_IO |= LCD_IO_DIR ) |
paul@43 | 4612 | #define __lcd_io_clr_dir() ( REG_LCD_IO &= ~LCD_IO_DIR ) |
paul@43 | 4613 | |
paul@43 | 4614 | #define __lcd_io_set_dep() ( REG_LCD_IO |= LCD_IO_DEP ) |
paul@43 | 4615 | #define __lcd_io_clr_dep() ( REG_LCD_IO &= ~LCD_IO_DEP ) |
paul@43 | 4616 | |
paul@43 | 4617 | #define __lcd_io_set_vsp() ( REG_LCD_IO |= LCD_IO_VSP ) |
paul@43 | 4618 | #define __lcd_io_clr_vsp() ( REG_LCD_IO &= ~LCD_IO_VSP ) |
paul@43 | 4619 | |
paul@43 | 4620 | #define __lcd_io_set_hsp() ( REG_LCD_IO |= LCD_IO_HSP ) |
paul@43 | 4621 | #define __lcd_io_clr_hsp() ( REG_LCD_IO &= ~LCD_IO_HSP ) |
paul@43 | 4622 | |
paul@43 | 4623 | #define __lcd_io_set_pcp() ( REG_LCD_IO |= LCD_IO_PCP ) |
paul@43 | 4624 | #define __lcd_io_clr_pcp() ( REG_LCD_IO &= ~LCD_IO_PCP ) |
paul@43 | 4625 | |
paul@43 | 4626 | #define __lcd_vsync_get_vps() \ |
paul@43 | 4627 | ( (REG_LCD_VSYNC & LCD_VSYNC_VPS_MASK) >> LCD_VSYNC_VPS_BIT ) |
paul@43 | 4628 | |
paul@43 | 4629 | #define __lcd_vsync_get_vpe() \ |
paul@43 | 4630 | ( (REG_LCD_VSYNC & LCD_VSYNC_VPE_MASK) >> LCD_VSYNC_VPE_BIT ) |
paul@43 | 4631 | #define __lcd_vsync_set_vpe(n) \ |
paul@43 | 4632 | do { \ |
paul@43 | 4633 | REG_LCD_VSYNC &= ~LCD_VSYNC_VPE_MASK; \ |
paul@43 | 4634 | REG_LCD_VSYNC |= (n) << LCD_VSYNC_VPE_BIT; \ |
paul@43 | 4635 | } while (0) |
paul@43 | 4636 | |
paul@43 | 4637 | #define __lcd_hsync_get_hps() \ |
paul@43 | 4638 | ( (REG_LCD_HSYNC & LCD_HSYNC_HPS_MASK) >> LCD_HSYNC_HPS_BIT ) |
paul@43 | 4639 | #define __lcd_hsync_set_hps(n) \ |
paul@43 | 4640 | do { \ |
paul@43 | 4641 | REG_LCD_HSYNC &= ~LCD_HSYNC_HPS_MASK; \ |
paul@43 | 4642 | REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPS_BIT; \ |
paul@43 | 4643 | } while (0) |
paul@43 | 4644 | |
paul@43 | 4645 | #define __lcd_hsync_get_hpe() \ |
paul@43 | 4646 | ( (REG_LCD_HSYNC & LCD_HSYNC_HPE_MASK) >> LCD_VSYNC_HPE_BIT ) |
paul@43 | 4647 | #define __lcd_hsync_set_hpe(n) \ |
paul@43 | 4648 | do { \ |
paul@43 | 4649 | REG_LCD_HSYNC &= ~LCD_HSYNC_HPE_MASK; \ |
paul@43 | 4650 | REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPE_BIT; \ |
paul@43 | 4651 | } while (0) |
paul@43 | 4652 | |
paul@43 | 4653 | #define __lcd_vat_get_ht() \ |
paul@43 | 4654 | ( (REG_LCD_VAT & LCD_VAT_HT_MASK) >> LCD_VAT_HT_BIT ) |
paul@43 | 4655 | #define __lcd_vat_set_ht(n) \ |
paul@43 | 4656 | do { \ |
paul@43 | 4657 | REG_LCD_VAT &= ~LCD_VAT_HT_MASK; \ |
paul@43 | 4658 | REG_LCD_VAT |= (n) << LCD_VAT_HT_BIT; \ |
paul@43 | 4659 | } while (0) |
paul@43 | 4660 | |
paul@43 | 4661 | #define __lcd_vat_get_vt() \ |
paul@43 | 4662 | ( (REG_LCD_VAT & LCD_VAT_VT_MASK) >> LCD_VAT_VT_BIT ) |
paul@43 | 4663 | #define __lcd_vat_set_vt(n) \ |
paul@43 | 4664 | do { \ |
paul@43 | 4665 | REG_LCD_VAT &= ~LCD_VAT_VT_MASK; \ |
paul@43 | 4666 | REG_LCD_VAT |= (n) << LCD_VAT_VT_BIT; \ |
paul@43 | 4667 | } while (0) |
paul@43 | 4668 | |
paul@43 | 4669 | #define __lcd_dah_get_hds() \ |
paul@43 | 4670 | ( (REG_LCD_DAH & LCD_DAH_HDS_MASK) >> LCD_DAH_HDS_BIT ) |
paul@43 | 4671 | #define __lcd_dah_set_hds(n) \ |
paul@43 | 4672 | do { \ |
paul@43 | 4673 | REG_LCD_DAH &= ~LCD_DAH_HDS_MASK; \ |
paul@43 | 4674 | REG_LCD_DAH |= (n) << LCD_DAH_HDS_BIT; \ |
paul@43 | 4675 | } while (0) |
paul@43 | 4676 | |
paul@43 | 4677 | #define __lcd_dah_get_hde() \ |
paul@43 | 4678 | ( (REG_LCD_DAH & LCD_DAH_HDE_MASK) >> LCD_DAH_HDE_BIT ) |
paul@43 | 4679 | #define __lcd_dah_set_hde(n) \ |
paul@43 | 4680 | do { \ |
paul@43 | 4681 | REG_LCD_DAH &= ~LCD_DAH_HDE_MASK; \ |
paul@43 | 4682 | REG_LCD_DAH |= (n) << LCD_DAH_HDE_BIT; \ |
paul@43 | 4683 | } while (0) |
paul@43 | 4684 | |
paul@43 | 4685 | #define __lcd_dav_get_vds() \ |
paul@43 | 4686 | ( (REG_LCD_DAV & LCD_DAV_VDS_MASK) >> LCD_DAV_VDS_BIT ) |
paul@43 | 4687 | #define __lcd_dav_set_vds(n) \ |
paul@43 | 4688 | do { \ |
paul@43 | 4689 | REG_LCD_DAV &= ~LCD_DAV_VDS_MASK; \ |
paul@43 | 4690 | REG_LCD_DAV |= (n) << LCD_DAV_VDS_BIT; \ |
paul@43 | 4691 | } while (0) |
paul@43 | 4692 | |
paul@43 | 4693 | #define __lcd_dav_get_vde() \ |
paul@43 | 4694 | ( (REG_LCD_DAV & LCD_DAV_VDE_MASK) >> LCD_DAV_VDE_BIT ) |
paul@43 | 4695 | #define __lcd_dav_set_vde(n) \ |
paul@43 | 4696 | do { \ |
paul@43 | 4697 | REG_LCD_DAV &= ~LCD_DAV_VDE_MASK; \ |
paul@43 | 4698 | REG_LCD_DAV |= (n) << LCD_DAV_VDE_BIT; \ |
paul@43 | 4699 | } while (0) |
paul@43 | 4700 | |
paul@43 | 4701 | #define __lcd_cmd0_set_sofint() ( REG_LCD_CMD0 |= LCD_CMD_SOFINT ) |
paul@43 | 4702 | #define __lcd_cmd0_clr_sofint() ( REG_LCD_CMD0 &= ~LCD_CMD_SOFINT ) |
paul@43 | 4703 | #define __lcd_cmd1_set_sofint() ( REG_LCD_CMD1 |= LCD_CMD_SOFINT ) |
paul@43 | 4704 | #define __lcd_cmd1_clr_sofint() ( REG_LCD_CMD1 &= ~LCD_CMD_SOFINT ) |
paul@43 | 4705 | |
paul@43 | 4706 | #define __lcd_cmd0_set_eofint() ( REG_LCD_CMD0 |= LCD_CMD_EOFINT ) |
paul@43 | 4707 | #define __lcd_cmd0_clr_eofint() ( REG_LCD_CMD0 &= ~LCD_CMD_EOFINT ) |
paul@43 | 4708 | #define __lcd_cmd1_set_eofint() ( REG_LCD_CMD1 |= LCD_CMD_EOFINT ) |
paul@43 | 4709 | #define __lcd_cmd1_clr_eofint() ( REG_LCD_CMD1 &= ~LCD_CMD_EOFINT ) |
paul@43 | 4710 | |
paul@43 | 4711 | #define __lcd_cmd0_set_pal() ( REG_LCD_CMD0 |= LCD_CMD_PAL ) |
paul@43 | 4712 | #define __lcd_cmd0_clr_pal() ( REG_LCD_CMD0 &= ~LCD_CMD_PAL ) |
paul@43 | 4713 | |
paul@43 | 4714 | #define __lcd_cmd0_get_len() \ |
paul@43 | 4715 | ( (REG_LCD_CMD0 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT ) |
paul@43 | 4716 | #define __lcd_cmd1_get_len() \ |
paul@43 | 4717 | ( (REG_LCD_CMD1 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT ) |
paul@43 | 4718 | |
paul@43 | 4719 | |
paul@43 | 4720 | |
paul@43 | 4721 | /*************************************************************************** |
paul@43 | 4722 | * DES |
paul@43 | 4723 | ***************************************************************************/ |
paul@43 | 4724 | |
paul@43 | 4725 | |
paul@43 | 4726 | /*************************************************************************** |
paul@43 | 4727 | * CPM |
paul@43 | 4728 | ***************************************************************************/ |
paul@43 | 4729 | #define __cpm_plcr1_fd() \ |
paul@43 | 4730 | ((REG_CPM_PLCR1 & CPM_PLCR1_PLL1FD_MASK) >> CPM_PLCR1_PLL1FD_BIT) |
paul@43 | 4731 | #define __cpm_plcr1_rd() \ |
paul@43 | 4732 | ((REG_CPM_PLCR1 & CPM_PLCR1_PLL1RD_MASK) >> CPM_PLCR1_PLL1RD_BIT) |
paul@43 | 4733 | #define __cpm_plcr1_od() \ |
paul@43 | 4734 | ((REG_CPM_PLCR1 & CPM_PLCR1_PLL1OD_MASK) >> CPM_PLCR1_PLL1OD_BIT) |
paul@43 | 4735 | #define __cpm_cfcr_mfr() \ |
paul@43 | 4736 | ((REG_CPM_CFCR & CPM_CFCR_MFR_MASK) >> CPM_CFCR_MFR_BIT) |
paul@43 | 4737 | #define __cpm_cfcr_pfr() \ |
paul@43 | 4738 | ((REG_CPM_CFCR & CPM_CFCR_PFR_MASK) >> CPM_CFCR_PFR_BIT) |
paul@43 | 4739 | #define __cpm_cfcr_sfr() \ |
paul@43 | 4740 | ((REG_CPM_CFCR & CPM_CFCR_SFR_MASK) >> CPM_CFCR_SFR_BIT) |
paul@43 | 4741 | #define __cpm_cfcr_ifr() \ |
paul@43 | 4742 | ((REG_CPM_CFCR & CPM_CFCR_IFR_MASK) >> CPM_CFCR_IFR_BIT) |
paul@43 | 4743 | |
paul@43 | 4744 | static __inline__ unsigned int __cpm_divisor_encode(unsigned int n) |
paul@43 | 4745 | { |
paul@43 | 4746 | unsigned int encode[10] = {1,2,3,4,6,8,12,16,24,32}; |
paul@43 | 4747 | int i; |
paul@43 | 4748 | for (i=0;i<10;i++) |
paul@43 | 4749 | if (n < encode[i]) |
paul@43 | 4750 | break; |
paul@43 | 4751 | return i; |
paul@43 | 4752 | } |
paul@43 | 4753 | |
paul@43 | 4754 | #define __cpm_set_mclk_div(n) \ |
paul@43 | 4755 | do { \ |
paul@43 | 4756 | REG_CPM_CFCR = (REG_CPM_CFCR & ~CPM_CFCR_MFR_MASK) | \ |
paul@43 | 4757 | ((n) << (CPM_CFCR_MFR_BIT)); \ |
paul@43 | 4758 | } while (0) |
paul@43 | 4759 | |
paul@43 | 4760 | #define __cpm_set_pclk_div(n) \ |
paul@43 | 4761 | do { \ |
paul@43 | 4762 | REG_CPM_CFCR = (REG_CPM_CFCR & ~CPM_CFCR_PFR_MASK) | \ |
paul@43 | 4763 | ((n) << (CPM_CFCR_PFR_BIT)); \ |
paul@43 | 4764 | } while (0) |
paul@43 | 4765 | |
paul@43 | 4766 | #define __cpm_set_sclk_div(n) \ |
paul@43 | 4767 | do { \ |
paul@43 | 4768 | REG_CPM_CFCR = (REG_CPM_CFCR & ~CPM_CFCR_SFR_MASK) | \ |
paul@43 | 4769 | ((n) << (CPM_CFCR_SFR_BIT)); \ |
paul@43 | 4770 | } while (0) |
paul@43 | 4771 | |
paul@43 | 4772 | #define __cpm_set_iclk_div(n) \ |
paul@43 | 4773 | do { \ |
paul@43 | 4774 | REG_CPM_CFCR = (REG_CPM_CFCR & ~CPM_CFCR_IFR_MASK) | \ |
paul@43 | 4775 | ((n) << (CPM_CFCR_IFR_BIT)); \ |
paul@43 | 4776 | } while (0) |
paul@43 | 4777 | |
paul@43 | 4778 | #define __cpm_set_lcdclk_div(n) \ |
paul@43 | 4779 | do { \ |
paul@43 | 4780 | REG_CPM_CFCR = (REG_CPM_CFCR & ~CPM_CFCR_LFR_MASK) | \ |
paul@43 | 4781 | ((n) << (CPM_CFCR_LFR_BIT)); \ |
paul@43 | 4782 | } while (0) |
paul@43 | 4783 | |
paul@43 | 4784 | #define __cpm_enable_cko1() (REG_CPM_CFCR |= CPM_CFCR_CKOEN1) |
paul@43 | 4785 | #define __cpm_enable_cko2() (REG_CPM_CFCR |= CPM_CFCR_CKOEN2) |
paul@43 | 4786 | #define __cpm_disable_cko1() (REG_CPM_CFCR &= ~CPM_CFCR_CKOEN1) |
paul@43 | 4787 | #define __cpm_disable_cko2() (REG_CPM_CFCR &= ~CPM_CFCR_CKOEN2) |
paul@43 | 4788 | |
paul@43 | 4789 | #define __cpm_idle_mode() \ |
paul@43 | 4790 | (REG_CPM_LPCR = (REG_CPM_LPCR & ~CPM_LPCR_LPM_MASK) | \ |
paul@43 | 4791 | CPM_LPCR_LPM_IDLE) |
paul@43 | 4792 | #define __cpm_sleep_mode() \ |
paul@43 | 4793 | (REG_CPM_LPCR = (REG_CPM_LPCR & ~CPM_LPCR_LPM_MASK) | \ |
paul@43 | 4794 | CPM_LPCR_LPM_SLEEP) |
paul@43 | 4795 | #define __cpm_hibernate_mode() \ |
paul@43 | 4796 | (REG_CPM_LPCR = (REG_CPM_LPCR & ~CPM_LPCR_LPM_MASK) | \ |
paul@43 | 4797 | CPM_LPCR_LPM_HIBERNATE) |
paul@43 | 4798 | |
paul@43 | 4799 | #define __cpm_start_uart0() \ |
paul@43 | 4800 | (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_UART0)) |
paul@43 | 4801 | #define __cpm_start_uart1() \ |
paul@43 | 4802 | (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_UART1)) |
paul@43 | 4803 | #define __cpm_start_uart2() \ |
paul@43 | 4804 | (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_UART2)) |
paul@43 | 4805 | #define __cpm_start_uart3() \ |
paul@43 | 4806 | (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_UART3)) |
paul@43 | 4807 | #define __cpm_start_ost() \ |
paul@43 | 4808 | (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_OST)) |
paul@43 | 4809 | #define __cpm_start_dmac() \ |
paul@43 | 4810 | (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_DMAC)) |
paul@43 | 4811 | #define __cpm_start_uhc() \ |
paul@43 | 4812 | (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_UHC)) |
paul@43 | 4813 | #define __cpm_start_lcd() \ |
paul@43 | 4814 | (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_LCD)) |
paul@43 | 4815 | #define __cpm_start_i2c() \ |
paul@43 | 4816 | (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_I2C)) |
paul@43 | 4817 | #define __cpm_start_aic_pclk() \ |
paul@43 | 4818 | (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_AICPCLK)) |
paul@43 | 4819 | #define __cpm_start_aic_bitclk() \ |
paul@43 | 4820 | (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_AICBCLK)) |
paul@43 | 4821 | #define __cpm_start_pwm0() \ |
paul@43 | 4822 | (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_PWM0)) |
paul@43 | 4823 | #define __cpm_start_pwm1() \ |
paul@43 | 4824 | (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_PWM1)) |
paul@43 | 4825 | #define __cpm_start_ssi() \ |
paul@43 | 4826 | (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_SSI)) |
paul@43 | 4827 | #define __cpm_start_msc() \ |
paul@43 | 4828 | (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_MSC)) |
paul@43 | 4829 | #define __cpm_start_scc() \ |
paul@43 | 4830 | (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_SCC)) |
paul@43 | 4831 | #define __cpm_start_eth() \ |
paul@43 | 4832 | (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_ETH)) |
paul@43 | 4833 | #define __cpm_start_kbc() \ |
paul@43 | 4834 | (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_KBC)) |
paul@43 | 4835 | #define __cpm_start_cim() \ |
paul@43 | 4836 | (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_CIM)) |
paul@43 | 4837 | #define __cpm_start_udc() \ |
paul@43 | 4838 | (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_UDC)) |
paul@43 | 4839 | #define __cpm_start_uprt() \ |
paul@43 | 4840 | (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_UPRT)) |
paul@43 | 4841 | #define __cpm_start_all() (REG_CPM_MSCR = 0) |
paul@43 | 4842 | |
paul@43 | 4843 | #define __cpm_stop_uart0() \ |
paul@43 | 4844 | (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_UART0)) |
paul@43 | 4845 | #define __cpm_stop_uart1() \ |
paul@43 | 4846 | (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_UART1)) |
paul@43 | 4847 | #define __cpm_stop_uart2() \ |
paul@43 | 4848 | (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_UART2)) |
paul@43 | 4849 | #define __cpm_stop_uart3() \ |
paul@43 | 4850 | (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_UART3)) |
paul@43 | 4851 | #define __cpm_stop_ost() \ |
paul@43 | 4852 | (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_OST)) |
paul@43 | 4853 | #define __cpm_stop_dmac() \ |
paul@43 | 4854 | (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_DMAC)) |
paul@43 | 4855 | #define __cpm_stop_uhc() \ |
paul@43 | 4856 | (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_UHC)) |
paul@43 | 4857 | #define __cpm_stop_lcd() \ |
paul@43 | 4858 | (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_LCD)) |
paul@43 | 4859 | #define __cpm_stop_i2c() \ |
paul@43 | 4860 | (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_I2C)) |
paul@43 | 4861 | #define __cpm_stop_aic_pclk() \ |
paul@43 | 4862 | (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_AICPCLK)) |
paul@43 | 4863 | #define __cpm_stop_aic_bitclk() \ |
paul@43 | 4864 | (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_AICBCLK)) |
paul@43 | 4865 | #define __cpm_stop_pwm0() \ |
paul@43 | 4866 | (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_PWM0)) |
paul@43 | 4867 | #define __cpm_stop_pwm1() \ |
paul@43 | 4868 | (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_PWM1)) |
paul@43 | 4869 | #define __cpm_stop_ssi() \ |
paul@43 | 4870 | (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_SSI)) |
paul@43 | 4871 | #define __cpm_stop_msc() \ |
paul@43 | 4872 | (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_MSC)) |
paul@43 | 4873 | #define __cpm_stop_scc() \ |
paul@43 | 4874 | (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_SCC)) |
paul@43 | 4875 | #define __cpm_stop_eth() \ |
paul@43 | 4876 | (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_ETH)) |
paul@43 | 4877 | #define __cpm_stop_kbc() \ |
paul@43 | 4878 | (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_KBC)) |
paul@43 | 4879 | #define __cpm_stop_cim() \ |
paul@43 | 4880 | (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_CIM)) |
paul@43 | 4881 | #define __cpm_stop_udc() \ |
paul@43 | 4882 | (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_UDC)) |
paul@43 | 4883 | #define __cpm_stop_uprt() \ |
paul@43 | 4884 | (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_UPRT)) |
paul@43 | 4885 | #define __cpm_stop_all() (REG_CPM_MSCR = 0xffffffff) |
paul@43 | 4886 | |
paul@43 | 4887 | #define __cpm_set_pin(n) \ |
paul@43 | 4888 | do { \ |
paul@43 | 4889 | unsigned int p, o; \ |
paul@43 | 4890 | p = (n) / 32; \ |
paul@43 | 4891 | o = (n) % 32; \ |
paul@43 | 4892 | if (p == 0) \ |
paul@43 | 4893 | REG_CPM_GSR0 |= (1 << o); \ |
paul@43 | 4894 | else if (p == 1) \ |
paul@43 | 4895 | REG_CPM_GSR1 |= (1 << o); \ |
paul@43 | 4896 | else if (p == 2) \ |
paul@43 | 4897 | REG_CPM_GSR2 |= (1 << o); \ |
paul@43 | 4898 | else if (p == 3) \ |
paul@43 | 4899 | REG_CPM_GSR3 |= (1 << o); \ |
paul@43 | 4900 | } while (0) |
paul@43 | 4901 | |
paul@43 | 4902 | #define __cpm_clear_pin(n) \ |
paul@43 | 4903 | do { \ |
paul@43 | 4904 | unsigned int p, o; \ |
paul@43 | 4905 | p = (n) / 32; \ |
paul@43 | 4906 | o = (n) % 32; \ |
paul@43 | 4907 | if (p == 0) \ |
paul@43 | 4908 | REG_CPM_GSR0 &= ~(1 << o); \ |
paul@43 | 4909 | else if (p == 1) \ |
paul@43 | 4910 | REG_CPM_GSR1 &= ~(1 << o); \ |
paul@43 | 4911 | else if (p == 2) \ |
paul@43 | 4912 | REG_CPM_GSR2 &= ~(1 << o); \ |
paul@43 | 4913 | else if (p == 3) \ |
paul@43 | 4914 | REG_CPM_GSR3 &= ~(1 << o); \ |
paul@43 | 4915 | } while (0) |
paul@43 | 4916 | |
paul@43 | 4917 | |
paul@43 | 4918 | #define __cpm_select_msc_clk(type) \ |
paul@43 | 4919 | do { \ |
paul@43 | 4920 | if (type == 0) \ |
paul@43 | 4921 | REG_CPM_CFCR &= ~CPM_CFCR_MSC; \ |
paul@43 | 4922 | else \ |
paul@43 | 4923 | REG_CPM_CFCR |= CPM_CFCR_MSC; \ |
paul@43 | 4924 | REG_CPM_CFCR |= CPM_CFCR_UPE; \ |
paul@43 | 4925 | } while(0) |
paul@43 | 4926 | |
paul@43 | 4927 | |
paul@43 | 4928 | /*************************************************************************** |
paul@43 | 4929 | * SSI |
paul@43 | 4930 | ***************************************************************************/ |
paul@43 | 4931 | |
paul@43 | 4932 | #define __ssi_enable() ( REG_SSI_CR0 |= SSI_CR0_SSIE ) |
paul@43 | 4933 | #define __ssi_disable() ( REG_SSI_CR0 &= ~SSI_CR0_SSIE ) |
paul@43 | 4934 | #define __ssi_select_ce() ( REG_SSI_CR0 &= ~SSI_CR0_FSEL ) |
paul@43 | 4935 | |
paul@43 | 4936 | #define __ssi_normal_mode() ( REG_SSI_ITR &= ~SSI_ITR_IVLTM_MASK ) |
paul@43 | 4937 | |
paul@43 | 4938 | #define __ssi_select_ce2() \ |
paul@43 | 4939 | do { \ |
paul@43 | 4940 | REG_SSI_CR0 |= SSI_CR0_FSEL; \ |
paul@43 | 4941 | REG_SSI_CR1 &= ~SSI_CR1_MULTS; \ |
paul@43 | 4942 | } while (0) |
paul@43 | 4943 | |
paul@43 | 4944 | #define __ssi_select_gpc() \ |
paul@43 | 4945 | do { \ |
paul@43 | 4946 | REG_SSI_CR0 &= ~SSI_CR0_FSEL; \ |
paul@43 | 4947 | REG_SSI_CR1 |= SSI_CR1_MULTS; \ |
paul@43 | 4948 | } while (0) |
paul@43 | 4949 | |
paul@43 | 4950 | #define __ssi_enable_tx_intr() \ |
paul@43 | 4951 | ( REG_SSI_CR0 |= SSI_CR0_TIE | SSI_CR0_TEIE ) |
paul@43 | 4952 | |
paul@43 | 4953 | #define __ssi_disable_tx_intr() \ |
paul@43 | 4954 | ( REG_SSI_CR0 &= ~(SSI_CR0_TIE | SSI_CR0_TEIE) ) |
paul@43 | 4955 | |
paul@43 | 4956 | #define __ssi_enable_rx_intr() \ |
paul@43 | 4957 | ( REG_SSI_CR0 |= SSI_CR0_RIE | SSI_CR0_REIE ) |
paul@43 | 4958 | |
paul@43 | 4959 | #define __ssi_disable_rx_intr() \ |
paul@43 | 4960 | ( REG_SSI_CR0 &= ~(SSI_CR0_RIE | SSI_CR0_REIE) ) |
paul@43 | 4961 | |
paul@43 | 4962 | #define __ssi_enable_loopback() ( REG_SSI_CR0 |= SSI_CR0_LOOP ) |
paul@43 | 4963 | #define __ssi_disable_loopback() ( REG_SSI_CR0 &= ~SSI_CR0_LOOP ) |
paul@43 | 4964 | |
paul@43 | 4965 | #define __ssi_enable_receive() ( REG_SSI_CR0 &= ~SSI_CR0_DISREV ) |
paul@43 | 4966 | #define __ssi_disable_receive() ( REG_SSI_CR0 |= SSI_CR0_DISREV ) |
paul@43 | 4967 | |
paul@43 | 4968 | #define __ssi_finish_receive() \ |
paul@43 | 4969 | ( REG_SSI_CR0 |= (SSI_CR0_RFINE | SSI_CR0_RFINC) ) |
paul@43 | 4970 | |
paul@43 | 4971 | #define __ssi_disable_recvfinish() \ |
paul@43 | 4972 | ( REG_SSI_CR0 &= ~(SSI_CR0_RFINE | SSI_CR0_RFINC) ) |
paul@43 | 4973 | |
paul@43 | 4974 | #define __ssi_flush_txfifo() ( REG_SSI_CR0 |= SSI_CR0_TFLUSH ) |
paul@43 | 4975 | #define __ssi_flush_rxfifo() ( REG_SSI_CR0 |= SSI_CR0_RFLUSH ) |
paul@43 | 4976 | |
paul@43 | 4977 | #define __ssi_flush_fifo() \ |
paul@43 | 4978 | ( REG_SSI_CR0 |= SSI_CR0_TFLUSH | SSI_CR0_RFLUSH ) |
paul@43 | 4979 | |
paul@43 | 4980 | #define __ssi_finish_transmit() ( REG_SSI_CR1 &= ~SSI_CR1_UNFIN ) |
paul@43 | 4981 | |
paul@43 | 4982 | /* Motorola's SPI format, set 1 delay */ |
paul@43 | 4983 | #define __ssi_spi_format() \ |
paul@43 | 4984 | do { \ |
paul@43 | 4985 | REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \ |
paul@43 | 4986 | REG_SSI_CR1 |= SSI_CR1_FMAT_SPI; \ |
paul@43 | 4987 | REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\ |
paul@43 | 4988 | REG_SSI_CR1 |= (SSI_CR1_TFVCK_1 | SSI_CR1_TCKFI_1); \ |
paul@43 | 4989 | } while (0) |
paul@43 | 4990 | |
paul@43 | 4991 | /* TI's SSP format, must clear SSI_CR1.UNFIN */ |
paul@43 | 4992 | #define __ssi_ssp_format() \ |
paul@43 | 4993 | do { \ |
paul@43 | 4994 | REG_SSI_CR1 &= ~(SSI_CR1_FMAT_MASK | SSI_CR1_UNFIN); \ |
paul@43 | 4995 | REG_SSI_CR1 |= SSI_CR1_FMAT_SSP; \ |
paul@43 | 4996 | } while (0) |
paul@43 | 4997 | |
paul@43 | 4998 | /* National's Microwire format, must clear SSI_CR0.RFINE, and set max delay */ |
paul@43 | 4999 | #define __ssi_microwire_format() \ |
paul@43 | 5000 | do { \ |
paul@43 | 5001 | REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \ |
paul@43 | 5002 | REG_SSI_CR1 |= SSI_CR1_FMAT_MW1; \ |
paul@43 | 5003 | REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\ |
paul@43 | 5004 | REG_SSI_CR1 |= (SSI_CR1_TFVCK_3 | SSI_CR1_TCKFI_3); \ |
paul@43 | 5005 | REG_SSI_CR0 &= ~SSI_CR0_RFINE; \ |
paul@43 | 5006 | } while (0) |
paul@43 | 5007 | |
paul@43 | 5008 | /* CE# level (FRMHL), CE# in interval time (ITFRM), |
paul@43 | 5009 | clock phase and polarity (PHA POL), |
paul@43 | 5010 | interval time (SSIITR), interval characters/frame (SSIICR) */ |
paul@43 | 5011 | |
paul@43 | 5012 | /* frmhl,endian,mcom,flen,pha,pol MASK */ |
paul@43 | 5013 | #define SSICR1_MISC_MASK \ |
paul@43 | 5014 | ( SSI_CR1_FRMHL_MASK | SSI_CR1_LFST | SSI_CR1_MCOM_MASK \ |
paul@43 | 5015 | | SSI_CR1_FLEN_MASK | SSI_CR1_PHA | SSI_CR1_POL ) \ |
paul@43 | 5016 | |
paul@43 | 5017 | #define __ssi_spi_set_misc(frmhl,endian,flen,mcom,pha,pol) \ |
paul@43 | 5018 | do { \ |
paul@43 | 5019 | REG_SSI_CR1 &= ~SSICR1_MISC_MASK; \ |
paul@43 | 5020 | REG_SSI_CR1 |= ((frmhl) << 30) | ((endian) << 25) | \ |
paul@43 | 5021 | (((mcom) - 1) << 12) | (((flen) - 2) << 4) | \ |
paul@43 | 5022 | ((pha) << 1) | (pol); \ |
paul@43 | 5023 | } while(0) |
paul@43 | 5024 | |
paul@43 | 5025 | /* Transfer with MSB or LSB first */ |
paul@43 | 5026 | #define __ssi_set_msb() ( REG_SSI_CR1 &= ~SSI_CR1_LFST ) |
paul@43 | 5027 | #define __ssi_set_lsb() ( REG_SSI_CR1 |= SSI_CR1_LFST ) |
paul@43 | 5028 | |
paul@43 | 5029 | /* n = 2 - 17 */ |
paul@43 | 5030 | #define __ssi_set_frame_length(n) \ |
paul@43 | 5031 | ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_FLEN_MASK) | SSI_CR1_FLEN_##n##BIT) ) |
paul@43 | 5032 | |
paul@43 | 5033 | /* n = 1 - 16 */ |
paul@43 | 5034 | #define __ssi_set_microwire_command_length(n) \ |
paul@43 | 5035 | ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_MCOM_MASK) | SSI_CR1_MCOM_##n##BIT) ) |
paul@43 | 5036 | |
paul@43 | 5037 | /* Set the clock phase for SPI */ |
paul@43 | 5038 | #define __ssi_set_spi_clock_phase(n) \ |
paul@43 | 5039 | ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_PHA) | (n&0x1)) ) |
paul@43 | 5040 | |
paul@43 | 5041 | /* Set the clock polarity for SPI */ |
paul@43 | 5042 | #define __ssi_set_spi_clock_polarity(n) \ |
paul@43 | 5043 | ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_POL) | (n&0x1)) ) |
paul@43 | 5044 | |
paul@43 | 5045 | /* n = 1,4,8,14 */ |
paul@43 | 5046 | #define __ssi_set_tx_trigger(n) \ |
paul@43 | 5047 | do { \ |
paul@43 | 5048 | REG_SSI_CR1 &= ~SSI_CR1_TTRG_MASK; \ |
paul@43 | 5049 | REG_SSI_CR1 |= SSI_CR1_TTRG_##n; \ |
paul@43 | 5050 | } while (0) |
paul@43 | 5051 | |
paul@43 | 5052 | /* n = 1,4,8,14 */ |
paul@43 | 5053 | #define __ssi_set_rx_trigger(n) \ |
paul@43 | 5054 | do { \ |
paul@43 | 5055 | REG_SSI_CR1 &= ~SSI_CR1_RTRG_MASK; \ |
paul@43 | 5056 | REG_SSI_CR1 |= SSI_CR1_RTRG_##n; \ |
paul@43 | 5057 | } while (0) |
paul@43 | 5058 | |
paul@43 | 5059 | #define __ssi_get_txfifo_count() \ |
paul@43 | 5060 | ( (REG_SSI_SR & SSI_SR_TFIFONUM_MASK) >> SSI_SR_TFIFONUM_BIT ) |
paul@43 | 5061 | |
paul@43 | 5062 | #define __ssi_get_rxfifo_count() \ |
paul@43 | 5063 | ( (REG_SSI_SR & SSI_SR_RFIFONUM_MASK) >> SSI_SR_RFIFONUM_BIT ) |
paul@43 | 5064 | |
paul@43 | 5065 | #define __ssi_clear_errors() \ |
paul@43 | 5066 | ( REG_SSI_SR &= ~(SSI_SR_UNDR | SSI_SR_OVER) ) |
paul@43 | 5067 | |
paul@43 | 5068 | #define __ssi_transfer_end() ( REG_SSI_SR & SSI_SR_END ) |
paul@43 | 5069 | #define __ssi_is_busy() ( REG_SSI_SR & SSI_SR_BUSY ) |
paul@43 | 5070 | |
paul@43 | 5071 | #define __ssi_txfifo_full() ( REG_SSI_SR & SSI_SR_TFF ) |
paul@43 | 5072 | #define __ssi_rxfifo_empty() ( REG_SSI_SR & SSI_SR_RFE ) |
paul@43 | 5073 | #define __ssi_rxfifo_noempty() ( REG_SSI_SR & SSI_SR_RFHF ) |
paul@43 | 5074 | |
paul@43 | 5075 | #define __ssi_set_clk(dev_clk, ssi_clk) \ |
paul@43 | 5076 | ( REG_SSI_GR = (dev_clk) / (2*(ssi_clk)) - 1 ) |
paul@43 | 5077 | |
paul@43 | 5078 | #define __ssi_receive_data() REG_SSI_DR |
paul@43 | 5079 | #define __ssi_transmit_data(v) ( REG_SSI_DR = (v) ) |
paul@43 | 5080 | |
paul@43 | 5081 | /*************************************************************************** |
paul@43 | 5082 | * WDT |
paul@43 | 5083 | ***************************************************************************/ |
paul@43 | 5084 | |
paul@43 | 5085 | #define __wdt_set_count(count) ( REG_WDT_WTCNT = (count) ) |
paul@43 | 5086 | #define __wdt_start() ( REG_WDT_WTCSR |= WDT_WTCSR_START ) |
paul@43 | 5087 | #define __wdt_stop() ( REG_WDT_WTCSR &= ~WDT_WTCSR_START ) |
paul@43 | 5088 | |
paul@43 | 5089 | |
paul@43 | 5090 | /*************************************************************************** |
paul@43 | 5091 | ***************************************************************************/ |
paul@43 | 5092 | |
paul@43 | 5093 | /* |
paul@43 | 5094 | * CPU clocks |
paul@43 | 5095 | */ |
paul@43 | 5096 | #define JZ_EXTAL CONFIG_SYS_EXTAL |
paul@43 | 5097 | #define JZ_EXTAL2 32768 /* RTC clock */ |
paul@43 | 5098 | |
paul@43 | 5099 | static __inline__ unsigned int __cpm_get_pllout(void) |
paul@43 | 5100 | { |
paul@43 | 5101 | unsigned int nf, nr, no, pllout; |
paul@43 | 5102 | unsigned long plcr = REG_CPM_PLCR1; |
paul@43 | 5103 | unsigned long od[4] = {1, 2, 2, 4}; |
paul@43 | 5104 | if (plcr & CPM_PLCR1_PLL1EN) { |
paul@43 | 5105 | nf = (plcr & CPM_PLCR1_PLL1FD_MASK) >> CPM_PLCR1_PLL1FD_BIT; |
paul@43 | 5106 | nr = (plcr & CPM_PLCR1_PLL1RD_MASK) >> CPM_PLCR1_PLL1RD_BIT; |
paul@43 | 5107 | no = od[((plcr & CPM_PLCR1_PLL1OD_MASK) >> CPM_PLCR1_PLL1OD_BIT)]; |
paul@43 | 5108 | pllout = (JZ_EXTAL) / ((nr+2) * no) * (nf+2); |
paul@43 | 5109 | } else |
paul@43 | 5110 | pllout = JZ_EXTAL; |
paul@43 | 5111 | return pllout; |
paul@43 | 5112 | } |
paul@43 | 5113 | |
paul@43 | 5114 | static __inline__ unsigned int __cpm_get_iclk(void) |
paul@43 | 5115 | { |
paul@43 | 5116 | unsigned int iclk; |
paul@43 | 5117 | int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; |
paul@43 | 5118 | unsigned long cfcr = REG_CPM_CFCR; |
paul@43 | 5119 | unsigned long plcr = REG_CPM_PLCR1; |
paul@43 | 5120 | if (plcr & CPM_PLCR1_PLL1EN) |
paul@43 | 5121 | iclk = __cpm_get_pllout() / |
paul@43 | 5122 | div[(cfcr & CPM_CFCR_IFR_MASK) >> CPM_CFCR_IFR_BIT]; |
paul@43 | 5123 | else |
paul@43 | 5124 | iclk = JZ_EXTAL; |
paul@43 | 5125 | return iclk; |
paul@43 | 5126 | } |
paul@43 | 5127 | |
paul@43 | 5128 | static __inline__ unsigned int __cpm_get_sclk(void) |
paul@43 | 5129 | { |
paul@43 | 5130 | unsigned int sclk; |
paul@43 | 5131 | int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; |
paul@43 | 5132 | unsigned long cfcr = REG_CPM_CFCR; |
paul@43 | 5133 | unsigned long plcr = REG_CPM_PLCR1; |
paul@43 | 5134 | if (plcr & CPM_PLCR1_PLL1EN) |
paul@43 | 5135 | sclk = __cpm_get_pllout() / |
paul@43 | 5136 | div[(cfcr & CPM_CFCR_SFR_MASK) >> CPM_CFCR_SFR_BIT]; |
paul@43 | 5137 | else |
paul@43 | 5138 | sclk = JZ_EXTAL; |
paul@43 | 5139 | return sclk; |
paul@43 | 5140 | } |
paul@43 | 5141 | |
paul@43 | 5142 | static __inline__ unsigned int __cpm_get_mclk(void) |
paul@43 | 5143 | { |
paul@43 | 5144 | unsigned int mclk; |
paul@43 | 5145 | int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; |
paul@43 | 5146 | unsigned long cfcr = REG_CPM_CFCR; |
paul@43 | 5147 | unsigned long plcr = REG_CPM_PLCR1; |
paul@43 | 5148 | if (plcr & CPM_PLCR1_PLL1EN) |
paul@43 | 5149 | mclk = __cpm_get_pllout() / |
paul@43 | 5150 | div[(cfcr & CPM_CFCR_MFR_MASK) >> CPM_CFCR_MFR_BIT]; |
paul@43 | 5151 | else |
paul@43 | 5152 | mclk = JZ_EXTAL; |
paul@43 | 5153 | return mclk; |
paul@43 | 5154 | } |
paul@43 | 5155 | |
paul@43 | 5156 | static __inline__ unsigned int __cpm_get_pclk(void) |
paul@43 | 5157 | { |
paul@43 | 5158 | unsigned int devclk; |
paul@43 | 5159 | int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; |
paul@43 | 5160 | unsigned long cfcr = REG_CPM_CFCR; |
paul@43 | 5161 | unsigned long plcr = REG_CPM_PLCR1; |
paul@43 | 5162 | if (plcr & CPM_PLCR1_PLL1EN) |
paul@43 | 5163 | devclk = __cpm_get_pllout() / |
paul@43 | 5164 | div[(cfcr & CPM_CFCR_PFR_MASK) >> CPM_CFCR_PFR_BIT]; |
paul@43 | 5165 | else |
paul@43 | 5166 | devclk = JZ_EXTAL; |
paul@43 | 5167 | return devclk; |
paul@43 | 5168 | } |
paul@43 | 5169 | |
paul@43 | 5170 | static __inline__ unsigned int __cpm_get_devclk(void) |
paul@43 | 5171 | { |
paul@43 | 5172 | unsigned int devclk; |
paul@43 | 5173 | int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; |
paul@43 | 5174 | unsigned long cfcr = REG_CPM_CFCR; |
paul@43 | 5175 | unsigned long plcr = REG_CPM_PLCR1; |
paul@43 | 5176 | if (plcr & CPM_PLCR1_PLL1EN) |
paul@43 | 5177 | devclk = __cpm_get_pllout() / |
paul@43 | 5178 | div[(cfcr & CPM_CFCR_PFR_MASK) >> CPM_CFCR_PFR_BIT]; |
paul@43 | 5179 | else |
paul@43 | 5180 | devclk = JZ_EXTAL; |
paul@43 | 5181 | return devclk; |
paul@43 | 5182 | } |
paul@43 | 5183 | |
paul@43 | 5184 | #endif /* !__ASSEMBLY__ */ |
paul@43 | 5185 | |
paul@43 | 5186 | #endif /* __JZ4730_H__ */ |