paul@0 | 1 | /* |
paul@35 | 2 | * Generic board initialisation, based on uboot-xburst and xburst-tools. |
paul@0 | 3 | * |
paul@35 | 4 | * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, <wd@denx.de> |
paul@35 | 5 | * Copyright (C) 2005-2006 Ingenic Semiconductor, <jlwei@ingenic.cn> |
paul@57 | 6 | * Copyright (C) 2006 Stefan Roese, DENX Software Engineering, sr@denx.de. |
paul@35 | 7 | * Copyright (C) Xiangfu Liu <xiangfu.z@gmail.com> |
paul@0 | 8 | * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk> |
paul@0 | 9 | * |
paul@63 | 10 | * This program is free software: you can redistribute it and/or modify |
paul@63 | 11 | * it under the terms of the GNU General Public License as published by |
paul@63 | 12 | * the Free Software Foundation, either version 3 of the License, or |
paul@63 | 13 | * (at your option) any later version. |
paul@0 | 14 | * |
paul@63 | 15 | * This program is distributed in the hope that it will be useful, |
paul@63 | 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@63 | 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@63 | 18 | * GNU General Public License for more details. |
paul@0 | 19 | * |
paul@63 | 20 | * You should have received a copy of the GNU General Public License |
paul@63 | 21 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
paul@0 | 22 | */ |
paul@0 | 23 | |
paul@35 | 24 | #ifdef CONFIG_CPU_JZ4730 |
paul@35 | 25 | #include "jz4730.h" |
paul@43 | 26 | #include "jz4730_compat.h" |
paul@35 | 27 | #else |
paul@0 | 28 | #include "jz4740.h" |
paul@35 | 29 | #endif |
paul@35 | 30 | |
paul@33 | 31 | #include "sdram.h" |
paul@10 | 32 | #include "usb_boot_defines.h" |
paul@10 | 33 | |
paul@10 | 34 | /* These arguments are initialised by usbboot and are defined in... |
paul@10 | 35 | /etc/xburst-tools/usbboot.cfg. */ |
paul@10 | 36 | |
paul@10 | 37 | struct fw_args *fw_args; |
paul@27 | 38 | volatile u32 FW_CPU_ID; |
paul@27 | 39 | volatile u8 FW_SDRAM_BW16; |
paul@27 | 40 | volatile u8 FW_SDRAM_BANK4; |
paul@27 | 41 | volatile u8 FW_SDRAM_ROW; |
paul@27 | 42 | volatile u8 FW_SDRAM_COL; |
paul@27 | 43 | volatile u8 FW_CONFIG_MOBILE_SDRAM; |
paul@27 | 44 | volatile u8 FW_IS_SHARE; |
paul@10 | 45 | |
paul@10 | 46 | void load_args(void) |
paul@10 | 47 | { |
paul@17 | 48 | /* Get the fw args from memory. See head1.S for the memory layout. */ |
paul@10 | 49 | |
paul@10 | 50 | fw_args = (struct fw_args *)0x80002008; |
paul@27 | 51 | FW_CPU_ID = fw_args->cpu_id ; |
paul@60 | 52 | |
paul@60 | 53 | /* Where the arguments have not been initialised, use the defaults. */ |
paul@60 | 54 | |
paul@60 | 55 | FW_SDRAM_BW16 = FW_CPU_ID ? fw_args->bus_width : SDRAM_BW16; |
paul@60 | 56 | FW_SDRAM_BANK4 = FW_CPU_ID ? fw_args->bank_num : SDRAM_BANK4; |
paul@60 | 57 | FW_SDRAM_ROW = FW_CPU_ID ? fw_args->row_addr : SDRAM_ROW; |
paul@60 | 58 | FW_SDRAM_COL = FW_CPU_ID ? fw_args->col_addr : SDRAM_COL; |
paul@27 | 59 | FW_CONFIG_MOBILE_SDRAM = fw_args->is_mobile; |
paul@27 | 60 | FW_IS_SHARE = fw_args->is_busshare; |
paul@10 | 61 | } |
paul@10 | 62 | |
paul@10 | 63 | /* Initialisation functions. */ |
paul@0 | 64 | |
paul@0 | 65 | void gpio_init(void) |
paul@0 | 66 | { |
paul@57 | 67 | #ifdef CONFIG_CPU_JZ4730 |
paul@57 | 68 | /* |
paul@57 | 69 | * Initialize SDRAM pins |
paul@57 | 70 | */ |
paul@57 | 71 | __gpio_as_emc(); |
paul@57 | 72 | #else |
paul@0 | 73 | /* |
paul@0 | 74 | * Initialize NAND Flash Pins |
paul@0 | 75 | */ |
paul@0 | 76 | __gpio_as_nand(); |
paul@0 | 77 | |
paul@0 | 78 | /* |
paul@0 | 79 | * Initialize SDRAM pins |
paul@0 | 80 | */ |
paul@17 | 81 | __gpio_as_sdram_16bit_4720(); |
paul@45 | 82 | #endif |
paul@6 | 83 | } |
paul@0 | 84 | |
paul@0 | 85 | void pll_init(void) |
paul@0 | 86 | { |
paul@0 | 87 | register unsigned int cfcr, plcr1; |
paul@0 | 88 | int nf, pllout2; |
paul@0 | 89 | |
paul@17 | 90 | /* See CPCCR (Clock Control Register). |
paul@17 | 91 | * 0 == same frequency; 2 == f/3 |
paul@17 | 92 | */ |
paul@17 | 93 | |
paul@0 | 94 | cfcr = CPM_CPCCR_CLKOEN | |
paul@17 | 95 | CPM_CPCCR_PCS | |
paul@17 | 96 | (0 << CPM_CPCCR_CDIV_BIT) | |
paul@17 | 97 | (2 << CPM_CPCCR_HDIV_BIT) | |
paul@17 | 98 | (2 << CPM_CPCCR_PDIV_BIT) | |
paul@17 | 99 | (2 << CPM_CPCCR_MDIV_BIT) | |
paul@17 | 100 | (2 << CPM_CPCCR_LDIV_BIT); |
paul@0 | 101 | |
paul@17 | 102 | /* Init USB Host clock. |
paul@17 | 103 | * Desired frequency == 48MHz |
paul@17 | 104 | */ |
paul@17 | 105 | |
paul@33 | 106 | #ifdef CONFIG_CPU_JZ4730 |
paul@33 | 107 | cfcr |= ((CFG_CPU_SPEED / 48000000 - 1) << 25); |
paul@33 | 108 | #else |
paul@33 | 109 | /* Determine the divider clock output based on the PCS bit. */ |
paul@33 | 110 | pllout2 = (cfcr & CPM_CPCCR_PCS) ? CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2); |
paul@33 | 111 | |
paul@33 | 112 | /* Divisor == UHCCDR + 1 */ |
paul@0 | 113 | REG_CPM_UHCCDR = pllout2 / 48000000 - 1; |
paul@33 | 114 | #endif |
paul@0 | 115 | |
paul@17 | 116 | nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL; |
paul@17 | 117 | plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */ |
paul@17 | 118 | (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */ |
paul@17 | 119 | (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */ |
paul@17 | 120 | CPM_CPPCR_PLLEN; /* enable PLL */ |
paul@0 | 121 | |
paul@17 | 122 | /* Update PLL and wait. */ |
paul@17 | 123 | |
paul@0 | 124 | REG_CPM_CPCCR = cfcr; |
paul@0 | 125 | REG_CPM_CPPCR = plcr1; |
paul@17 | 126 | while (!__cpm_pll_is_on()); |
paul@0 | 127 | } |
paul@0 | 128 | |
paul@0 | 129 | void sdram_init(void) |
paul@0 | 130 | { |
paul@0 | 131 | register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns; |
paul@17 | 132 | unsigned int pllout = __cpm_get_pllout(); |
paul@0 | 133 | |
paul@0 | 134 | unsigned int cas_latency_sdmr[2] = { |
paul@0 | 135 | EMC_SDMR_CAS_2, |
paul@0 | 136 | EMC_SDMR_CAS_3, |
paul@0 | 137 | }; |
paul@0 | 138 | |
paul@0 | 139 | unsigned int cas_latency_dmcr[2] = { |
paul@0 | 140 | 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */ |
paul@0 | 141 | 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */ |
paul@0 | 142 | }; |
paul@0 | 143 | |
paul@17 | 144 | /* Divisors for CPCCR values. */ |
paul@17 | 145 | |
paul@0 | 146 | int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; |
paul@0 | 147 | |
paul@17 | 148 | cpu_clk = pllout / div[__cpm_get_cdiv()]; |
paul@17 | 149 | mem_clk = pllout / div[__cpm_get_mdiv()]; |
paul@0 | 150 | |
paul@0 | 151 | REG_EMC_BCR = 0; /* Disable bus release */ |
paul@0 | 152 | REG_EMC_RTCSR = 0; /* Disable clock for counting */ |
paul@0 | 153 | |
paul@0 | 154 | /* Fault DMCR value for mode register setting*/ |
paul@30 | 155 | dmcr0 = (0<<EMC_DMCR_RA_BIT) | |
paul@30 | 156 | (0<<EMC_DMCR_CA_BIT) | |
paul@30 | 157 | (0<<EMC_DMCR_BA_BIT) | |
paul@27 | 158 | (FW_SDRAM_BW16<<EMC_DMCR_BW_BIT) | |
paul@0 | 159 | EMC_DMCR_EPIN | |
paul@0 | 160 | cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; |
paul@0 | 161 | |
paul@0 | 162 | /* Basic DMCR value */ |
paul@30 | 163 | dmcr = ((FW_SDRAM_ROW-SDRAM_ROW0)<<EMC_DMCR_RA_BIT) | |
paul@30 | 164 | ((FW_SDRAM_COL-SDRAM_COL0)<<EMC_DMCR_CA_BIT) | |
paul@30 | 165 | ((FW_SDRAM_BANK4-SDRAM_BANK40)<<EMC_DMCR_BA_BIT) | |
paul@27 | 166 | (FW_SDRAM_BW16<<EMC_DMCR_BW_BIT) | |
paul@0 | 167 | EMC_DMCR_EPIN | |
paul@0 | 168 | cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; |
paul@0 | 169 | |
paul@0 | 170 | /* SDRAM timimg */ |
paul@0 | 171 | ns = 1000000000 / mem_clk; |
paul@0 | 172 | tmp = SDRAM_TRAS/ns; |
paul@0 | 173 | if (tmp < 4) tmp = 4; |
paul@0 | 174 | if (tmp > 11) tmp = 11; |
paul@0 | 175 | dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT); |
paul@0 | 176 | tmp = SDRAM_RCD/ns; |
paul@0 | 177 | if (tmp > 3) tmp = 3; |
paul@0 | 178 | dmcr |= (tmp << EMC_DMCR_RCD_BIT); |
paul@0 | 179 | tmp = SDRAM_TPC/ns; |
paul@0 | 180 | if (tmp > 7) tmp = 7; |
paul@0 | 181 | dmcr |= (tmp << EMC_DMCR_TPC_BIT); |
paul@0 | 182 | tmp = SDRAM_TRWL/ns; |
paul@0 | 183 | if (tmp > 3) tmp = 3; |
paul@0 | 184 | dmcr |= (tmp << EMC_DMCR_TRWL_BIT); |
paul@0 | 185 | tmp = (SDRAM_TRAS + SDRAM_TPC)/ns; |
paul@0 | 186 | if (tmp > 14) tmp = 14; |
paul@0 | 187 | dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT); |
paul@0 | 188 | |
paul@0 | 189 | /* SDRAM mode value */ |
paul@0 | 190 | sdmode = EMC_SDMR_BT_SEQ | |
paul@0 | 191 | EMC_SDMR_OM_NORMAL | |
paul@0 | 192 | EMC_SDMR_BL_4 | |
paul@0 | 193 | cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)]; |
paul@0 | 194 | |
paul@33 | 195 | /* jz4730 additional measures */ |
paul@33 | 196 | #ifdef CONFIG_CPU_JZ4730 |
paul@33 | 197 | if (FW_SDRAM_BW16) |
paul@33 | 198 | sdmode <<= 1; |
paul@33 | 199 | else |
paul@33 | 200 | sdmode <<= 2; |
paul@33 | 201 | #endif |
paul@33 | 202 | |
paul@0 | 203 | /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */ |
paul@0 | 204 | REG_EMC_DMCR = dmcr; |
paul@0 | 205 | REG8(EMC_SDMR0|sdmode) = 0; |
paul@0 | 206 | |
paul@33 | 207 | /* jz4730 additional measures */ |
paul@33 | 208 | #ifdef CONFIG_CPU_JZ4730 |
paul@33 | 209 | REG8(EMC_SDMR1|sdmode) = 0; |
paul@33 | 210 | #endif |
paul@33 | 211 | |
paul@0 | 212 | /* Wait for precharge, > 200us */ |
paul@0 | 213 | tmp = (cpu_clk / 1000000) * 1000; |
paul@0 | 214 | while (tmp--); |
paul@0 | 215 | |
paul@0 | 216 | /* Stage 2. Enable auto-refresh */ |
paul@0 | 217 | REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH; |
paul@0 | 218 | |
paul@0 | 219 | tmp = SDRAM_TREF/ns; |
paul@0 | 220 | tmp = tmp/64 + 1; |
paul@0 | 221 | if (tmp > 0xff) tmp = 0xff; |
paul@0 | 222 | REG_EMC_RTCOR = tmp; |
paul@0 | 223 | REG_EMC_RTCNT = 0; |
paul@0 | 224 | REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */ |
paul@0 | 225 | |
paul@0 | 226 | /* Wait for number of auto-refresh cycles */ |
paul@0 | 227 | tmp = (cpu_clk / 1000000) * 1000; |
paul@0 | 228 | while (tmp--); |
paul@0 | 229 | |
paul@0 | 230 | /* Stage 3. Mode Register Set */ |
paul@0 | 231 | REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET; |
paul@0 | 232 | REG8(EMC_SDMR0|sdmode) = 0; |
paul@0 | 233 | |
paul@33 | 234 | /* jz4730 additional measures */ |
paul@33 | 235 | #ifdef CONFIG_CPU_JZ4730 |
paul@33 | 236 | REG8(EMC_SDMR1|sdmode) = 0; |
paul@33 | 237 | #endif |
paul@33 | 238 | |
paul@0 | 239 | /* Set back to basic DMCR value */ |
paul@0 | 240 | REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET; |
paul@0 | 241 | |
paul@0 | 242 | /* everything is ok now */ |
paul@0 | 243 | } |