paul@62 | 1 | /* |
paul@90 | 2 | * CPU-specific routines originally from U-Boot. |
paul@62 | 3 | * See: uboot-xburst/files/arch/mips/cpu/xburst/cpu.c |
paul@62 | 4 | * See: u-boot/arch/mips/include/asm/cacheops.h |
paul@62 | 5 | * |
paul@62 | 6 | * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, <wd@denx.de> |
paul@90 | 7 | * Copyright (C) 2015, 2016 Paul Boddie <paul@boddie.org.uk> |
paul@62 | 8 | * |
paul@62 | 9 | * This program is free software; you can redistribute it and/or |
paul@62 | 10 | * modify it under the terms of the GNU General Public License as |
paul@62 | 11 | * published by the Free Software Foundation; either version 2 of |
paul@62 | 12 | * the License, or (at your option) any later version. |
paul@62 | 13 | * |
paul@62 | 14 | * This program is distributed in the hope that it will be useful, |
paul@62 | 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@62 | 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@62 | 17 | * GNU General Public License for more details. |
paul@62 | 18 | * |
paul@62 | 19 | * You should have received a copy of the GNU General Public License |
paul@62 | 20 | * along with this program; if not, write to the Free Software |
paul@62 | 21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@62 | 22 | * Boston, MA 02110-1301, USA |
paul@62 | 23 | */ |
paul@62 | 24 | |
paul@113 | 25 | #include "cpu.h" |
paul@62 | 26 | #include "sdram.h" |
paul@151 | 27 | #include "paging.h" |
paul@62 | 28 | |
paul@62 | 29 | void flush_icache_all(void) |
paul@62 | 30 | { |
paul@62 | 31 | u32 addr, t = 0; |
paul@62 | 32 | |
paul@62 | 33 | asm volatile ("mtc0 $0, $28"); /* Clear Taglo */ |
paul@62 | 34 | asm volatile ("mtc0 $0, $29"); /* Clear TagHi */ |
paul@62 | 35 | |
paul@62 | 36 | for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_ICACHE_SIZE; |
paul@62 | 37 | addr += CONFIG_SYS_CACHELINE_SIZE) { |
paul@62 | 38 | asm volatile ( |
paul@62 | 39 | ".set mips3\n\t" |
paul@62 | 40 | " cache %0, 0(%1)\n\t" |
paul@62 | 41 | ".set mips2\n\t" |
paul@62 | 42 | : |
paul@62 | 43 | : "I" (Index_Store_Tag_I), "r"(addr)); |
paul@62 | 44 | } |
paul@62 | 45 | |
paul@62 | 46 | /* invalicate btb */ |
paul@62 | 47 | asm volatile ( |
paul@62 | 48 | ".set mips32\n\t" |
paul@62 | 49 | "mfc0 %0, $16, 7\n\t" |
paul@62 | 50 | "nop\n\t" |
paul@62 | 51 | "ori %0,2\n\t" |
paul@62 | 52 | "mtc0 %0, $16, 7\n\t" |
paul@62 | 53 | ".set mips2\n\t" |
paul@62 | 54 | : |
paul@62 | 55 | : "r" (t)); |
paul@62 | 56 | } |
paul@62 | 57 | |
paul@62 | 58 | void flush_dcache_all(void) |
paul@62 | 59 | { |
paul@62 | 60 | u32 addr; |
paul@62 | 61 | |
paul@62 | 62 | for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE; |
paul@62 | 63 | addr += CONFIG_SYS_CACHELINE_SIZE) { |
paul@62 | 64 | asm volatile ( |
paul@62 | 65 | ".set mips3\n\t" |
paul@62 | 66 | " cache %0, 0(%1)\n\t" |
paul@62 | 67 | ".set mips2\n\t" |
paul@62 | 68 | : |
paul@62 | 69 | : "I" (Index_Writeback_Inv_D), "r"(addr)); |
paul@62 | 70 | } |
paul@62 | 71 | |
paul@62 | 72 | asm volatile ("sync"); |
paul@62 | 73 | } |
paul@62 | 74 | |
paul@62 | 75 | void flush_cache_all(void) |
paul@62 | 76 | { |
paul@62 | 77 | flush_dcache_all(); |
paul@62 | 78 | flush_icache_all(); |
paul@62 | 79 | } |
paul@67 | 80 | |
paul@73 | 81 | void handle_error_level(void) |
paul@73 | 82 | { |
paul@73 | 83 | asm volatile( |
paul@117 | 84 | "mfc0 $t3, $12\n" /* CP0_STATUS */ |
paul@117 | 85 | "li $t4, 0xfffffffb\n" /* ERL = 0 */ |
paul@115 | 86 | "and $t3, $t3, $t4\n" |
paul@115 | 87 | "mtc0 $t3, $12\n" |
paul@115 | 88 | "nop\n"); |
paul@115 | 89 | } |
paul@115 | 90 | |
paul@67 | 91 | void enable_interrupts(void) |
paul@67 | 92 | { |
paul@67 | 93 | asm volatile( |
paul@117 | 94 | "mfc0 $t3, $12\n" /* CP0_STATUS */ |
paul@117 | 95 | "li $t4, 0x0000fc01\n" /* IE = enable interrupts */ |
paul@67 | 96 | "or $t3, $t3, $t4\n" |
paul@67 | 97 | "mtc0 $t3, $12\n" |
paul@67 | 98 | "nop\n"); |
paul@67 | 99 | } |
paul@73 | 100 | |
paul@73 | 101 | void init_interrupts(void) |
paul@73 | 102 | { |
paul@73 | 103 | /* Set exception registers. */ |
paul@73 | 104 | |
paul@73 | 105 | asm volatile( |
paul@73 | 106 | "mtc0 $zero, $18\n" /* CP0_WATCHLO */ |
paul@73 | 107 | "li $t3, 0x00800000\n" /* IV = 1 (use 0x80000200 for interrupts) */ |
paul@73 | 108 | "mtc0 $t3, $13\n" /* CP0_CAUSE */ |
paul@111 | 109 | "mfc0 $t4, $12\n" /* CP0_STATUS */ |
paul@111 | 110 | "li $t3, 0xffbfffff\n" /* BEV=0 */ |
paul@84 | 111 | "and $t3, $t3, $t4\n" |
paul@84 | 112 | "mtc0 $t3, $12\n" |
paul@73 | 113 | "nop\n"); |
paul@73 | 114 | } |
paul@73 | 115 | |
paul@133 | 116 | void set_task(u8 asid) |
paul@133 | 117 | { |
paul@133 | 118 | asm volatile( |
paul@133 | 119 | |
paul@133 | 120 | /* Set the ASID. */ |
paul@133 | 121 | |
paul@133 | 122 | "mtc0 %0, $10\n" /* CP0_ENTRYHI */ |
paul@133 | 123 | "nop" |
paul@133 | 124 | : |
paul@133 | 125 | : "r" (asid) |
paul@133 | 126 | ); |
paul@133 | 127 | } |
paul@133 | 128 | |
paul@145 | 129 | void init_registers(u32 *base, u32 got, void (*function)(), u32 args[], u8 nargs) |
paul@133 | 130 | { |
paul@133 | 131 | u8 i; |
paul@133 | 132 | |
paul@133 | 133 | /* Provide arguments to the function. */ |
paul@133 | 134 | |
paul@133 | 135 | for (i = 0; i < nargs; i++) |
paul@133 | 136 | { |
paul@145 | 137 | base[i+4] = args[i]; |
paul@133 | 138 | } |
paul@133 | 139 | |
paul@133 | 140 | /* Store essential data for the function environment. */ |
paul@133 | 141 | |
paul@145 | 142 | base[25] = (u32) function - 0x80000000; /* store the function address as t9 */ |
paul@145 | 143 | base[26] = got - 0x80000000; /* store the global pointer */ |
paul@145 | 144 | base[29] = (u32) function - 0x80000000; /* store the function address as EPC (for the handler) */ |
paul@133 | 145 | } |
paul@133 | 146 | |
paul@117 | 147 | void enter_user_mode(void) |
paul@117 | 148 | { |
paul@117 | 149 | asm volatile( |
paul@117 | 150 | "mfc0 $t3, $12\n" /* CP0_STATUS */ |
paul@124 | 151 | "li $t4, 0x00000010\n" /* KSU = 2 (UM = 1) */ |
paul@124 | 152 | "or $t3, $t3, $t4\n" |
paul@117 | 153 | "mtc0 $t3, $12\n" |
paul@117 | 154 | "nop\n"); |
paul@117 | 155 | } |
paul@117 | 156 | |
paul@73 | 157 | void init_tlb(void) |
paul@73 | 158 | { |
paul@147 | 159 | unsigned short first_random = 0, i, limit; |
paul@136 | 160 | |
paul@73 | 161 | asm volatile( |
paul@136 | 162 | "mtc0 $zero, $4\n" /* CP0_CONTEXT */ |
paul@147 | 163 | "mtc0 %1, $6\n" /* CP0_WIRED */ |
paul@147 | 164 | "mfc0 %0, $16\n" /* CP0_CONFIG1 */ |
paul@145 | 165 | "nop" |
paul@147 | 166 | : "=r" (limit) |
paul@145 | 167 | : "r" (first_random) |
paul@145 | 168 | ); |
paul@147 | 169 | |
paul@147 | 170 | /* Reset the mappings. The total number is bits 30..25 of Config1. */ |
paul@147 | 171 | |
paul@147 | 172 | for (i = 0; i < ((limit >> 25) & 0x3f); i++) |
paul@147 | 173 | { |
paul@157 | 174 | map_page_index(0, 0, 4096, 0, 0, i); |
paul@147 | 175 | } |
paul@117 | 176 | } |
paul@83 | 177 | |
paul@117 | 178 | void map_page_index(u32 virtual, u32 physical, u32 pagesize, u8 flags, u8 asid, u32 index) |
paul@117 | 179 | { |
paul@130 | 180 | u32 start = (virtual & 0xffffe000) | asid; /* VPN2 | ASID*/ |
paul@117 | 181 | u32 lower = ((physical & 0xfffff000) >> 6) | flags; |
paul@117 | 182 | u32 upper = (((physical + pagesize) & 0xfffff000) >> 6) | flags; |
paul@117 | 183 | u32 pagemask = ((pagesize - 1) & 0xfffff000) << 1; |
paul@117 | 184 | |
paul@117 | 185 | asm volatile( |
paul@117 | 186 | "mtc0 %3, $5\n" /* CP0_PAGEMASK */ |
paul@117 | 187 | |
paul@117 | 188 | /* Set the index. */ |
paul@117 | 189 | |
paul@117 | 190 | "mtc0 %4, $0\n" /* CP0_INDEX */ |
paul@83 | 191 | |
paul@73 | 192 | /* Set physical address. */ |
paul@73 | 193 | |
paul@117 | 194 | "mtc0 %0, $2\n" /* CP0_ENTRYLO0 */ |
paul@117 | 195 | "mtc0 %1, $3\n" /* CP0_ENTRYLO1 */ |
paul@73 | 196 | |
paul@73 | 197 | /* Set virtual address. */ |
paul@73 | 198 | |
paul@130 | 199 | "mtc0 %2, $10\n" /* CP0_ENTRYHI */ |
paul@73 | 200 | "nop\n" |
paul@73 | 201 | |
paul@83 | 202 | "tlbwi\n" |
paul@117 | 203 | "nop" |
paul@117 | 204 | : |
paul@117 | 205 | : "r" (lower), "r" (upper), "r" (start), "r" (pagemask), "r" (index) |
paul@117 | 206 | ); |
paul@113 | 207 | } |
paul@83 | 208 | |
paul@136 | 209 | void init_page_table(u32 page_table, u32 virtual, u32 physical, u32 pagesize, u8 flags, u8 asid) |
paul@136 | 210 | { |
paul@136 | 211 | u32 lower = ((physical & 0xfffff000) >> 6) | flags; |
paul@136 | 212 | u32 upper = (((physical + pagesize) & 0xfffff000) >> 6) | flags; |
paul@136 | 213 | |
paul@136 | 214 | /* |
paul@136 | 215 | With a complete address space mapping involving pairs of 4KB pages |
paul@136 | 216 | described by two values for each entry, there would be... |
paul@136 | 217 | |
paul@136 | 218 | an address space of 0x100000000 requiring... |
paul@136 | 219 | |
paul@136 | 220 | 0x100000000 / (8 * 1024) == 0x100000000 >> 13 |
paul@136 | 221 | == 524288 entries |
paul@136 | 222 | == 0x80000 entries |
paul@136 | 223 | |
paul@136 | 224 | Thus, each task's entries would require... |
paul@136 | 225 | |
paul@136 | 226 | 0x80000 * 8 == 0x400000 bytes |
paul@136 | 227 | |
paul@136 | 228 | The kseg2 region thus permits 256 tasks occupying 0x40000000 bytes. |
paul@136 | 229 | |
paul@136 | 230 | However, for more modest address spaces occupying as much as 32MB there |
paul@136 | 231 | would be... |
paul@136 | 232 | |
paul@136 | 233 | an address space of 0x02000000 requiring... |
paul@136 | 234 | |
paul@136 | 235 | 0x02000000 / (8 * 1024) == 0x02000000 >> 13 |
paul@136 | 236 | == 4096 entries |
paul@136 | 237 | == 0x1000 entries |
paul@136 | 238 | |
paul@136 | 239 | Thus, each task's entries would only require... |
paul@136 | 240 | |
paul@136 | 241 | 0x1000 * 8 == 0x8000 bytes |
paul@136 | 242 | */ |
paul@136 | 243 | |
paul@136 | 244 | u32 base = page_table + page_table_task_size * asid; |
paul@136 | 245 | |
paul@136 | 246 | /* Each page table entry corresponds to a pair of 4KB pages and holds two values. */ |
paul@136 | 247 | |
paul@136 | 248 | u32 entry = ((virtual & 0xffffe000) >> 13) * 8; |
paul@136 | 249 | u32 address = base + entry; |
paul@136 | 250 | |
paul@136 | 251 | /* The page tables should be permanently mapped to avoid hierarchical TLB miss handling. */ |
paul@136 | 252 | |
paul@136 | 253 | asm volatile( |
paul@136 | 254 | "sw %1, 0(%0)\n" |
paul@136 | 255 | "sw %2, 4(%0)\n" |
paul@136 | 256 | : |
paul@136 | 257 | : "r" (address), "r" (lower), "r" (upper) |
paul@136 | 258 | ); |
paul@136 | 259 | } |
paul@136 | 260 | |
paul@117 | 261 | void map_page(u32 virtual, u32 physical, u32 pagesize, u8 flags, u8 asid) |
paul@113 | 262 | { |
paul@130 | 263 | u32 start = (virtual & 0xffffe000) | asid; /* VPN2 | ASID*/ |
paul@116 | 264 | u32 lower = ((physical & 0xfffff000) >> 6) | flags; |
paul@116 | 265 | u32 upper = (((physical + pagesize) & 0xfffff000) >> 6) | flags; |
paul@113 | 266 | u32 pagemask = ((pagesize - 1) & 0xfffff000) << 1; |
paul@113 | 267 | |
paul@113 | 268 | asm volatile( |
paul@113 | 269 | "mtc0 %3, $5\n" /* CP0_PAGEMASK */ |
paul@83 | 270 | |
paul@83 | 271 | /* Set physical address. */ |
paul@83 | 272 | |
paul@113 | 273 | "mtc0 %0, $2\n" /* CP0_ENTRYLO0 */ |
paul@113 | 274 | "mtc0 %1, $3\n" /* CP0_ENTRYLO1 */ |
paul@83 | 275 | |
paul@83 | 276 | /* Set virtual address. */ |
paul@83 | 277 | |
paul@113 | 278 | "mtc0 %2, $10\n" /* CP0_ENTRYHI */ |
paul@83 | 279 | "nop\n" |
paul@83 | 280 | |
paul@113 | 281 | "tlbwr\n" |
paul@113 | 282 | "nop" |
paul@113 | 283 | : |
paul@113 | 284 | : "r" (lower), "r" (upper), "r" (start), "r" (pagemask) |
paul@113 | 285 | ); |
paul@73 | 286 | } |
paul@114 | 287 | |
paul@135 | 288 | void map_page_miss(u32 physical, u32 pagesize, u8 flags) |
paul@135 | 289 | { |
paul@135 | 290 | u32 lower = ((physical & 0xfffff000) >> 6) | flags; |
paul@135 | 291 | u32 upper = (((physical + pagesize) & 0xfffff000) >> 6) | flags; |
paul@135 | 292 | u32 pagemask = ((pagesize - 1) & 0xfffff000) << 1; |
paul@135 | 293 | |
paul@135 | 294 | asm volatile( |
paul@135 | 295 | "mtc0 %2, $5\n" /* CP0_PAGEMASK */ |
paul@135 | 296 | |
paul@135 | 297 | /* Set physical address. */ |
paul@135 | 298 | |
paul@135 | 299 | "mtc0 %0, $2\n" /* CP0_ENTRYLO0 */ |
paul@135 | 300 | "mtc0 %1, $3\n" /* CP0_ENTRYLO1 */ |
paul@135 | 301 | "nop\n" |
paul@135 | 302 | |
paul@135 | 303 | "tlbwr\n" |
paul@135 | 304 | "nop" |
paul@135 | 305 | : |
paul@135 | 306 | : "r" (lower), "r" (upper), "r" (pagemask) |
paul@135 | 307 | ); |
paul@135 | 308 | } |
paul@135 | 309 | |
paul@117 | 310 | void unmap_page(u32 virtual, u32 physical, u32 pagesize, u8 flags, u8 asid) |
paul@117 | 311 | { |
paul@130 | 312 | u32 start = (virtual & 0xffffe000) | asid; /* VPN2 | ASID*/ |
paul@117 | 313 | u32 lower = ((physical & 0xfffff000) >> 6) | flags; |
paul@117 | 314 | u32 upper = (((physical + pagesize) & 0xfffff000) >> 6) | flags; |
paul@117 | 315 | u32 pagemask = ((pagesize - 1) & 0xfffff000) << 1; |
paul@117 | 316 | u32 index = 0; |
paul@117 | 317 | |
paul@117 | 318 | asm volatile( |
paul@117 | 319 | "mtc0 %4, $5\n" /* CP0_PAGEMASK */ |
paul@117 | 320 | |
paul@117 | 321 | /* Set physical address. */ |
paul@117 | 322 | |
paul@117 | 323 | "mtc0 %1, $2\n" /* CP0_ENTRYLO0 */ |
paul@117 | 324 | "mtc0 %2, $3\n" /* CP0_ENTRYLO1 */ |
paul@117 | 325 | |
paul@117 | 326 | /* Set virtual address. */ |
paul@117 | 327 | |
paul@117 | 328 | "mtc0 %3, $10\n" /* CP0_ENTRYHI */ |
paul@117 | 329 | "nop\n" |
paul@117 | 330 | |
paul@117 | 331 | /* Find an existing mapping. */ |
paul@117 | 332 | |
paul@117 | 333 | "tlbp\n" |
paul@117 | 334 | "nop\n" |
paul@117 | 335 | |
paul@117 | 336 | /* Read the index register to see if a match was found. */ |
paul@117 | 337 | |
paul@117 | 338 | "mfc0 %0, $0\n" /* CP0_INDEX */ |
paul@117 | 339 | "nop" |
paul@117 | 340 | : "=r" (index) |
paul@117 | 341 | : "r" (lower), "r" (upper), "r" (start), "r" (pagemask) |
paul@117 | 342 | ); |
paul@117 | 343 | |
paul@117 | 344 | /* Return if the page is not mapped. */ |
paul@117 | 345 | |
paul@117 | 346 | if (index & 0x80000000) |
paul@117 | 347 | return; |
paul@117 | 348 | |
paul@117 | 349 | /* Otherwise, invalidate the mapping. */ |
paul@117 | 350 | |
paul@117 | 351 | map_page_index(virtual, physical, pagesize, flags & 0xfd, asid, index); |
paul@117 | 352 | } |