NanoPayload

Annotated stage2/cpu.c

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2016-05-04 Paul Boddie file changeset files shortlog Moved almost all assembly language fragments into a separate file.
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/*
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 * CPU-specific routines originally from U-Boot.
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 * See: uboot-xburst/files/arch/mips/cpu/xburst/cpu.c
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 * See: u-boot/arch/mips/include/asm/cacheops.h
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 *
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 * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
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 * Copyright (C) 2015, 2016 Paul Boddie <paul@boddie.org.uk>
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 *
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 * This program is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU General Public License as
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 * published by the Free Software Foundation; either version 2 of
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 * the License, or (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 *
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 * You should have received a copy of the GNU General Public License
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 * along with this program; if not, write to the Free Software
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 * Foundation, Inc., 51 Franklin Street, Fifth Floor,
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 * Boston, MA  02110-1301, USA
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 */
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#include "cpu.h"
 
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#include "cpu_op.h"
 
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#include "sdram.h"
 
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#include "paging.h"
 
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void flush_icache_all(void)
 
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{
 
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	u32 addr;
 
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	flush_icache_tag();
 
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	for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_ICACHE_SIZE; addr += CONFIG_SYS_CACHELINE_SIZE)
 
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		flush_icache_region(addr);
 
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	flush_icache_config();
 
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}
 
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void flush_dcache_all(void)
 
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{
 
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	u32 addr;
 
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	for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE; addr += CONFIG_SYS_CACHELINE_SIZE)
 
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		flush_dcache_region(addr);
 
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	asm volatile ("sync");
 
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}
 
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void flush_cache_all(void)
 
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{
 
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	flush_dcache_all();
 
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	flush_icache_all();
 
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}
 
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void init_registers(u32 *base, u32 got, void (*function)(), u32 args[], u8 nargs)
 
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{
 
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	u8 i;
 
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	/* Provide arguments to the function. */
 
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	for (i = 0; i < nargs; i++)
 
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	{
 
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		base[i+4] = args[i];
 
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	}
 
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	/* Store essential data for the function environment. */
 
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	base[25] = (u32) function - 0x80000000;	/* store the function address as t9 */
 
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	base[26] = got - 0x80000000;		/* store the global pointer */
 
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	base[29] = (u32) function - 0x80000000;	/* store the function address as EPC (for the handler) */
 
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}
 
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void init_tlb(void)
 
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{
 
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	u32 limit = configure_tlb(), i;
 
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	/* Reset the mappings. The total number is bits 30..25 of Config1. */
 
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	for (i = 0; i < ((limit >> 25) & 0x3f); i++)
 
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	{
 
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		map_page_index(0, 0, 4096, 0, 0, i);
 
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	}
 
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}
 
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void map_page_index(u32 virtual, u32 physical, u32 pagesize, u8 flags, u8 asid, u32 index)
 
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{
 
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	u32 start = (virtual & 0xffffe000) | asid; /* VPN2 | ASID*/
 
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	u32 lower = ((physical & 0xfffff000) >> 6) | flags;
 
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	u32 upper = (((physical + pagesize) & 0xfffff000) >> 6) | flags;
 
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	u32 pagemask = ((pagesize - 1) & 0xfffff000) << 1;
 
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	map_page_set_index(index);
 
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	map_page_index_op(lower, upper, start, pagemask);
 
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}
 
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void init_page_table(u32 page_table, u32 virtual, u32 physical, u32 pagesize, u8 flags, u8 asid)
 
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{
 
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	u32 lower = ((physical & 0xfffff000) >> 6) | flags;
 
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	u32 upper = (((physical + pagesize) & 0xfffff000) >> 6) | flags;
 
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	/*
 
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	With a complete address space mapping involving pairs of 4KB pages
 
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	described by two values for each entry, there would be...
 
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	an address space of 0x100000000 requiring...
 
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	0x100000000 / (8 * 1024) == 0x100000000 >> 13
 
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	== 524288 entries
 
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	== 0x80000 entries
 
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	Thus, each task's entries would require...
 
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	0x80000 * 8 == 0x400000 bytes
 
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	The kseg2 region thus permits 256 tasks occupying 0x40000000 bytes.
 
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	However, for more modest address spaces occupying as much as 32MB there
 
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	would be...
 
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	an address space of 0x02000000 requiring...
 
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	0x02000000 / (8 * 1024) == 0x02000000 >> 13
 
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	== 4096 entries
 
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	== 0x1000 entries
 
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	Thus, each task's entries would only require...
 
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	0x1000 * 8 == 0x8000 bytes
 
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	*/
 
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	u32 base = page_table + page_table_task_size * asid;
 
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	/* Each page table entry corresponds to a pair of 4KB pages and holds two values. */
 
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	u32 entry = ((virtual & 0xffffe000) >> 13) * 8;
 
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	u32 *address = (u32 *) (base + entry);
 
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	/* The page tables should be permanently mapped to avoid hierarchical TLB miss handling. */
 
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	*address = lower;
 
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	*(address + 1) = upper;
 
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}
 
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void map_page(u32 virtual, u32 physical, u32 pagesize, u8 flags, u8 asid)
 
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{
 
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	u32 start = (virtual & 0xffffe000) | asid; /* VPN2 | ASID*/
 
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	u32 lower = ((physical & 0xfffff000) >> 6) | flags;
 
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	u32 upper = (((physical + pagesize) & 0xfffff000) >> 6) | flags;
 
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	u32 pagemask = ((pagesize - 1) & 0xfffff000) << 1;
 
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	map_page_op(lower, upper, start, pagemask);
 
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}